An 8-Gbps, Low-Jitter, Four-Channel Transmitter with a Fractional-Spaced Feed-Forward Equalizer

Abstract

An 8 gigabits per second (Gbps), low-jitter, four-channel transmitter with fractional-spaced feed-forward equalizer (FFE) is designed to meet the demand for broad transmission bandwidth in serial data communications. A novel frequency divider chain (FDC) architecture is developed, to satisfy the time requirements for high-speed data serialization. Moreover, a reconfigurable output driver circuit is employed to ensure compatibility with different protocols. In addition, a three-tap fractional-spaced FFE, which can enhance signal bandwidth significantly, is proposed, to compensate for channel loss. The transmitter was simulated and validated based on the Semiconductor Manufacturing International Corporation (SMIC) 55-nm process. The post-layout simulation results show the following: The tuning range of the phase-locked loop (PLL) can cover 1.6 to 4.6 GHz. At an output frequency of 4 GHz, the root-mean-square jitter (RJ) of the PLL after integration from phase noise was 1.93 ps. With an 8 Gbps output data rate, using the pseudo-random binary sequence (PRBS)-31 as a data source to simulate the whole transmitter, the power consumption values of the PLL and drive circuit were 27.0 and 29.2 mW, respectively, and the eye width and the valid eye height of output data were 0.76 unit interval (UI) and 0.68.

1. Introduction

High-speed serializer/de-serializer (SerDes) technology is extensively employed to improve the data transmission performance of wireline transmission systems [1]. Due to the continuous development of data-intensive services, such as the Internet of Things, cloud computing, and cloud storage, telecommunication infrastructure is required to be upgraded; therefore, the requirements for the data transmission rate of SerDes should be increased [2,3,4,5]. Therefore, the transmitter of SerDes must provide a high-speed data transfer rate and maintain the signal integrity, which is the main problem faced in the design.

A SerDes transmitter generally consists of two parts: a phase-locked loop (PLL), and a driver. The function of the PLL is to provide stable and high-accuracy clock signals [6,7,8]. Meanwhile, correct output data and sufficient signal swing are required for the driver [9,10]. From an application perspective, the driver needs to conform to different protocols. Moreover, because the integrity of high-speed signals is often affected by the channel loss of the transmission line, a feed-forward equalizer (FFE) is usually used in the driver, to compensate for channel loss [11,12,13]. In general, a baud-spaced FFE is usually used. However, the peak frequency of the baud-spaced FFE’s frequency response is the Nyquist frequency of the output data rate. Compared with the baud-spaced FFE, a fractional-spaced FFE can improve the peak frequency significantly; therefore, increasing the signal bandwidth after equalization. As a result, a fractional-spaced FFE can reduce signal aliasing effectively, and improve the integrity and performance of the equalized signal [14,15].

Against the above research background, in this article, we present a low-cost, low-power-consumption, low-jitter, four-channel SerDes transmitter that can transmit data at 8 gigabits per second (Gbps) and is compatible with multiple transmission protocols. The transmitter contains a type-II fourth-order PLL, which can provide a differential clock with high speed and low jitter. The multiplexers (MUXs) in the driver serialize 32-bit data. Moreover, a novel frequency divider chain (FDC) architecture is designed to satisfy the time requirements for high-speed serialization, with applicability for higher-speed transmitter architectures. Furthermore, a reconfigurable output driver that conforms to multiple protocols is developed. Finally, a three-tap fractional-spaced FFE is used to compensate for channel loss, which can enhance the signal bandwidth significantly.

This paper is organized as follows: Section 1 presents the introduction. Section 2 introduces the top architecture of the presented transmitter. Section 3 and Section 4 provide the circuit design implementation and details of the PLL and driver, respectively. The simulation results and discussions are given in Section 5. Finally, the conclusions are summarized in Section 6.

2. Top Architecture

Figure 1 shows a block diagram of the designed transmitter system.

A fourth-order PLL is adopted in the transmitter, which can enhance the ability to suppress the noise of vcon at high frequency, with a small price of chip area, and will not have a prominent influence on the PLL’s phase margin (vcon is the input voltage of the voltage-controlled oscillator (VCO)). Low-dropout regulators (LDOs) are used to supply power and reduce clock jitter. To fully satisfy the time requirements for the flip-flops (FFs) in the MUXs during high-speed applications, a novel clock FDC architecture is developed to divide the frequency of the clock signal output by the PLL. The frequency-divided clocks serve as a reference clock signal for a 32-to-1 MUX, while another 1/16-frequency-divided clock is input as a reference clock into a digital module. An encoder is used to generate 32-bit parallel data or pseudo-random binary sequence (PRBS) signals that are subsequently input into the transmitter for serialization. First, the 32-to-2 MUX transforms the parallel data to an odd data stream D_ODD and an even data stream D_EVEN, and subsequently inputs them into a latch array and delay block, to generate a main cursor, a fractional cursor that is fractional unit interval (UI) behind the main cursor, and a postcursor that is one UI behind the main cursor. The proportion of the main-cursor, fractional cursor, and post cursor can be programmed to change the output swing of the transmitter, and to modify the range of de-emphasis, to compensate for the attenuation introduced by the different channels.

3. PLL Circuit Implementation

Figure 2 shows a block diagram of the designed PLL. The PLL consists of a predivider (PD), a phase frequency detector (PFD), a charge pump (CP), a third-order loop-filter (LPF), a ring VCO, a loop divider, and an output divider (OD).

An adjustable reset delay module is added to the PFD to eliminate the dead-zone effects with different sets of process–voltage–temperature (PVT) conditions. The CP uses two rail-to-rail operational amplifiers to reduce the drain-voltage fluctuations in the metal-oxide-semiconductor field-effect transistor (MOSFET) in the current supply, with the goal of mitigating the mismatch between the charge and discharge currents introduced by channel-length modulation [16]. Moreover, a ring VCO architecture is adopted to reduce the chip area and cost, while providing a broadband tuning range [17]. The PD and OD divide the frequency of the reference and output clocks, respectively, to expand the output frequency band of the PLL [18]. A two-stage LDO regulator chain is used to supply power to the components of the PLL. An LDO regulator with an output voltage of 1.8 V is used to supply power to the VCO alone. The CP, PFD, divider (DIV), and OD are high-frequency modules that operate at different frequencies. Therefore, to reduce the clock jitter caused by power-supply fluctuations, three LDO regulators with an output voltage of 1.2 V are used to supply power to these components [19].

4. Driver Circuit Implementation

4.1. MUXs

MUXs in transmitters are responsible for transforming parallel data to high-speed serial data. The designed 32-to-1 MUX features a tree-shaped half-rate architecture, to reduce the timing constraints of the high-speed path [20], as shown in Figure 3.

For a half-rate architecture, the clock duty cycle (CDC) affects the output-signal jitter and, thus, needs to be corrected using a duty cycle corrector. The input of the high-speed clock output by the PLL into the clock frequency divider module generates 0-, 1/2-, 1/4-, 1/8-, and 1/16-frequency-divided differential clocks. These five pairs of clock s are successively used as the sampling clocks for different layers of the tree-shaped architecture, to serialize the parallel data level-by-level with the 2-to-1 MUX in Figure 4 as a basic unit.

As seen in Figure 4, the 2-to-1 MUX is composed of three D FFs (DFFs) and one selector. One data stream, Da, is sampled to point A at the rising edge of the CLK. Another data stream, Db, is sampled to point B at the rising edge of the CLK and subsequently sampled by a DFF to point C at the rising edge of the $\overline{\mathrm{CLK}}$. Therefore, point C is half a clock cycle behind point A. Finally, the selector outputs point C (Db) during a positive half cycle of CLK and point A (Da) during a negative half cycle of CLK, to double the data rate. An additional cross-coupled pair are included to prevent charge leakage in the low-speed MUX. The 32-to-2 MUX transforms the parallel data to D_ODD and D_EVEN, which are subsequently passed through the latch array and the delay block to output the main cursor, fractional cursor, and post cursor. These cursors are ultimately input into the driver, to compensate the channel loss.

4.2. Clock FDC Architecture

In high-speed mode, the 2-to-1 MUX needs to fully meet the setup and hold time (T_ST and T_HD, respectively) requirements of the DFFs, to prevent errors [21]. A clock FDC architecture is developed in this study, as shown in Figure 5a. Figure 5b shows the corresponding timing diagram.

First, the PLL outputs a half-rate clock (CLKO). The CLKO is then buffered by a two-stage phase-inverter chain, to produce CLK1, then by a one-stage divide-by-two divider and a four-stage phase-inverter chain, to produce CLK2. The signal at the midpoint of the four-stage phase-inverter chain is input into the subsequent one-stage divide-by-two divider. The above process is then repeated. Ultimately, five clocks, CLK1, CLK2, CLK4, CLK8, and CLK16, are obtained. Let T_CTD and T_INV be the time delay of a one-stage divide-by-two divider and the time delay of a one-stage phase inverter, respectively. Then, the time delay of each CLK relative to the preceding CLK is calculated as follows:

$$T_{DELAY}=T_{CTD}+4T_{INV}-2T_{INV}=T_{CTD}+2T_{INV}.$$

(1)

For the 2-to-1 MUX in Figure 4, the time delay between the data at point O and the data at point A or C is equivalent to the time delay of the selector, T_SEL. In addition, the initial data are generated by the digital module, with CLK16 as a reference clock, and have a width equivalent to the CLK16 cycle. The 2-to-1 MUX selects one out of the two data streams. This process requires CLK(2N) to be first used for selection. After T_SEL, the selected data stream is sent to the subsequent 2-to-1 MUX for sampling. The width of the sampled data stream is half the CLK(2N) cycle. Here, the sampling of data stream D0 is used as an example. At a low voltage of CLK16, CLK16 selects D0 and outputs D0₈ after T_SEL. CLK8 then samples D0₈. In this process, T_ST8 = (16 UI − T_DELAY − T_SEL), and T_HD8 = (T_DELAY + T_SEL). Similarly, at a low voltage of CLK8, CLK8 selects D0₈ and outputs D0₄ after T_SEL. Hence, when CLKN is used to sample D0_N, the DFF obtains the following T_STN and T_HDN:

$$T_{STN}=(2N)\ast T_{1UI}-T_{DELAY}-T_{SEL},$$

(2)

$$T_{HDN}=T_{DELAY}+T_{SEL}.$$

(3)

T_CTD, T_INV, and T_SEL reach maximum values (67, 20, and 35 ps, respectively) under the worst PVT condition (at slow corner, 125 °C, and 1.08 V supply). Thus, based on Equation (1), the maximum T_DELAY is 107 ps. At the maximum transmitter rate, the duration of one UI, T_1UI, is 125 ps. Under the worst PVT condition, the maximum T_ST and T_HD required by the DFF are 69 and 12 ps, respectively. Analysis of Equation (2) reveals that the DFF achieves the minimum T_ST at N = 1. Therefore, the minimum T_ST and T_HD achieved by the DFF are 108 and 142 ps, respectively, suggesting a sufficient time margin. The worst case scenario is considered in the above analysis. Under a normal PVT condition (at typical corner, 50 °C, and 1.2 V supply), T_CTD, T_INV, and T_SEL are 40, 15, and 25 ps, respectively, while the maximum T_ST and T_HD required by the DFF are 40 and 8 ps, respectively. The use of this FDC architecture allows an even larger time margin (a T_ST of 155 ps and a T_HD of 95 ps) for the DFF.

The value of each time-delay parameter of the design presented in this study is relatively high, due to the use of the Semiconductor Manufacturing International Corporation (SMIC)-55-nm process, and can be reduced by using a more advanced process. Therefore, this architecture can be applied to higher-speed transmitters. In summary, the proposed clock FDC architecture can not only fully satisfy the time (T_ST and T_HD) requirements of high-speed DFFs in 2-to-1 MUXs, but can also be used in higher-speed transmitter architectures.

4.3. Output Driver Circuit

The designed output driver circuit includes a predriver circuit and a reconfigurable output driver circuit, as shown in Figure 6. For simplicity, the predriver circuit is shown as a half-side circuit. The predriver circuit takes the output of the 32-to-1 MUX as input; and after the predriver circuit, the differential data are input to the reconfigurable driver circuit. The differential main cursor is input into M₅, and M₆, and the differential fractional cursor and post cursor are input into M₇ and M₈.

4.3.1. Predriver Circuit

An output driver circuit is required to drive a very high load. Therefore, a current mode (CM) driver needs a predriver circuit, to ensure its driving capacity. In this study, the inverse proportional method is employed to design a predriver circuit, to obtain a good trade-off between power consumption and bandwidth.

4.3.2. Reconfigurable Output Driver Circuit

A reconfigurable output driver circuit prototype, as shown in Figure 6, is designed to ensure compatibility with protocols such as High-Definition Multimedia Interface (HDMI) 2.0b and Peripheral Component Interconnect (PCI) Express 3.1. HDMI 2.0b is a relatively special protocol, in that it requires the receiver end to supply a voltage of 3.3 V and a pull-up resistor. The switches in Figure 6 are ideal, because the parasitic of the switches will degrade the performance of the driver. Satisfying the HDMI 2.0b protocol requires switches S₁ to be closed and switches S₂ and R_SIN to be taken out. After this operation, the two differential resistors (R_DIFF) connected in series serve as a 100-Ω transmission-line matching resistor, while TX_OUTP and TX_OUTN function as the data output end of the transmitter. As the receiver end supplies a voltage of 3.3 V, use of a conventional CM driver can lead to an overly high drain voltage for the input pair transistors, which in turn causes transistor breakdowns and circuit failure. Therefore, thick-gate transistors, M₁–M₄, need to be added to the input pair transistors, with the goal of reducing the drain voltage of the input transistors and preventing transistor failure.

The PCI Express 3.1 protocol requires a power supply and a pull-up resistor to be provided on chip and the data to be output below the pull-up resistor. To satisfy this protocol, it is necessary to close switches S₂ and take out switches S₁, R_DIFF and M₁–M₄. This operation allows the 50-Ω R_SIN to function as a pull-up resistor and a transmission-line matching resistor.

4.3.3. Three-Tap Fractional-Spaced FFE

A three-tap fractional-spaced FFE is presented for channel equalization. The three taps are the main-cursor, fractional-cursor, and post-cursor, respectively. The block diagram and the schematic of the three-tap fractional-spaced FFE are shown in Figure 7a,b, respectively, where dT_UI is the delay time of the fractional-cursor relative to the main-cursor, and m is the proportion of the fractional-cursor relative to the main-cursor.

It can be ratiocinated from Figure 7 that the relationship between y(t) and x(t) is:

$$y(t)=x(t)-mx(t-d{T}_{UI}),$$

(4)

after Laplace transformation of Equation (4), the relationship between Y(s) and X(s) in the s domain can be obtained:

$$H(s)=\frac{Y(s)}{X(s)}=1-m{e}^{-d{T}_{UI}s},$$

(5)

then calculating the magnitude of H(s), we can obtain:

$$\left|H(\omega )\right|=\sqrt{1+m^2-2m\cos (d\omega T_{UI})}.$$

(6)

Equation (6) shows that |H(ω)| is a periodic function for ω, and its period is 2π/(dT_UI). When (dωT_UI) equals π, which means ω equals π/(dT_UI), |H(ω)| reaches the first maximum value, so the frequency f_peak here is:

$$f_{peak}=1/(2d{T}_{UI})=f_{Nyquist}/d.$$

(7)

Equation (7) suggests that by decreasing the coefficient d of the fractional-spaced FFE, the peak frequency of the FFE frequency response can be increased to the Nyquist frequency divided by d. Therefore, the compensable frequency can be enhanced significantly.

To verify the deduction above, a first order low-pass filter with a 3 dB bandwidth of 1.5 GHz is used to simulate the channel loss [22,23]. The bode diagram of the channel model is shown in Figure 8.

Channel equalization requires that the compensated frequency response amplitude remains flat within the band, which means it cannot be over-compensated. From this premise, the max m is chosen for different d manually. When m is smaller, the bandwidth will be degraded. When m is larger, the frequency response will introduce a peak. Hence, the m chosen for different d is the optimal value in terms of bandwidth. Therefore, each d corresponds to a specific m. Figure 9 shows the frequency response of the cascaded fractional-spaced FFE and channel.

It can be seen from Figure 9 that, as d decreases, the bandwidth of the compensated signal (BW) increases, but the low-frequency gain (Gain) decreases. Therefore, the cost of the increase in BW is the decrease in Gain. That is, in the case of the same power consumption, the bandwidth of the signal can be increased by the fractional-spaced FFE, but the output swing of the signal will be reduced.

Based on the 500 mV output swing after compensation (in the case of no attenuation, the 500 mV output swing corresponds to 5 mA pull-down current), use the ratio of BW and power consumption (set as BOP) to define the trade-off between bandwidth and power consumption corresponding to different d. The total required current at a specific d is:

$$I_{TOTAL}=I_{MAIN}+I_{FRAC}=(5 \mathrm{mA})\frac{1+m}{1-m},$$

(8)

where the relationship between Gain and m is:

$$Gain(\mathrm{dB})=20{\log }_{10}(1-m).$$

(9)

Then combining Equations (8) and (9), the value of BOP can be obtained as:

$$BOP(\mathrm{GHz}/\mathrm{mA})=\frac{BW}{I_{TOTAL}}=\frac{{10}^{(Gain/20)}}{(2-{10}^{(Gain/20)})(5 \mathrm{mA})}BW.$$

(10)

We know that each d corresponds to a specific m, so the relationship between d, BW, and Gain is constructed. Therefore, each group of d corresponds to a specific BOP from Equation (10). Since BW and Gain should be as large as possible, the BOP should be as large as possible as well.

Based on the situation discussed above, the curve of BOP versus d is obtained, as shown in Figure 10.

This suggests that when using a fractional-spaced FFE to compensate the channel, BOP is the biggest when d is 0.5. Hence, a good compromise can be achieved between power consumption and bandwidth when d is 0.5 in this situation.

The group delay of the cascaded fractional-spaced FFE and channel with the variation of d is shown in Figure 11.

The group delay is the measure of the time delay of each frequency component of the signal passing through the system. To achieve signal transmission without distortion, the group delay should be constant. Figure 11 shows that with different d, the group delay is the constant at low frequency, and changes a lot when utilizing a higher frequency. Therefore, the max frequency of the constant group delay is set to define the degree of change of group delay with frequency. Compared with the initial constant group delay, a 5 ps variation is set to define the max frequency of constant group delay. The max frequency of constant group delay with different d is shown in Figure 11. This suggests that the fractional-spaced FFE can enhance the max frequency of the constant group delay.

Figure 12 shows the output eye diagrams with 500 mV output swing when d is 0.5 and 1, respectively. When d is 0.5, m is 0.56; while, when d is 1, d is 0.3.

Due to the increase in bandwidth, the eye height is 500 mV when d is 0.5, which is obviously better than the eye height of 370 mV when d is 1. Meanwhile, the deterministic jitter (DJ) is reduced from 4.5 to 1.5 ps. Data-dependent jitter (DDJ) is the prominent part of DJ, and DDJ is caused by threshold-crossing time deviations correlated to the previous data bits on the current data bit. As the transmitted data is produced by a particular pattern, there is insufficient bandwidth to preserve the memory of the previous data, and this will harm future data transitions [24,25]. Hence, the increased signal bandwidth will decrease DJ. As a consequence, the fractional-spaced FFE greatly improves the quality of the eye diagram and the integrity of the signal. For different channels, the BOP can be used to trade off between power consumption and output signal bandwidth, thereby compensating for different situations.

A fractional cursor is produced by the main cursor after the delay block. The block diagram of the delay block is shown in Figure 13.

The delay time is coarsely tuned by a parallel capacitor array, and finely tuned by an adjustable varactor. The delay block is placed before the single-differential converter (S2D). Compared with the case where the delay block is placed in the clock chain, the varactor diode and capacitor array used in this design are halved, which can reduce the chip area [22]. Since d is very small, the power consumption is very large, which is not conducive to a low-power design; thus, the case when d is less than 0.4 can be ignored. Under different control words of capacitance, the variation of the delay time versus Vctrl under three different PVT conditions is shown in Figure 14.

Due to the delay time variation from PVT, the effective delay time is the intersecting part of three PVT conditions, which range from 50 to 105 ps. As a result, the delay block can provide delay time ranges from 0.4 to 0.8 UI.

5. Simulation Results and Discussions

The designed transmitter was implemented and validated based on the SMIC-55-nm process. Figure 15 shows a photograph of the layout of the designed transmitter. The PLL and single-channel driver were 350 μm × 380 μm (0.133 mm²) and 250 μm × 300 μm (0.075 mm²) in area, respectively. Clock-shielding, virtual-device, protection-ring, and central-symmetry layout techniques were employed to implement the high-speed signal wiring and modules.

Figure 16 shows the frequency tuning range of the VCO in the PLL under three different PVT conditions. For a 8 Gbps data rate, the frequency of clock signal should be 4 GHz. Figure 16 suggests that under every PVT condition, the VCO can provide a tuning range that ranges from 1.6 to 4.6 GHz. The OD can be used to further expand the low-frequency output range and provide a broadband clock signal for the transmitter.

Figure 17 shows the phase–noise curve of the PLL at an output frequency of 4 GHz. The phase noise values of the PLL are −92 and −94 dBc/Hz at in-band frequency offsets of 100 kHz and 1 MHz, respectively, and −112 dBc/Hz at an out-of-band frequency offset of 10 MHz. The PLL exhibited a good jitter performance, as evidenced by a root-mean-square jitter of 1.93 ps in 4-GHz output clock after integration of total phase noise.

The transmitter was simulated as a whole at an operating transmission rate of 8 Gbps. In terms of power consumption, the PLL and driver consumed 27.0 and 29.2 mW of power, respectively. The 27.0 mW power consumption of the PLL includes all five LDOs. For each LDO, the power consumption was as follows: The power consumption of the LDO for VCO was 12.3 mW; the power consumption of the LDO for the second stage was 13.4 mW, which includes the power consumption of the second stage LDOs (0.9 mW for the LDO for CP, 1.8 mW for the LDO for PFD, and DIV, 4.6 mW for the LDO for OD).

Figure 18 shows the differential insertion loss curve of the line model used in the simulation. At an operating transmission rate of 8 Gbps, the Nyquist frequency and insertion loss were 4 GHz and −8.05 dB, respectively.

The transmitter was simulated with PRBS-31 code as data source. The output swing was ±300 mV. Figure 19 shows the output eye diagram of the transmitter without FFE under the typical corner, 50 °C and 1.2 V supply. The excessive inter-symbol interference resulted in a highly distorted eye diagram.

Figure 20 shows the output eye diagram of the transmitter equipped with baud-spaced FFE under typical corner, 50 °C and 1.2 V supply. The eye height is 340 mV. Here, a bit error ratio lower than 10⁻¹² is used as a criterion. In total, the PLL introduces a jitter of 28 ps. The eye width of the eye diagram of the whole transmitter is 0.69 UI.

Figure 21 shows the output eye diagram of the transmitter equipped with a fractional-spaced FFE under a typical corner, 50 °C and 1.2 V supply. The eye height and the eye width of the output data were 470 mV and 0.76 UI, respectively. Due to the enhancement of bandwidth by the fractional-spaced FFE, under the same output swing, the eye height was increased by 130 mV, and the total jitter was decreased by 8 ps. The verification results show the effectiveness and feasibility of the proposed fractional-spaced FFE.

Table 1. Comparison of the valid eye height and eye width with fractional-spaced FFE under nine PVT conditions.

Process	Supply Voltage (V)	Temperature (°C)	Valid Eye Height 1	Eye Width (UI)
Typical		−25	0.81	0.76
	1.2	50	0.78	0.76
		125	0.74	0.74
Fast		−25	0.83	0.77
	1.32	50	0.79	0.76
		125	0.78	0.76
Slow		−25	0.75	0.72
	1.08	50	0.72	0.72
		125	0.68	0.71

¹ Valid eye height = eye height/output swing.

compares the eye height and eye width of the transmitter output data compensated by the fractional-spaced FFE under nine different PVT conditions. The valid eye height is at least 0.68, due to the attenuation of MOSFET speed caused by the slow corner, 125 °C and 1.08 V supply. The eye width is at least 0.71 UI without much change, because the jitter is mainly caused by the RJ introduced by the PLL.

Table 2. Performance comparison and summary.

	This Work 1	[1] 2	[2] 2	[9] 2	[11] 2
CMOS Technology (nm)	55	65	65	65	55
Data Rate (Gbps)	8	6	10	10	8
Power 3 (mW)	29.2	33.6	72.0	36.0	15.1
Energy Efficiency 4 (mW/Gbps)	3.65	5.60	7.20	3.60	1.89
Eye Width	0.71	0.65	0.70	0.58	0.52
Valid Eye Height	0.68	0.32	0.63	0.35	0.52
FFE Tap	3	2	4	2	3
Type of FFE	Fractional-spaced	Baud-spaced	Baud-spaced	Baud-spaced	Baud-spaced

¹ Simulated result. ² Measured result. ³ The power is for a single lane of the transmitter. ⁴ Energy Efficiency (mW/Gbps) = Power/Data Rate.

compares the transmitter presented in this paper with recent transmitters that were fabricated with a similar CMOS technology and operating at a similar data rate. The transmitter in this article has a relatively low power consumption. Meanwhile, the proposed transmitter outputs data with low jitter. Moreover, this paper proposes a three-tap fractional-spaced FFE to equalize the channel loss, which can notably increase the valid eye height.

6. Conclusions

An 8-Gbps, low-jitter, four-channel transmitter equipped with a three-tap fractional-spaced FFE was designed in this study. The PLL can provide a differential clock with high speed and low jitter. A 32-to-1 MUX was also designed to serialize 32-bit data. Moreover, a novel FDC architecture was developed to satisfy the time requirements for high-speed data serialization, with applicability for higher-speed transmitter architectures. A reconfigurable output driver was put forward, to ensure compatibility with multiple protocols. Finally, a three-tap fractional-spaced FFE was employed to compensate for channel loss. The fractional-spaced FFE can overcome the shortcoming that the peak frequency of the baud-spaced FFE frequency response can only reach the Nyquist frequency; hence, it can enhance the signal bandwidth observably, thereby improving signal integrity and performance. The validation results showed that the PLL can provide differential clock up to 4 GHz, and the RJ is 1.93 ps at this rate; therefore, the jitter performance is good. At 8-Gbps, PRBS-31 was used as data source to simulate the whole transmitter. The energy efficiency of the driver stage was 3.65 mW/Gbps. Moreover, the fractional-spaced FFE could effectively improve the signal integrity of the output data. After channel compensation through FFE, the eye width and valid eye height of the output data were 0.71 UI and 0.68, respectively.