Receiver Analog Front-End Cascading Transimpedance Amplifier and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s

Abstract

A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance amplifier (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor R_m. A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with fixed degenerate capacitance C_S and resistance R_S. The proposed AFE achieved high bandwidth, and the use of a feedback resistor R_f and inductor L_f improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10⁻¹² for a 2³¹ − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V.

1. Introduction

As data rates have increased by 1.5 times every year since 2000, high-speed data communications are required in modern broadband applications to address bandwidth demand. Initially, in 2000, radio frequency applications required a bandwidth of 1–2 GHz for optical time-domain reflectometer applications. To meet modern broadband demand, data rates have increased to 25~30 Gbps, which is more than 75% of previous data communications. Increasing bandwidth must meet multiple challenges including channel loss, high-speed operation, area, equalization, and robustness. For data communication power, in particular, consumption is a very important factor in maintaining high performance. There are several previous studies of 28 Gbps or higher data rates [1,2,3,4,5]. Those use unrolled decision feedback equalizers to meet critical timing margins, but the unrolled CTLE structure increases the power and die’s area. To achieve these challenges, one of the key designs is an analog front-end (AFE) cascading transimpedance amplifier with a continuous-time linear equalizer.

Historically, TIAs have been mostly developed for the front-ends of the optical receivers (for example, the families of 2.5, 10, 40, … GB/s). However, their usage is not limited to optical applications, although they have been for a long time the major driving force beyond development towards both lower noise and higher speeds. Nevertheless, in recent decades, advanced TIA designs have become increasingly popular for a variety of applications such as physics and radiation detectors of particles, miniaturized magnetic resonance spectroscopy [2], and vision and biological sensors. Different applications have their own requirements for the main parameters of TIA design. For example, high-speed optical communication circuits have pushed the bandwidth of TIAs in multiple GHz ranges from novel designs with lower power consumption to reduced chip area and minimized noise while operating at significant frequency [6]. Obviously, the front-end TIA is the most critical component of the channel influencing both noise sensitivity and the speed of the overall system. At the output of the linear channel, voltage is provided that can be later used by decision circuits.

The second most critical component of the analog front-end block is the decision circuit or equalization circuit as shown in Figure 1. Equalization is typically implemented in both the transmitter and the receiver [7]. Before the channel, it is desirable to “peak” the transmitted high-frequency content instead of performing all the high-frequency peaking at the receiver side. On the receiver side, high-frequency peaking degrades the receiver input signal-to-noise ratio (SNR), whereas the transmit side does not. Therefore, within the transmitter, equalization is implemented to supply pre-emphasis of the high-frequency vanguard of bit transitions. In the receiver, equalization is implemented to revive the combined transmitter and channel characteristics towards a reference channel that has no or reduced ISI. Obviously, CTLE in a receiver is intended to equalize the combined characteristics of the transmitter and channel and remove the ISI at the received signal sampling points. The RX CTLE is similar to TX FFE CTLE except the input is an analog signal. The RX CTLE is often called a discrete-time linear equalizer [3,8]. As an FIR filter, designed to subtract ISI effects from adjacent bits. The output of RX CTLE is further sampled to point per data time interval for data detection. The RX CTLE will only cancel ISI at the data detection sample points.

Channel losses or insufficient bandwidth are obstacles to achieving higher data rates in data communications. One solution is changing the signal transformation scheme from two-level pulse amplitude modulation (PAM2), also known as non-return-to-zero (NRZ), to four-level pulse amplitude modulation (PAM4), to double the data rate without increasing the bandwidth [9,10]. However, PAM4 requires greater system linearity. Increasing system bandwidth or using a continuous-time linear equalizer (CTLE) to compensate for channel losses are other potential solutions [11,12,13].

Receivers with equalization can overcome problems caused by channel loss, such as intersymbol interference. Effective high-performance receivers must meet numerous requirements, including those for power consumption, area, bit error rate (BER), and equalization. In receiver analog front-ends (AFEs), equalizers such as CTLE are commonly used (Figure 1). CTLE has lower power consumption than other equalizers in high-speed applications. Moreover, as the data rate increases, the proposed CTLE can achieve different equalization for different cable lengths by tuning the tail current with a fixed capacitor and resistor. The architecture presented in [1] is generally used in high-speed AFEs.

Typically, transimpedance amplifiers (TIAs) are used to limit receiver noise. Common-gate stages are effective amplifiers for high frequencies but have poor noise characteristics [14,15]. The TIAs based on the shunt–feedback architecture have a low-noise topology that is advantageous for high-data-rate applications. However, a trade-off exists between the performance of the circuit and the suitability of the DC operating point in conventional linear transconductance (Gm)-TIA systems. To achieve a suitable DC operating point, the size of the transistors must be increased, resulting in a large parasitic capacitance at the output nodes and reducing the bandwidth of the circuit. To overcome this problem, source follower (SF) stages were used to design the proposed AFE. This paper is organized as follows: Section 2 details the design considerations, Section 3 presents the simulation results, and Section 4 concludes the research.

2. Design Consideration

2.1. CTLE

The equalization value of conventional CTLEs can be increased or decreased by varying the capacitor (C_S) and resistor (R_S), illustrated in the schematic in Figure 2. The peaking frequency is directly correlated with this equalization value and affects the bandwidth f_w. Consequently, disassociating the equalization value and f_w in the circuit is key. The source-degenerated Gm-cell is chosen such that the gain is degenerated through R_S, ensuring sufficient linearity in the system (Figure 2). A zero can also be introduced by combining C_S and R_S [8,16].

Equation (1) presents the transfer function of the single-ended CTLE.

$$\mathrm{H}(\mathrm{S})=\frac{G_M{R}_L}{1+\frac{G_M{R}_S}{2}}\times \frac{1+\frac{S}{{\omega }_z}}{\left(1+\frac{S}{{\omega }_{p1}}\right)\left(1+\frac{S}{{\omega }_{p2}}\right)}$$

(1)

where ${\omega }_z$=$\frac{1}{R_s{C}_s}$, ${\omega }_{p1}$=$\frac{1+\frac{G_M{R}_s}{2}}{R_s{C}_s},\mathrm{and}{\omega }_{p2}$= $\frac{1}{R_L{C}_L}$ are the zero and two poles of the CTLE, respectively (Figure 3).

To attain the peak gain at a higher frequency, the CTLE must be designed such that the pole frequency is higher than the zero frequency [17,18,19]. The peaking gain also depends on the dominant pole and zero. The frequencies depend on G_M of the differential pair and of the degeneration C_S and R_S, as presented in Equation (2).

$$\mathrm{Maximum}\mathrm{boost}\mathrm{peaking}=\frac{{\omega }_{p1}}{{\omega }_z}=1+G_M{R}_s.$$

(2)

In the low-frequency range, CTLE operates similarly to a differential amplifier with source degeneration, and their gains are therefore equal in this range:

$$\mathrm{DC}\mathrm{gain}=\frac{g_m{R}_L}{1+\frac{G_M{R}_s}{2}}$$

(3)

In the high-frequency range, C_S shorts the pins of the CTLE, and the circuit operates similarly to a differential amplifier without source degeneration. Therefore, the peak gain of the CTLE is as follows:

$$\mathrm{peak}\mathrm{gain}=g_m{R}_L$$

(4)

Figure 2 reveals that if $V_{bias}$ varies, the current flow through transistors M₁ and M₂ varies. However, the output current at nodes $V_{out1}$ and $V_{out2}$ changes drastically, and the dominant poles and zero also change slightly. To achieve constant current flow at nodes $V_{out1}$ and $V_{out2}$ while enabling variation in $V_{bias}$, a two-stage differential input pair CTLE with fixed degeneration C_S and R_S is proposed.

2.2. Proposed Continous-Time Linear Equalizer

Figure 4 presents a schematic of the proposed CTLE comprising two differential pairs, M₁ with M₂ and M₃ with M₄. The differential pair comprising M₃ and M₄ is degenerated by the parallel resistor R_S and the capacitor C_S. $M_5,$ $M_6{,\mathrm{and}M}_7$ are the current sinks and are controlled $V_{bias1}$ and $V_{bias2}$.

The left-hand side of Figure 4 presents the bias circuit for the CTLE. The CTLE gain can be varied by adjusting the differential voltages of V_biasn and V_biasp. The differential voltages of V_biasn and V_biasp can be expressed as follows:

$$V_{biasn}=V_{cm}+/-V_{adjust}$$

(5)

$$V_{biasp}=V_{cm}-/+V_{adjust}$$

(6)

where V_cm is the common-mode voltage, and V_adjust is the adjusting voltage for varying the bias currents of the differential pairs of the CTLE. If V_biasp > V_biasn, the current I₂ = 2I₁ flows through M₅, passes to M₁ and M₂, and the current I₁ flowing through M₆ and M₇ passes to M₃ and M₄, as presented in Figure 4. The output current at nodes V_out1 and V_out2 is I_tot = 2I₁. Similarly, V_biasp < V_biasn; the output current at nodes V_out1 and V_out2 is I_tot = 2I₁. This design also boosts the DC gain at high frequency and slightly shifts the zero (ω_z) and poles (ω_p1 and ω_p2). The zero ω_z of the proposed CTLE is dependent on g_m1 and g_m3 and on R_S and C_S. The transfer function of the single-ended proposed CTLE is presented in Equation (8).

$$\mathrm{H}(\mathrm{S})=\frac{(G_{M1}+G_{M3})R_L}{1+\frac{(G_{M1}{G}_{M3})R_S}{2}}\times \frac{1+\frac{S}{{\omega }_z}}{\left(1+\frac{S}{{\omega }_{p1}}\right)\left(1+\frac{S}{{\omega }_{p2}}\right)}$$

(7)

where ${\omega }_z$=$\frac{1}{R_s{C}_s}$, ${\omega }_{p1}$=$\frac{1+\frac{(G_{M1}{G}_{M3})R_s}{2}}{R_s{C}_s}$, and ${\omega }_{p2}$=$\frac{1}{R_L{C}_L}$ are the zero and poles of the proposed CTLE.

The maximum boost gain at higher frequencies and the DC gain are determined using Equations (8) and (9).

$$\frac{{\omega }_{p1}}{{\omega }_z}=1+(G_{M1}{G}_{M3})R_s$$

(8)

$$\mathrm{DC}\mathrm{gain}=\frac{\left(g_{m1 }\times g_{m3}\right)R_{L1}}{1+\frac{(G_{M1}{G}_{M3})R_s}{2}}$$

(9)

The Bode plot of the single-ended proposed CTLE with zeroes ω_Z and ω_Z1 that shift due to variations in the DC gain is presented in Figure 5.

2.3. TIA

A trade-off exists between the suitability of the DC operating point and performance at low frequency in this conventional g_m transimpedance structure. The bandwidth f_w and transimpedance g_m in TIAs are decoupled. High-feedback resistance is necessary for good noise performance. Figure 6 presents a schematic of a TIA topology with a feedback resistor R_f. The input impedance is extended by a factor of A + 1, where A is the amplifier gain, and the transimpedance is approximately R_f [1,14,15].

For a fixed-bandwidth amplifier, the equivalent transfer function T(s) is as shown in Equation (10):

$$\mathrm{T}(\mathrm{S})=\frac{V_{out}}{{\mathrm{I}}_{\mathrm{in}}}=-\frac{\mathrm{A}}{1+\mathrm{A}}\frac{{\mathrm{R}}_{\mathrm{f}}}{1+\frac{{\mathrm{R}}_{\mathrm{f}}\mathrm{C}}{1+\mathrm{A}}}=-\frac{\mathrm{A}}{1+\mathrm{A}}{R}_{\mathrm{f}}$$

(10)

To achieve the desired DC operating point, transistor size ($W/L$) must be increased. However, bandwidth decreases, and large parasitic capacitances occur at the output nodes [15,17]. To overcome this problem, the SF state is introduced along with a shunt feedback resistor in the TIA as preferred in [14]. To increase the frequency bandwidth, a differential out-phase circuit is included in the TIA as shown in Figure 7.

A two-input differential TIA with resistor feedback along the inductor in series is implemented. The TIA can facilitate data transfer at all speeds tolerated by the interface. The architecture has three parts that each corresponds to a stage. The first part is a shunted feedback resistor, the second part is a simple buffer, and the third part is an entirely differential output phase. A single-ended schematic is presented in Figure 7 [14,17]. Specifically, the shunt feedback resistor in the first stage converts a current to a voltage. M_S1 and R_D are simple common sources, whereas M_SB is the tail current. The second-stage M_B1 acts as a buffer and inverter with two SFs enabling isolation between the input and output of the amplifier. The third stage, M_O1, is the output phase, which increases the phase and increases the amplifier gain in which Mo_B is the tail current.

Figure 8 shows a single-ended TIA circuit with a common source stage and SF. The SF isolates R_D from the loading effect of both R_f and L_f. The output impedance of the SF is less than the resistor feedback [17,20,21].

The open-loop gain of the amplifier is as follows:

$$\mathrm{T}(\mathrm{S})=-\frac{\mathrm{A}}{1+\mathrm{A}}\frac{{\mathrm{G}}_{\mathrm{Ms}}{\mathrm{R}}_{\mathrm{D}}}{1+{\mathrm{G}}_{\mathrm{Ms}}{\mathrm{R}}_{\mathrm{D}}}\frac{1}{\mathrm{Z}}$$

(11)

where Z is the impedance, which is the total resistance to current flow in a circuit containing both resistance R_f and inductor reactance X_L. Z is defined as $\sqrt{{\mathrm{R}}_{\mathrm{f}}{}^2+{\mathrm{X}}_{\mathrm{L}}{}^2}$.

The input and output impedances of the resistor feedback at low frequencies are as follows.

$${\mathrm{R}}_{\mathrm{Zin}}=\frac{\mathrm{Z} }{1+{\mathrm{G}}_{\mathrm{Ms}}{\mathrm{R}}_{\mathrm{D}}}$$

(12)

$${\mathrm{R}}_{\mathrm{Zout}}=\frac{\frac{1}{{\mathrm{G}}_{MB}}}{(1+{\mathrm{G}}_{\mathrm{MS}}{\mathrm{R}}_{\mathrm{D}})}$$

(13)

The inductor and resistor in series, gives second order frequency 3 dB bandwidth as follows.

$${\mathsf{\omega }}_{-3dB}=\frac{\sqrt{2}\left(1+A\right)}{{\mathrm{R}}_{\mathrm{D}}}$$

(14)

2.4. Reciever AFE Architecture

The AFE architecture presented in Figure 9 includes a differential R_m (100 Ω) termination, a two-stage CTLE and TIA, and a feedback resistor (R_f) and inductance reactance (L_f). The 100 Ω resistor was adopted to match the differential input of the circuit with that of the equipment. The AFE topology along the g_m TIA with the CTLE compensates for the channel loss at a 15 GHz Nyquist frequency and adjusts the output amplitude without bandwidth deterioration [1,4,7]. The transfer function of the AFE circuit is as follows:

$${\mathrm{A}}_{v,DC}=-\frac{{\mathrm{g}}_m{\mathrm{R}}_D}{1+{\mathrm{g}}_m{\mathrm{R}}_s}\frac{1-{\mathrm{g}}_{mTIA},{\mathrm{R}}_F}{1+{\mathrm{g}}_{mTIA},{\mathrm{R}}_D}$$

(15)

$${\mathrm{A}}_{v,AC}={\mathrm{A}}_{v,DC}\frac{\left(1+\frac{S}{{\omega }_{z1}}\right)\left(1+\frac{S}{{\omega }_{z2}}\right)}{\left(1+\frac{S}{{\omega }_{p1}}\right)\left(1+\frac{S}{{\omega }_{p2}}\right)((\frac{S}{{\omega }_n}{)}^2+\frac{2\S s}{{\omega }_n}+1)}$$

(16)

where ${\mathsf{\omega }}_{z1}$ = $\frac{1}{R_s{C}_s}$,${\omega }_{p1}$= $\frac{1+\frac{G_M{R}_s}{2}}{R_s{C}_s},$ ${\mathsf{\omega }}_n$ = $\frac{\sqrt{1+{\mathrm{g}}_{mTIA},{\mathrm{R}}_D}}{\left({\mathrm{C}}_{L2}{\mathrm{L}}_f\right)}$, ${\mathsf{\omega }}_{p2}$ = $\frac{\sqrt{1+{\mathrm{g}}_{mTIA},{\mathrm{R}}_D}}{\left({\mathrm{C}}_{L2}{\mathrm{L}}_f{\mathrm{R}}_f\right)}$,${\mathsf{\omega }}_{z2}$ = 2$\mathsf{\S }wn$, $\S =\frac{{\mathrm{C}}_L{\mathrm{R}}_D+{\mathrm{g}}_{mTIA},{\mathrm{L}}_f\sqrt{1+{\mathrm{g}}_{mTIA},{\mathrm{R}}_D}/\left({\mathrm{C}}_{L2}{\mathrm{L}}_f\right)}{2\left(1+{\mathrm{g}}_{mTIA},{\mathrm{R}}_D\right)}$, C_L2 is the capacitance load, L_f is the inductance reactance, R_f is the feedback resistance, and R_D is the load resistance. The transfer function comprises one dominant pole ω_p2 and two high-frequency poles ω_n and ω_p1. To increase the gain, R_f should be larger. However, the RC constant can be increased by simply increasing R_f, unexpectedly decreasing the bandwidth [22,23]. Thus, inductance reactance is used to increase bandwidth without changing the pole ω_p2.

3. Results

The proposed AFE cascading TIA and CTLE was designed and simulated in a 180 nm complementary metal–oxide–semiconductor (CMOS) process. The performance of the CTLE, TIA, and the resulting eye diagram was simulated with Virtuoso 6.1.8–64 b software.

A high-frequency through-silicon scalable electrical model using a field solver was used as a transmission line (channel) [24,25]. Figure 10 reveals that the simulated channel can achieve 10 dB decay isolation loss at a 1.5 GHz Nyquist frequency for different cable lengths (2–8 m).

Figure 11 reveals that the simulated CTLE can achieve a DC gain of −2 to 9 dB at a 3 GHz Nyquist frequency by tuning bias voltage V_biasn and V_biasp and adjusting the voltage V_adjust (represented by X in Figure 11) from +360 to −360 mV for a channel length of 3 m. Figure 12 presents the characteristics of CTLE with and without a 3 m channel at a 3 GHz Nyquist frequency.

Figure 13 presents the simulated single-ended 6 Gb/s NRZ eye diagrams with the two different lossy channels. Figure 13b reveals that output eye is closed at the decay stage in which the CTLE is disabled. By contrast, Figure 13a reveals that the 6 Gb/s NRZ eyes are open if the CTLE is enabled.

In this case, the input signal was a simulated NRZ pseudorandom bit sequence 2³¹ − 1 with a peak-to-peak amplitude of 189.914 mV; the root-mean square jitter was 8.86 picosecond. An input and output impedance of 50 Ω and a 50 pf capacitor were used in this case. Figure 14 presents all measured parameters of the simulated eye diagram.

Figure 15 presents the simulated histogram plots used to calculate the eye width and height. Figure 15a presents a horizontal histogram used to measure the eye width at each time point and to sum up the number of traces across vertical bins. Figure 15b is a vertical histogram of eye height measurements for every amplitude point; these points were summed across the time axis.

Simulated BER bathtub curves for NRZ input data rates of 6 Gb/s are presented in Figure 16. The BER variations for different positions of the sampling point for both time delay and the voltage–power relationship are presented in Figure 16. In this case, BER(t) was 0.16 × 10⁻¹².

Table 1. Performance comparison.

Equalization	[9]	[10]	[12]	[13]	This Work
Data rate (Gbps)	10	16	16	20	5–15
Channel loss (dB)Nyquist	NA	27.6	20.5	12	16
$\mathrm{Eye}\mathrm{width}@\mathrm{BER}<{10}^{-12}$	0.62	0.18	0.16	NA	0.16
Supply (V)	1	1.2	1.2	1.5	1.8
Power (mW)	72	173.17	173.17	100	14
Technology	65 nm	65 nm	65 nm	90 nm	180 nm

summarizes the key performance metrics of the proposed CTLE and other recently published CTLEs. The proposed CTLE achieved a peaking frequency with constant current for tuning its equalization competence.

Figure 17 presents the simulated frequency response of the AFE cascading the CTLE and the TIA. Subsequently, the bandwidth must recover from 6 GHz (approximately 18/3 GHz) to 15 GHz; thus, the equalizer is tuned to its maximum peaking. To reach this required bandwidth, the TIA is designed to boost the equalizer by introducing a feedback resistor R_s and inductor L_f. The frequency response for AFE reached 15 GHz at various bias voltages (−80, 0, and 80 mV) with 12 dB channel losses at a 15 GHz Nyquist frequency with a 3 m channel (Figure 17a). Similarly, Figure 17b reveals that the DC gain varies as V_adjust varied from −80 to 160 mV at a 15 GHz Nyquist frequency.

Figure 18 reveals that the simulated single-ended 30 Gb/s PAM4 eyes are open for 12 dB of channel loss at a 15 GHz Nyquist frequency. The PAM4 eyes parameters are indicated as (1)–(4) in the figure. The simulated 0-le_Vel (1), 1-le_Vel (2), 2-le_Vel (3), and 3-le_Vel (4) voltages were 1.325, 1.392, 1.463, and 1.544 V, respectively. The eye width of levels 0/1, 1/2, and 2/3 were all 375 ps. Figure 19a presents the width of a simulated level-4 eye using the histograms for the other levels. Similarly, Figure 19b presents the bit periods for level 0/1, 1/2, and 2/3 through threshold histograms.

Table 2. Performance comparison.

Reference	[1]	[4]	[15]	[23]	This Work
Technology CMOS	28 nm	28 nm	40 nm	40 nm	180 nm
Power supply	1.5 V	0.9 V	1 V	1.2 V	1.8 V
Equalization	14-tap CTLE	CTLE+DFE	CTLE	CTLE	CTLE
Data rate range (Gbps)	1.25~28.5	32	8~10	20	5~30
Power (mW)	560	240	10	12.8	27
Channel loss (@GHz)	34 dB@14	37 dB@16	17 dB@4	18 dB@10	28 dB@15

presents the key performance metrics of the proposed AFE and other recently proposed AFEs.

4. Conclusions

The simulated two-stage differential input pair CTLE can successfully compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open the closed-eye 6 Gb/s NRZ signal with an energy efficiency of 8 pJ/bit and a BER of 0.16 × 10⁻¹² from a 2³¹ − 1 pseudorandom binary sequence input. The TIA topology can achieve higher bandwidth, ameliorating the trade-off between bandwidth and DC gain. The AFE compensated for 12 dB of channel loss at a 15 GHz Nyquist frequency and opened closed eyes for a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power from a 1.8 V supply.