Receiver Analog Front-End Cascading Transimpedance Ampliﬁer and Continuous-Time Linear Equalizer for Signals of 5 to 30 Gb/s

: A 5–30 Gb/s receiver analog front-end (AFE) cascading transimpedance ampliﬁer (TIA) and continuous-time linear equalizer (CTLE) were implemented using a Taiwan Semiconductor 180 nm process. The system comprises a two-stage differential input pair CTLE, TIA, and a differential termination resistor R m . A source-degenerated transconductance stage was adopted in the CTLE, and source follower and shunt feedback resistor stages were adopted in the TIA. The proposed CTLE could achieve high frequencies by altering the tail current with ﬁxed degenerate capacitance C S and resistance R S . The proposed AFE achieved high bandwidth, and the use of a feedback resistor R f and inductor L f improved its high-frequency performance. Simulation results revealed that the CTLE can compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open closed eyes in a 6 Gb/s non-return-to-zero signal with a bit error rate of 0.16 × 10 − 12 for a 2 31 − 1 pseudorandom binary sequence input. The AFE could compensate for 12 dB of channel loss at a 15 GHz Nyquist frequency and can open closed eyes in a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power at 1.8 V.


Introduction
As data rates have increased by 1.5 times every year since 2000, high-speed data communications are required in modern broadband applications to address bandwidth demand. Initially, in 2000, radio frequency applications required a bandwidth of 1-2 GHz for optical time-domain reflectometer applications. To meet modern broadband demand, data rates have increased to 25~30 Gbps, which is more than 75% of previous data communications. Increasing bandwidth must meet multiple challenges including channel loss, high-speed operation, area, equalization, and robustness. For data communication power, in particular, consumption is a very important factor in maintaining high performance. There are several previous studies of 28 Gbps or higher data rates [1][2][3][4][5]. Those use unrolled decision feedback equalizers to meet critical timing margins, but the unrolled CTLE structure increases the power and die's area. To achieve these challenges, one of the key designs is an analog front-end (AFE) cascading transimpedance amplifier with a continuous-time linear equalizer.
Historically, TIAs have been mostly developed for the front-ends of the optical receivers (for example, the families of 2.5, 10, 40, . . . GB/s). However, their usage is not limited to optical applications, although they have been for a long time the major driving force beyond development towards both lower noise and higher speeds. Nevertheless, in recent decades, advanced TIA designs have become increasingly popular for a variety of applications such as physics and radiation detectors of particles, miniaturized magnetic resonance spectroscopy [2], and vision and biological sensors. Different applications have resonance spectroscopy [2], and vision and biological sensors. Different applications ha their own requirements for the main parameters of TIA design. For example, high-spe optical communication circuits have pushed the bandwidth of TIAs in multiple G ranges from novel designs with lower power consumption to reduced chip area and m imized noise while operating at significant frequency [6]. Obviously, the front-end TIA the most critical component of the channel influencing both noise sensitivity and t speed of the overall system. At the output of the linear channel, voltage is provided th can be later used by decision circuits.
The second most critical component of the analog front-end block is the decision c cuit or equalization circuit as shown in Figure 1. Equalization is typically implemented both the transmitter and the receiver [7]. Before the channel, it is desirable to "peak" t transmitted high-frequency content instead of performing all the high-frequency peaki at the receiver side. On the receiver side, high-frequency peaking degrades the receiv input signal-to-noise ratio (SNR), whereas the transmit side does not. Therefore, with the transmitter, equalization is implemented to supply pre-emphasis of the high-f quency vanguard of bit transitions. In the receiver, equalization is implemented to rev the combined transmitter and channel characteristics towards a reference channel that h no or reduced ISI. Obviously, CTLE in a receiver is intended to equalize the combin characteristics of the transmitter and channel and remove the ISI at the received sign sampling points. The RX CTLE is similar to TX FFE CTLE except the input is an anal signal. The RX CTLE is often called a discrete-time linear equalizer [3,8]. As an FIR filt designed to subtract ISI effects from adjacent bits. The output of RX CTLE is further sa pled to point per data time interval for data detection. The RX CTLE will only cancel at the data detection sample points. Channel losses or insufficient bandwidth are obstacles to achieving higher data ra in data communications. One solution is changing the signal transformation scheme fro two-level pulse amplitude modulation (PAM2), also known as non-return-to-zero (NR to four-level pulse amplitude modulation (PAM4), to double the data rate without incre ing the bandwidth [9,10]. However, PAM4 requires greater system linearity. Increasi system bandwidth or using a continuous-time linear equalizer (CTLE) to compensate channel losses are other potential solutions [11][12][13].

TIA CTLE
Receivers with equalization can overcome problems caused by channel loss, such intersymbol interference. Effective high-performance receivers must meet numerous quirements, including those for power consumption, area, bit error rate (BER), and equ ization. In receiver analog front-ends (AFEs), equalizers such as CTLE are commonly us ( Figure 1). CTLE has lower power consumption than other equalizers in high-speed a plications. Moreover, as the data rate increases, the proposed CTLE can achieve differe equalization for different cable lengths by tuning the tail current with a fixed capaci and resistor. The architecture presented in [1] is generally used in high-speed AFEs. Channel losses or insufficient bandwidth are obstacles to achieving higher data rates in data communications. One solution is changing the signal transformation scheme from two-level pulse amplitude modulation (PAM2), also known as non-return-to-zero (NRZ), to four-level pulse amplitude modulation (PAM4), to double the data rate without increasing the bandwidth [9,10]. However, PAM4 requires greater system linearity. Increasing system bandwidth or using a continuous-time linear equalizer (CTLE) to compensate for channel losses are other potential solutions [11][12][13].
Receivers with equalization can overcome problems caused by channel loss, such as intersymbol interference. Effective high-performance receivers must meet numerous requirements, including those for power consumption, area, bit error rate (BER), and equalization. In receiver analog front-ends (AFEs), equalizers such as CTLE are commonly used ( Figure 1). CTLE has lower power consumption than other equalizers in high-speed applications. Moreover, as the data rate increases, the proposed CTLE can achieve different Electronics 2022, 11, 1546 3 of 16 equalization for different cable lengths by tuning the tail current with a fixed capacitor and resistor. The architecture presented in [1] is generally used in high-speed AFEs.
Typically, transimpedance amplifiers (TIAs) are used to limit receiver noise. Common-gate stages are effective amplifiers for high frequencies but have poor noise characteristics [14,15]. The TIAs based on the shunt-feedback architecture have a low-noise topology that is advantageous for high-data-rate applications. However, a trade-off exists between the performance of the circuit and the suitability of the DC operating point in conventional linear transconductance (Gm)-TIA systems. To achieve a suitable DC operating point, the size of the transistors must be increased, resulting in a large parasitic capacitance at the output nodes and reducing the bandwidth of the circuit. To overcome this problem, source follower (SF) stages were used to design the proposed AFE. This paper is organized as follows: Section 2 details the design considerations, Section 3 presents the simulation results, and Section 4 concludes the research.

CTLE
The equalization value of conventional CTLEs can be increased or decreased by varying the capacitor (C S ) and resistor (R S ), illustrated in the schematic in Figure 2. The peaking frequency is directly correlated with this equalization value and affects the bandwidth f w . Consequently, disassociating the equalization value and f w in the circuit is key. The source-degenerated Gm-cell is chosen such that the gain is degenerated through R S , ensuring sufficient linearity in the system ( Figure 2). A zero can also be introduced by combining C S and R S [8,16].
Typically, transimpedance amplifiers (TIAs) are used to limit receiver noise mon-gate stages are effective amplifiers for high frequencies but have poor noise teristics [14,15]. The TIAs based on the shunt-feedback architecture have a low-n pology that is advantageous for high-data-rate applications. However, a trade-of between the performance of the circuit and the suitability of the DC operating p conventional linear transconductance (Gm)-TIA systems. To achieve a suitable D ating point, the size of the transistors must be increased, resulting in a large para pacitance at the output nodes and reducing the bandwidth of the circuit. To overco problem, source follower (SF) stages were used to design the proposed AFE. Thi is organized as follows: Section 2 details the design considerations, Section 3 prese simulation results, and Section 4 concludes the research.

CTLE
The equalization value of conventional CTLEs can be increased or decreased ying the capacitor (CS) and resistor (RS), illustrated in the schematic in Figure 2. Th ing frequency is directly correlated with this equalization value and affects the ban fw. Consequently, disassociating the equalization value and fw in the circuit is k source-degenerated Gm-cell is chosen such that the gain is degenerated through RS ing sufficient linearity in the system ( Figure 2). A zero can also be introduced by com CS and RS [8,16].
where ω z = 1 R s C s , ω p1 = 1+ G M Rs 2 R s C s , and ω p2 = 1 R L C L are the zero and two poles of the CTLE, respectively ( Figure 3). To attain the peak gain at a higher frequency, the CTLE must be designed su the pole frequency is higher than the zero frequency [17][18][19]. The peaking gain a pends on the dominant pole and zero. The frequencies depend on GM of the diff pair and of the degeneration CS and RS, as presented in Equation (2).
In the low-frequency range, CTLE operates similarly to a differential amplifi source degeneration, and their gains are therefore equal in this range:

DC gain =
In the high-frequency range, CS shorts the pins of the CTLE, and the circuit o similarly to a differential amplifier without source degeneration. Therefore, the pe of the CTLE is as follows: peak gain = Figure 2 reveals that if varies, the current flow through transistors M1 varies. However, the output current at nodes and changes drastical the dominant poles and zero also change slightly. To achieve constant current nodes and while enabling variation in , a two-stage differentia pair CTLE with fixed degeneration CS and RS is proposed.  To attain the peak gain at a higher frequency, the CTLE must be designed such that the pole frequency is higher than the zero frequency [17][18][19]. The peaking gain also depends on the dominant pole and zero. The frequencies depend on G M of the differential pair and of the degeneration C S and R S , as presented in Equation (2).

Proposed Continous-Time Linear Equalizer
In the low-frequency range, CTLE operates similarly to a differential amplifier with source degeneration, and their gains are therefore equal in this range: In the high-frequency range, C S shorts the pins of the CTLE, and the circuit operates similarly to a differential amplifier without source degeneration. Therefore, the peak gain of the CTLE is as follows: peak gain = g m R L (4) Figure 2 reveals that if V bias varies, the current flow through transistors M 1 and M 2 varies. However, the output current at nodes V out1 and V out2 changes drastically, and the dominant poles and zero also change slightly. To achieve constant current flow at nodes V out1 and V out2 while enabling variation in V bias , a two-stage differential input pair CTLE with fixed degeneration C S and R S is proposed.   The left-hand side of Figure 4 presents the bias circuit for the CTLE. The CTLE gain can be varied by adjusting the differential voltages of Vbiasn and Vbiasp. The differential voltages of Vbiasn and Vbiasp can be expressed as follows:

Proposed Continous-Time Linear Equalizer
where Vcm is the common-mode voltage, and Vadjust is the adjusting voltage for varying the bias currents of the differential pairs of the CTLE. If Vbiasp > Vbiasn, the current I2 = 2I1 flows through M5, passes to M1 and M2, and the current I1 flowing through M6 and M7 passes to M3 and M4, as presented in Figure 4. The output current at nodes Vout1 and Vout2 is Itot = 2I1. Similarly, Vbiasp < Vbiasn; the output current at nodes Vout1 and Vout2 is Itot = 2I1. This design also boosts the DC gain at high frequency and slightly shifts the zero (ωz) and poles (ωp1 and ωp2). The zero ωz of the proposed CTLE is dependent on gm1 and gm3 and on RS and CS. The transfer function of the single-ended proposed CTLE is presented in Equation (8).
The Bode plot of the single-ended proposed CTLE with zeroes ωZ and ωZ1 that shift due to variations in the DC gain is presented in Figure 5. The left-hand side of Figure 4 presents the bias circuit for the CTLE. The CTLE gain can be varied by adjusting the differential voltages of V biasn and V biasp . The differential voltages of V biasn and V biasp can be expressed as follows: where V cm is the common-mode voltage, and V adjust is the adjusting voltage for varying the bias currents of the differential pairs of the CTLE. If V biasp > V biasn , the current I 2 = 2I 1 flows through M 5 , passes to M 1 and M 2 , and the current I 1 flowing through M 6 and M 7 passes to M 3 and M 4 , as presented in Figure 4. The output current at nodes V out1 and V out2 is I tot = 2I 1 . Similarly, V biasp < V biasn ; the output current at nodes V out1 and V out2 is I tot = 2I 1 . This design also boosts the DC gain at high frequency and slightly shifts the zero (ω z ) and poles (ω p1 and ω p2 ). The zero ω z of the proposed CTLE is dependent on g m1 and g m3 and on R S and C S . The transfer function of the single-ended proposed CTLE is presented in Equation (8). where , and ω p2 = 1 R L C L are the zero and poles of the proposed CTLE.
The maximum boost gain at higher frequencies and the DC gain are determined using Equations (8) and (9).
Electronics 2022, 11, 1546 6 of 16 The Bode plot of the single-ended proposed CTLE with zeroes ω Z and ω Z1 that shift due to variations in the DC gain is presented in Figure 5.

TIA
A trade-off exists between the suitability of the DC operating point and performance at low frequency in this conventional gm transimpedance structure. The bandwidth fw and transimpedance gm in TIAs are decoupled. High-feedback resistance is necessary for good noise performance. Figure 6 presents a schematic of a TIA topology with a feedback resistor Rf. The input impedance is extended by a factor of A + 1, where A is the amplifier gain, and the transimpedance is approximately Rf [1,14,15]. For a fixed-bandwidth amplifier, the equivalent transfer function T(s) is as shown in Equation (10): To achieve the desired DC operating point, transistor size ( ⁄ ) must be increased. However, bandwidth decreases, and large parasitic capacitances occur at the output nodes [15,17]. To overcome this problem, the SF state is introduced along with a shunt feedback resistor in the TIA as preferred in [14]. To increase the frequency bandwidth, a differential out-phase circuit is included in the TIA as shown in Figure 7.

TIA
A trade-off exists between the suitability of the DC operating point and performance at low frequency in this conventional g m transimpedance structure. The bandwidth f w and transimpedance g m in TIAs are decoupled. High-feedback resistance is necessary for good noise performance. Figure 6 presents a schematic of a TIA topology with a feedback resistor R f . The input impedance is extended by a factor of A + 1, where A is the amplifier gain, and the transimpedance is approximately R f [1,14,15].

TIA
A trade-off exists between the suitability of the DC operating point and performance at low frequency in this conventional gm transimpedance structure. The bandwidth fw and transimpedance gm in TIAs are decoupled. High-feedback resistance is necessary for good noise performance. Figure 6 presents a schematic of a TIA topology with a feedback resistor Rf. The input impedance is extended by a factor of A + 1, where A is the amplifier gain, and the transimpedance is approximately Rf [1,14,15]. For a fixed-bandwidth amplifier, the equivalent transfer function T(s) is as shown in Equation (10): To achieve the desired DC operating point, transistor size ( ⁄ ) must be increased. However, bandwidth decreases, and large parasitic capacitances occur at the output nodes [15,17]. To overcome this problem, the SF state is introduced along with a shunt feedback resistor in the TIA as preferred in [14]. To increase the frequency bandwidth, a differential out-phase circuit is included in the TIA as shown in Figure 7.
To achieve the desired DC operating point, transistor size (W/L) must be increased. However, bandwidth decreases, and large parasitic capacitances occur at the output nodes [15,17]. To overcome this problem, the SF state is introduced along with a shunt feedback resistor in the TIA as preferred in [14]. To increase the frequency bandwidth, a differential out-phase circuit is included in the TIA as shown in Figure 7. A two-input differential TIA with resistor feedback along the inductor in series is implemented. The TIA can facilitate data transfer at all speeds tolerated by the interface. The architecture has three parts that each corresponds to a stage. The first part is a shunted feedback resistor, the second part is a simple buffer, and the third part is an entirely differential output phase. A single-ended schematic is presented in Figure 7 [14,17]. Specifically, the shunt feedback resistor in the first stage converts a current to a voltage. MS1 and RD are simple common sources, whereas MSB is the tail current. The second-stage MB1 acts as a buffer and inverter with two SFs enabling isolation between the input and output of the amplifier. The third stage, MO1, is the output phase, which increases the phase and increases the amplifier gain in which MoB is the tail current. Figure 8 shows a single-ended TIA circuit with a common source stage and SF. The SF isolates RD from the loading effect of both Rf and Lf. The output impedance of the SF is less than the resistor feedback [17,20,21]. A two-input differential TIA with resistor feedback along the inductor in series is implemented. The TIA can facilitate data transfer at all speeds tolerated by the interface. The architecture has three parts that each corresponds to a stage. The first part is a shunted feedback resistor, the second part is a simple buffer, and the third part is an entirely differential output phase. A single-ended schematic is presented in Figure 7 [14,17]. Specifically, the shunt feedback resistor in the first stage converts a current to a voltage. M S1 and R D are simple common sources, whereas M SB is the tail current. The second-stage M B1 acts as a buffer and inverter with two SFs enabling isolation between the input and output of the amplifier. The third stage, M O1 , is the output phase, which increases the phase and increases the amplifier gain in which Mo B is the tail current. Figure 8 shows a single-ended TIA circuit with a common source stage and SF. The SF isolates R D from the loading effect of both R f and L f . The output impedance of the SF is less than the resistor feedback [17,20,21]. The open-loop gain of the amplifier is as follows: where Z is the impedance, which is the total resistance to current flow in a circuit contain- The open-loop gain of the amplifier is as follows: where Z is the impedance, which is the total resistance to current flow in a circuit containing both resistance R f and inductor reactance X L . Z is defined as R f 2 + X L 2 . The input and output impedances of the resistor feedback at low frequencies are as follows.
The inductor and resistor in series, gives second order frequency 3 dB bandwidth as follows.

Reciever AFE Architecture
The AFE architecture presented in Figure 9 includes a differential R m (100 Ω) termination, a two-stage CTLE and TIA, and a feedback resistor (R f ) and inductance reactance (L f ). The 100 Ω resistor was adopted to match the differential input of the circuit with that of the equipment. The AFE topology along the g m TIA with the CTLE compensates for the channel loss at a 15 GHz Nyquist frequency and adjusts the output amplitude without bandwidth deterioration [1,4,7]. The transfer function of the AFE circuit is as follows: where , C L2 is the capacitance load, L f is the inductance reactance, R f is the feedback resistance, and R D is the load resistance. The transfer function comprises one dominant pole ω p2 and two high-frequency poles ω n and ω p1 . To increase the gain, R f should be larger. However, the RC constant can be increased by simply increasing R f , unexpectedly decreasing the bandwidth [22,23]. Thus, inductance reactance is used to increase bandwidth without changing the pole ω p2 .

Results
The proposed AFE cascading TIA and CTLE was designed and simulated in a 180 nm complementary metal-oxide-semiconductor (CMOS) process. The performance of the CTLE, TIA, and the resulting eye diagram was simulated with Virtuoso 6.1.8-64 b soft-

Results
The proposed AFE cascading TIA and CTLE was designed and simulated in a 180 nm complementary metal-oxide-semiconductor (CMOS) process. The performance of the CTLE, TIA, and the resulting eye diagram was simulated with Virtuoso 6.1.8-64 b software.
A high-frequency through-silicon scalable electrical model using a field solver was used as a transmission line (channel) [24,25]. Figure 10 reveals that the simulated channel can achieve 10 dB decay isolation loss at a 1.5 GHz Nyquist frequency for different cable lengths (2-8 m).

Results
The proposed AFE cascading TIA and CTLE was designed and simulated in a 180 nm complementary metal-oxide-semiconductor (CMOS) process. The performance of the CTLE, TIA, and the resulting eye diagram was simulated with Virtuoso 6.1.8-64 b software.
A high-frequency through-silicon scalable electrical model using a field solver was used as a transmission line (channel) [24,25]. Figure 10 reveals that the simulated channel can achieve 10 dB decay isolation loss at a 1.5 GHz Nyquist frequency for different cable lengths (2-8 m).   Figure 11 reveals that the simulated CTLE can achieve a DC gain of −2 to 9 dB at a 3 GHz Nyquist frequency by tuning bias voltage V biasn and V biasp and adjusting the voltage V adjust (represented by X in Figure 11) from +360 to −360 mV for a channel length of 3 m. Figure 12 presents the characteristics of CTLE with and without a 3 m channel at a 3 GHz Nyquist frequency.
Electronics 2022, 11, x FOR PEER REVIEW 10 of 18 Figure 11 reveals that the simulated CTLE can achieve a DC gain of −2 to 9 dB at a 3 GHz Nyquist frequency by tuning bias voltage Vbiasn and Vbiasp and adjusting the voltage Vadjust (represented by X in Figure 11) from +360 to −360 mV for a channel length of 3 m. Figure 12 presents the characteristics of CTLE with and without a 3 m channel at a 3 GHz Nyquist frequency.     Figure 13 presents the simulated single-ended 6 Gb/s NRZ eye diagrams with the two different lossy channels. Figure 13b reveals that output eye is closed at the decay stage  Figure 13 presents the simulated single-ended 6 Gb/s NRZ eye diagrams with the two different lossy channels. Figure 13b reveals that output eye is closed at the decay stage in which the CTLE is disabled. By contrast, Figure 13a   In this case, the input signal was a simulated NRZ pseudorandom bit sequence 2 31 − 1 with a peak-to-peak amplitude of 189.914 mV; the root-mean square jitter was 8.86 picosecond. An input and output impedance of 50 Ω and a 50 pf capacitor were used in this case. Figure 14 presents all measured parameters of the simulated eye diagram. In this case, the input signal was a simulated NRZ pseudorandom bit sequence 2 31 − 1 with a peak-to-peak amplitude of 189.914 mV; the root-mean square jitter was 8.86 picosecond. An input and output impedance of 50 Ω and a 50 pf capacitor were used in this case. Figure 14 presents all measured parameters of the simulated eye diagram. In this case, the input signal was a simulated NRZ pseudorandom bit sequence 2 1 with a peak-to-peak amplitude of 189.914 mV; the root-mean square jitter was 8.86 cosecond. An input and output impedance of 50 Ω and a 50 pf capacitor were used in t case. Figure 14 presents all measured parameters of the simulated eye diagram.  Figure 15 presents the simulated histogram plots used to calculate the eye width and height. Figure 15a presents a horizontal histogram used to measure the eye width at each time point and to sum up the number of traces across vertical bins. Figure 15b is a vertical histogram of eye height measurements for every amplitude point; these points were summed across the time axis.
Simulated BER bathtub curves for NRZ input data rates of 6 Gb/s are presented in Figure 16. The BER variations for different positions of the sampling point for both time delay and the voltage-power relationship are presented in Figure 16. In this case, BER(t) was 0.16 × 10 −12 . Table 1 summarizes the key performance metrics of the proposed CTLE and other recently published CTLEs. The proposed CTLE achieved a peaking frequency with constant current for tuning its equalization competence. Figure 17 presents the simulated frequency response of the AFE cascading the CTLE and the TIA. Subsequently, the bandwidth must recover from 6 GHz (approximately 18/3 GHz) to 15 GHz; thus, the equalizer is tuned to its maximum peaking. To reach this required bandwidth, the TIA is designed to boost the equalizer by introducing a feedback resistor R s and inductor L f . The frequency response for AFE reached 15 GHz at various bias voltages (−80, 0, and 80 mV) with 12 dB channel losses at a 15 GHz Nyquist frequency with a 3 m channel (Figure 17a). Similarly, Figure 17b reveals that the DC gain varies as V adjust varied from −80 to 160 mV at a 15 GHz Nyquist frequency.  Figure 15 presents the simulated histogram plots used to calculate the eye width and height. Figure 15a presents a horizontal histogram used to measure the eye width at each time point and to sum up the number of traces across vertical bins. Figure 15b is a vertical histogram of eye height measurements for every amplitude point; these points were summed across the time axis. Simulated BER bathtub curves for NRZ input data rates of 6 Gb/s are presented in Figure 16. The BER variations for different positions of the sampling point for both time delay and the voltage-power relationship are presented in Figure 16. In this case, BER(t) was 0.16 × 10 −12 . Table 1 summarizes the key performance metrics of the proposed CTLE and other recently published CTLEs. The proposed CTLE achieved a peaking frequency with constant current for tuning its equalization competence.       Figure 19a presents the width of a simulated level-4 eye using   (3), and 3-le V el (4) voltages were 1.325, 1.392, 1.463, and 1.544 V, respectively. The eye width of levels 0/1, 1/2, and 2/3 were all 375 ps. Figure 19a presents the width of a simulated level-4 eye using the histograms for the other levels. Similarly, Figure 19b presents the bit periods for level 0/1, 1/2, and 2/3 through threshold histograms.     Figure 19b presents the bit periods for l 0/1, 1/2, and 2/3 through threshold histograms.    Table 2 presents the key performance metrics of the proposed AFE and other rec proposed AFEs.

Conclusions
The simulated two-stage differential input pair CTLE can successfully compen for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open the closed-eye 6 NRZ signal with an energy efficiency of 8 pJ/bit and a BER of 0.16 × 10 −12 from a 2 pseudorandom binary sequence input. The TIA topology can achieve higher bandw ameliorating the trade-off between bandwidth and DC gain. The AFE compensated f dB of channel loss at a 15 GHz Nyquist frequency and opened closed eyes for a 30 PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of p from a 1.8 V supply.
Author Contributions: P.V.S.C.N. contributed to the schematic design, simulation in software simulation results of the proposed circuits, as well as writing the paper. C.-W.L. contributed t vice on the design process, simulation, and editing of this paper. All authors have read and a to the published version of the manuscript.
Funding: This research received no external funding.

Acknowledgments:
The authors would like to acknowledge the Chip Implementation Center ( Taiwan, for its EDA tools, facility, and technology support.  Table 2 presents the key performance metrics of the proposed AFE and other recently proposed AFEs.

Conclusions
The simulated two-stage differential input pair CTLE can successfully compensate for 16 dB of channel loss at a 3 GHz Nyquist frequency and can open the closed-eye 6 Gb/s NRZ signal with an energy efficiency of 8 pJ/bit and a BER of 0.16 × 10 −12 from a 2 31 − 1 pseudorandom binary sequence input. The TIA topology can achieve higher bandwidth, ameliorating the trade-off between bandwidth and DC gain. The AFE compensated for 12 dB of channel loss at a 15 GHz Nyquist frequency and opened closed eyes for a 30 Gb/s PAM4 signal from a pseudorandom binary sequence input; it consumed 27 mW of power from a 1.8 V supply.
Author Contributions: P.V.S.C.N. contributed to the schematic design, simulation in software, and simulation results of the proposed circuits, as well as writing the paper. C.-W.L. contributed to advice on the design process, simulation, and editing of this paper. All authors have read and agreed to the published version of the manuscript.
Funding: This research received no external funding.