Towards Realization of a Low-Voltage Class-AB VCII with High Current Drive Capability

Abstract

In this paper, the implementation of a low-voltage class AB second generation voltage conveyor (VCII) with high current drive capability is presented. Simple realization and good overall performance are the main features of the proposed circuit. Proper solutions and techniques were used to achieve high signal swing and high linearity at Y, X and Z ports of VCII as well as low-voltage operation. The operation of the proposed VCII was verified through SPICE simulations based on TSMC 0.18 µm CMOS technology parameters and a supply voltage of ±0.9 V. The small signal impedance values were 973 Ω, 120 kΩ and 217 Ω at Y, X and Z ports, respectively. The maximum current at the X port was ±10 mA with maximum total harmonic distortion (THD) of 2.4% at a frequency of 1 MHz. Considering a bias current (I_B) of 29 µA and output current at the X port (I_X) of 10 mA, the current drive capability (I_X/I_B) of about 345 was achieved at the X port. The voltage swing at the Z port was (−0.4, 0.4) V. The THD value at the Z port for an input signal with 0.8 V peak-to-peak value and frequency of 1 MHz was 3.9%. The total power consumption was 0.393 µW.

1. Introduction

Since the introduction of current-mode signal processing, second generation current conveyors (CCII) [1] have been employed in various circuits, such as inductance simulators [2,3], filters [4,5,6], oscillators [7,8,9], and instrumentation amplifiers [10,11,12] as possible substitutes for conventional operational amplifiers (OAs). It is generally known that the OA-based circuits suffer from many disadvantages, mainly low frequency performance resulting from the limited gain-bandwidth product of OAs. Actually, the introduction of CCII has created a valid alternative to OAs in analog circuit design area, and circuits employing CCIIs offer high frequency operation and simplicity. Despite these benefits, the main weakness of CCII is its output signal in the form of current at the high impedance Z port of CCII. Therefore, CCII is not a good block for applications requiring output signal in the form of voltage.

In [13,14,15], the concept of dual topology of CCII, called a second generation voltage conveyor (VCII), was introduced. For this duality, VCII shows the additional advantage of providing output signal in the form of voltage. VCII has a low impedance current input port (Y), a high impedance current output port (X) and a low impedance voltage output port (Z). These impedance levels at Y, X and Z ports are of great importance in both voltage based and current based applications. In [16], the authors showed that most of the analog signal processing circuits are realizable by VCII with the advantage of providing output voltage signal at the low impedance Z port of VCII. In [17], a comparison between OA-based circuits and VCII-based circuits was drawn, showing that the problem of the cross-talk effect among inputs in a conventional OA-based non-inverting summing amplifier can be cancelled out using VCII. Literature survey shows the possibility of realizing various VCII-based analog circuits such as filters, integrators, differentiators, rectifiers, and impedance simulators [16,17,18,19,20,21,22,23,24,25,26,27].

As VCII design is a new research area, the VCII implementations reported up to this point lack the maximum efficiency. Analyzing the previously reported VCII circuits, it appears that most of them [16,17,18,19,20,21,22,23,24] are designed in class A, which has limited current drive capability at the X port. Due to high power consumption and poor current drive capability of circuits including class A VCIIs, they are unsuitable for low power applications and off-chip loads [28], while the class AB VCII with high current drive capability finds wide application as an integrated circuit front-end block. However, designing circuits with high current drive capability under low supply voltage restriction is a very challenging task. For example, to drive 10 mA in 0.18 µm technology with an aspect ratio of 100 µm/0.5 µm, a gate-source voltage equal to 2 V must be provided [29] for the PMOS transistor, while the maximum allowed supply voltage is 1.8 V. Distortion due to the transistor channel modulation effect (λ effect) is another serious issue [29] in fine technologies. It is worth mentioning that the conventional cascode structures that were conventionally used to mitigate the channel length modulation effect are not practical, due to the limited allowed supply voltage.

Literature survey shows that there are very few VCII circuits designed in class AB [25,26,27,30]; however, all of them suffer from poor current drive capability. In [25], a flipped voltage follower (FVF)-based VCII circuit was presented, which can provide an output current up to ±2 mA. In the VCII circuit reported in [26], the maximum current at X terminal is limited to ±0.5 mA. The VCII circuit presented in [27] is optimized for the minimum number of transistors. Its current drive capability is limited to ±1.065 mA. The class AB VCII reported in [30] is based on the simple translinear principle. Unfortunately, its cur-rent drive capability is only ±1.22 mA.

In this paper we propose a VCII with high current drive capability at the X terminal. The circuit operates in class AB for increasing current swing and reducing power consumption. The current splitting method used previously in current output stages was employed to increase the linearity of output voltage at the Z port and to obtain a high current drive capability at the X port. Due to low voltage restrictions, cascode structures are avoided and the required high linearity in the X port output current is maintained using simple controlling circuits by means of three transistors. The proposed circuit is able to drive a maximum current of ±10 mA at the X port at ±0.9 V supply with a power consumption of 382 µW.

The organization of this paper is as follows. In Section II, details of VCII internal circuit design are given. The existing challenges and design considerations to increase current swing are also discussed in this section. Simulation results are presented in Section III and finally Section IV concludes the paper.

2. Class AB VCII Realization

The internal structure of VCII is composed of a current buffer (CB) and a voltage buffer (VB) as shown in Figure 1. Y is a low impedance current input port. The input current to the Y port is transferred to a high impedance X port through CB. In practice finite impedance is connected to the X port to convert the conveyed current into the voltage. Then, the voltage produced at the X port is buffered to the low impedance Z port by VB. The matrix operation of a VCII is expressed as:

$$\left[{\begin{array}{c}{\mathrm{I}}_{\mathrm{X}}\\ {\mathrm{V}}_{\mathrm{Z}}\\ \mathrm{V}\end{array}}_{\mathrm{Y}}\right]=\left[\begin{array}{c}\mathsf{\beta }00\\ 0\mathsf{\alpha }0\\ 000\end{array}\right]\left[\begin{array}{c}{\mathrm{I}}_{\mathrm{Y}}\\ {\mathrm{V}}_{\mathrm{X}}\\ {\mathrm{I}}_{\mathrm{Z}}\end{array}\right],$$

(1)

where α and β are non-ideal VB and CB gains, respectively. Other requirements are high current drive capability in Y and X ports, low THD for the current transferred from Y to X ports, and high voltage swing at the Z port. In all applications reported in [16,17,18,19,20,21,22,23,24,25,26], both CB and VB sections are not included in the negative feedback loop, and as a result, overall performance is determined by VCII linearity and port impedances.

In this Section, design considerations of a high drive class AB VCII under low supply voltage are discussed. The analysis is twofold, where the first of which is the CB section.

Figure 2 shows a conventional class AB current buffer [30]. The translinear loop created by M₁–M₄ sets the value of the input voltage at zero for I_in = 0. Input current is transferred to output node through simple current mirrors (M5-M6, M7-M8). Input impedance is approximately r_in ≅ (gm₂) − 1//(gm₄) − 1. The required minimum supply voltage is:

$${\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ss}}={\mathrm{Vsg}}_{\mathrm{M}5}+\mathrm{Vds}{\left(\mathrm{sat}\right)}_{\mathrm{M}2}+\mathrm{Vsd}{\left(\mathrm{sat}\right)}_{\mathrm{M}4}+{\mathrm{Vgs}}_{\mathrm{M}7},$$

(2)

where Vgs, Vsg, Vds and Vsd are gate-source voltage, source-gate voltage, drain-source voltage, and source-drain voltage, respectively, of the related transistor. In Equation (2), Vsg_M5 and Vgs_M7 are very large for high drain currents. For instance, as mentioned in the introduction, in 0.18 µm CMOS technology, by setting the aspect ratio of M5 at 100 µm/0.5 µm, Vsg_M5 is approximately 2 V for a drain source current of 10 mA, which exceeds the allowed supply voltage of technology [29]. Evidently, for larger currents, the gate-source voltage is even higher. In the saturation region, the minimum value of the drain-source voltage is Vds(sat) = Vgs – Vth; therefore, in Equation (2), the Vgs terms play a more important role in increasing supply voltage, so if Vgs is replaced with Vds, supply voltage is reduced significantly.

Another problem associated with the conventional class AB current buffer of Figure 2 is harmonic distortion caused by the channel length modulation effect or the λ effect of M₆ and M₈. In other words, in the upper side, as the drain-source voltage of mirroring transistors M₅ and M₆ are not equal, the current transferred to the output node is not exactly equal to the input current according to:

$${\mathrm{Ids}}_{\mathrm{M}6}=\frac{{\mu \mathrm{C}}_{\mathrm{ox}}{\mathrm{W}}_6}{2{\mathrm{L}}_6}{\left({\mathrm{Vsg}}_{\mathrm{M}6}-\left|{\mathrm{Vth}}_{\mathrm{M}6}\right|\right)}^2\left(1+{\mathsf{\lambda }\mathrm{Vsd}}_{\mathrm{M}6}\right),$$

(3)

$${\mathrm{Ids}}_{\mathrm{M}5}=\frac{{\mu \mathrm{C}}_{\mathrm{ox}}{\mathrm{W}}_5}{2{\mathrm{L}}_5}{\left({\mathrm{Vsg}}_{\mathrm{M}5}-\left|{\mathrm{Vth}}_{\mathrm{M}5}\right|\right)}^2\left(1+{\mathsf{\lambda }\mathrm{Vsd}}_{\mathrm{M}5}\right),$$

(4)

where µ, C_ox, W_i and L_i (for I = 5–6) are the carrier mobility, gate oxide capacitance, channel width and channel length, respectively, of the related transistor. The same holds in the lower side of the circuit. The problems of large Vgs for M₅ and M₇ along with the nonlinearity caused by the non-zero value of λ are eliminated in the topology shown in Figure 3, where the minimum required supply voltage is reduced to:

$${\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ss}}=\mathrm{Vsd}{\left(\mathrm{sat}\right)}_{\mathrm{M}5}+\mathrm{Vds}{\left(\mathrm{sat}\right)}_{\mathrm{M}2}+\mathrm{Vsd}{\left(\mathrm{sat}\right)}_{\mathrm{M}4}+\mathrm{Vds}{\left(\mathrm{sat}\right)}_{\mathrm{M}7},$$

(5)

To increase the current drive capability of CB, the required voltage of M₂, M₄, M₅ and M₇ must be reduced, through introduction of M₉ and M₁₀ splitting transistors [29]. Transistor M₉ in the upper half has an aspect ratio m times larger than the aspect ratio of M₅. Similarly, in the lower half, M₁₀ has an aspect ratio m times larger than that of M₇. Therefore, a large part of the input current is provided by splitting transistors M₉ and M₁₀. As a result, the currents in M₅ and M₇ are reduced and consequently their Vds is reduced, resulting in lower required supply voltage. Therefore, considering Vds(sat) = Vgs − Vth and λ ≅ 0, Equation (5) can also be expressed in terms of drain-source currents as:

$${\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ss}}\approx \sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}5}}{{\mathrm{K}}_5}}+\sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}2}}{{\mathrm{K}}_2}}+\sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}4}}{{\mathrm{K}}_4}}+\sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}7}}{{\mathrm{K}}_7}},$$

(6a)

or:

$${\mathrm{V}}_{\mathrm{dd}}-{\mathrm{V}}_{\mathrm{ss}}\approx \sqrt{\frac{2{\mathrm{I}}_{\mathrm{in}}}{\left(1+\mathrm{m}\right){\mathrm{K}}_5}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{in}}}{\left(1+\mathrm{m}\right){\mathrm{K}}_2}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{in}}}{\left(1+\mathrm{m}\right){\mathrm{K}}_4}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{in}}}{\left(1+\mathrm{m}\right){\mathrm{K}}_7}},$$

(6b)

with the usual meaning of symbols for K_i = μC_ox(W_i/L_i) for i = 2, 4, 5, 7.

From Equation (6a,b), the splitting transistors results in a significant decrease of the supply voltage. In addition, the negative feedback loop provided by the splitting transistors at the input node reduces the Y port impedance by a factor of (1 + m) as follows:

$${\mathrm{r}}_{\mathrm{in}}\cong \frac{{\mathrm{gm}}_2^{-1}\Vert {\mathrm{gm}}_4^{-1}}{\left(1+\mathrm{m}\right)},$$

(7)

The channel length modulation effect is reduced using two simple controlling circuitries [31]. In the upper half, the drain-source voltages of M₅ and M₆ are kept equal by a negative feedback loop established by M_C1–M_C2. Similarly, in the lower side of the circuit, the drain-source voltages of M₇ and M₈ are kept equal by M_C3–M_C4. Here, M_L1 and M_L2 are simple level shifters used to provide appropriate bias voltage at drain nodes of M_C2 and M_C4, respectively. Current sources I_B2-I_B7 are used to bias transistors in controlling circuitries. In the lower half, the drain current of M_C3 is fixed by the I_B5 current source. Therefore, its gate-source voltage is a fixed value, and it transfers V_X to the gate of M_C4. Any difference between V_X and the drain voltage of M₇ is compared by M_C4 and the appropriate voltage is produced at its drain node, which is applied to the gate of mirroring transistors M₇–M₈, and M₁₀ by M_L2. To elaborate the operation of controlling circuitries of the lower half, let us consider the case that V_X is reduced. Due to the channel length modulation effect, a reduction in V_X tends to reduce the M₁₀ drain current. In this case, the gate voltage of M_C4 is also reduced, which results in an increase in its drain voltage, which is applied to the gate of M₇–M₈, and M₁₀ through M_L2. As a result, the drain current of M₁₀ is kept constant regardless of V_X variation.

Similarly, if V_out is increased, the gate voltage of M₇–M₈, and M₁₀ is reduced to avoid any increase in output current.

Therefore, any variation of the M₁₀ drain current due to variations in V_X is compensated for. A similar procedure occurs in the upper half by M_C1–M_C2 transistors. As the λ effects of M₆ and M₈ are compensated for by control circuitry, we can ignore their effect on output impedance and therefore, the impedance at the output node is approximately found as:

$${\mathrm{r}}_{\mathrm{out}}\approx ({\mathrm{ro}}_{\mathrm{IB}2}+\frac{1}{{\mathrm{gm}}_{\mathrm{MC}1}})\Vert ({\mathrm{ro}}_{\mathrm{IB}5}+\frac{1}{{\mathrm{gm}}_{\mathrm{MC}3}})\Vert {(\frac{1}{{\mathrm{ro}}_{\mathrm{M}6}}-\frac{{\mathrm{gm}}_{\mathrm{M}6}}{{\mathrm{gm}}_{\mathrm{M}5}{\mathrm{ro}}_{\mathrm{M}5}})}^{-1}\Vert {(\frac{1}{{\mathrm{ro}}_{\mathrm{M}8}}-\frac{{\mathrm{gm}}_{\mathrm{M}8}}{{\mathrm{gm}}_{\mathrm{M}7}{\mathrm{ro}}_{\mathrm{M}7}})}^{-1}$$

(8)

To avoid complications, Equation (8) is derived by the assumption that the open loop gain of the λ effect cancelling circuit is infinite. However, in practice, due to its limited gain, it is expected that the impedance at the X port is smaller than Equation (8).

In Figure 3, in the λ effect cancelling circuit at the upper side, there are four poles located at the source of M_C2, gate of M_C1, source of M_L1 and drain of M_C2. Due to low impedance values at the source of M_C2, gate of M_C1 and source of M_L1, their related poles are smaller than the pole related to the drain of M_C2. To grantee frequency stability, a compensation capacitor can be added to the drain of M_C2 to make this pole much smaller than the other poles. Therefore, the negative feedback loop operates as a single pole system and its stability is guaranteed. The same explanations hold for the lower side where a compensation capacitor can be added to the drain of M_C4 to make the related pole the dominant pole of the lower side.

Starting from Figure 2, we can isolate a conventional Class AB voltage buffer [30] as shown in Figure 4. In the positive cycle, the input voltage is transferred to the output through M₁₁–M₁₂ transistors. It follows that in this case we have:

$${\mathrm{V}}_{\mathrm{out}}={\mathrm{V}}_{\mathrm{in}}+{\mathrm{Vgs}}_{\mathrm{M}11}-{\mathrm{Vgs}}_{\mathrm{M}12},$$

(9)

From Equation (9), to have V_out = V_in, gate-source voltages of M₁₁ and M₁₂ must be kept equal. However, the drain-source current of M₁₁ is a constant value of I_B8, while that of M₁₂ is not constant and is equal to I_L. In terms of drain currents, Equation (9) can be expressed as:

$${\mathrm{V}}_{\mathrm{out}}={\mathrm{V}}_{\mathrm{in}}+\sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}11}}{{\mathrm{K}}_{11}}}+{\mathrm{V}}_{\mathrm{thM}11}-\sqrt{\frac{2{\mathrm{Ids}}_{\mathrm{M}12}}{{\mathrm{K}}_{12}}}-{\mathrm{V}}_{\mathrm{thM}12},$$

(10)

As I_dsM12 = I_L + I_B8, by assuming I_B8 << I_L, and V_thM11 = V_thM12, Equation (10) is:

$${\mathrm{V}}_{\mathrm{out}}\approx {\mathrm{V}}_{\mathrm{in}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{B}8}}{{\mathrm{K}}_{11}}}-\sqrt{\frac{2{\mathrm{I}}_{\mathrm{L}}}{{\mathrm{K}}_{12}}},$$

(11)

Inserting I_L = V_out/R_L, Equation (11) becomes:

$${\mathrm{V}}_{\mathrm{out}}\approx {\mathrm{V}}_{\mathrm{in}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{B}2}}{{\mathrm{K}}_{11}}}-\sqrt{\frac{2{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{K}}_{12}{\mathrm{R}}_{\mathrm{L}}}},$$

(12)

One effective method to reduce the non-linearity of V_out is to keep the third term in Equations (11) and (12) as small as possible. This can be realized by minimizing the variation in the drain current of M₁₂. Another disadvantage of the conventional class AB voltage buffer of Figure 4 is its high output impedance, which is equal to:

$${\mathrm{r}}_{\mathrm{out}}\approx {\mathrm{gm}}_{12}^{-1}\Vert {\mathrm{gm}}_{14}^{-1},$$

(13)

Figure 5 shows the modified version of the conventional class AB voltage buffer of Figure 4 where the current splitting method reported in [29] is used to keep the Ids_M12 variation as small as possible. In the upper side, the current mirror made of M₁₅–M₁₆ is added and the drain of M₁₆ is connected to the input node. By setting the aspect ratio of M₁₆ n times larger than that of M₁₅, we have:

$${\mathrm{Ids}}_{\mathrm{M}16}={\mathrm{nIds}}_{\mathrm{M}15}={\mathrm{nIds}}_{\mathrm{M}12},$$

(14)

By assuming a positive cycle of the input signal, for I_L we have:

$${\mathrm{I}}_{\mathrm{L}}={\mathrm{Ids}}_{\mathrm{M}12}+{\mathrm{Ids}}_{\mathrm{M}16},$$

(15)

Inserting Equation (14) into Equation (15) we have:

$${\mathrm{I}}_{\mathrm{L}}=\left(1+\mathrm{n}\right){\mathrm{Ids}}_{\mathrm{M}12},$$

(16)

Assuming Vth_M11 = Vth_M12, from Equations (16) and (10), we have:

$${\mathrm{V}}_{\mathrm{out}}\approx {\mathrm{V}}_{\mathrm{in}}+\sqrt{\frac{2{\mathrm{I}}_{\mathrm{B}8}}{{\mathrm{K}}_{11}}}-\sqrt{\frac{2{\mathrm{V}}_{\mathrm{out}}}{{\mathrm{K}}_{12}{\mathrm{R}}_{\mathrm{L}}\left(1+\mathrm{n}\right)}},$$

(17)

Comparing Equations (12) and (17), we show that by applying the current splitting method, the third term in Equation (12), which is the main cause of non-linearity is reduced by a factor of (1 + n). Similarly, the current mirror made of M₁₇–M₁₈ has been added to the lower side to reduce current variation in M₁₄ for the negative cycle of the input voltage. Another advantage of applying the current splitting method is to reduce the output impedance by (1 + n) times:

$${\mathrm{r}}_{\mathrm{out}}\approx \frac{{\mathrm{gm}}_{12}^{-1}\Vert {\mathrm{gm}}_{14}^{-1}}{\left(1+\mathrm{n}\right)},$$

(18)

In Figure 5, in the upper half, there is only one dominant pole at the gate of M₁₅. In the lower half, the dominant pole is at the gate of M₁₇. In fact, the aspect ratio of M₁₈ is much larger (in this design 200 times) than the aspect ratio of M₁₄ and M₁₇. Therefore, at the gate of M₁₈, the value of parasitic capacitance is large, which makes the dominant pole of the lower half. Similarly, the large capacitance at the gate of M₁₆ makes the dominant pole of the upper half. Consequently, the negative feedback loops at the voltage buffer section operate as a single pole system, which is naturally stable, and no compensation capacitor is required.

The complete implementation of the high drive class AB VCII realization is shown in Figure 6, which is constructed by series connection of the CB of Figure 3 and the VB of Figure 5.

3. Simulation Results

The proposed circuit of Figure 6 was simulated in TSMC 0.18 μm CMOS technology [32] with a supply voltage of ±0.9 V. Transistor aspect ratios are reported in

Table 1. Aspect ratio of the used transistors.

Transistor	W (µm)/L (µm)	Transistor	W (µm)/L (µm)
M1, M2	36/0.36	ML1, ML2	0.9/0.45
M3–M4	72/0.36	MC1	18/0.9
M5	72/0.9	MC2	0.81/0.9
M6	792/0.9	MC3	0.9/0.9
M7	36/0.45	MC4	9/0.9
M8	396/0.45	M13-M14	4.5/0.9
M9	720/0.9	M15, M17	0.18/0.36
M10	360/0.45	M16, M18	36/0.36
M11–M12	3.6/0.18

. The values of m and n were set to 10 and 200. For frequency performance analysis, a load of 50 Ω and 5 pF was connected to the X node. The Z node was connected to 10 kΩ. For frequency stability, 5 pF compensation capacitors were added between the drain and gate of M_C2 and M_C4. All bias current sources (I_B1 = 1.5 μA, I_B2,3,4,5,6,7 = 10 μA, I_B8 = 0.5 μA) were implemented with simple current mirrors with an aspect ratio of 9 µm/0.9 µm. As the current splitting section in the voltage buffer has a gain of 200, we selected a low bias current of 0.5 µA for this section. The current splitting section in the current buffer has a gain of 10 and the output branch transistors gain is 11, so we selected 1.5 μA for this section. This was done to reduce overall power consumption. The λ effect cancelling circuit operates in class A, so we selected 10 µA for this section.

The variation of V_X by I_X in the DC domain was also examined, which is shown in Figure 7. From Figure 7, the value of r_X is about 120.6 kΩ. The frequency performance of r_Y, r_X and r_Z are also shown in Figure 8. The calculated and simulated values of the transistors’ small signal parameters are reported in

Table 2. Transistors calculated and simulated small signal parameters used in the formulas.

Transistor	Parameter	Calculated	Simulation
MIB2	gm	208 µA/V	161 µA/V
	ro	740 kΩ	641 kΩ
	Vsat	0.096 V	0.08 V
MIB5	gm	129 µA/V	107 µA/V
	ro	1.25 MΩ	1 MΩ
	Vsat	0.154 V	0.159 V
MC1	gm	181 µA/V	130 µA/V
	ro	1.2 MΩ	1.25 MΩ
	Vsat	0.1 V	0.109 V
MC3	gm	207 µA/V	182 µA/V
	ro	740 kΩ	641 kΩ
	Vsat	0.096 V	0.09 V
M2	gm	48 µA/V	72 µA/V
	ro	1.7 MΩ	1.02 MΩ
	Vsat	0.012 V	0.04 V
M4	gm	38.4 µA/V	35 µA/V
	ro	3 MΩ	4.3 MΩ
	Vsat	0.014 V	0.04 V
M8	gm	0.506 µA/V	0.659 µA/V
	ro	298 kΩ	175 kΩ
	Vsat	0.022 V	0.04 V
M6	gm	0.500 µA/V	0.571 µA/V
	ro	235 kΩ	390 kΩ
	Vsat	0.037 V	0.05 V
M12	gm	16.6 µA/V	11.8 µA/V
	ro	9.2 MΩ	8.8 MΩ
	Vsat	0.033 V	0.047 V
M14	gm	13.3 µA/V	9.7 µA/V
	ro	18.8 MΩ	19 MΩ
	Vsat	0.047 V	0.06 V

. Using these values, the simulation and calculation results for r_x, r_Y and r_Z are summarized in

Table 3. The calculated simulated values of r_Y, r_X and r_Z.

Parameter	Calculated	Simulated
rZ (Equation (18))	167 Ω	217 Ω
rY (Equation (7))	1.15 kΩ	973 Ω
rX (Equation (8))	158 kΩ	120 kΩ

. As it is seen, there is good agreement between the simulation and calculation results for r_x and r_Z. The achieved result for r_X is 120 kΩ for simulation and 158 kΩ for calculation. The reason for this difference is that in calculations it is assumed that the open loop gain of the λ effect cancelling circuit is assumed as infinite. However, in practice, due to its limited gain, the value of impedance at the X port is lower than expected.

To examine the frequency performance of the circuit, the X port was connected to 50 Ω resistors and a 5 pF capacitor, while the Z port was connected to a 10 kΩ resistor. The frequency performance of β and α is shown in Figure 9. For β, the DC value and −3dB frequency were 0.993 and 11 MHz, respectively. For α, the DC value and −3 dB frequency are 0.953 and 50 MHz, respectively. The circuit power consumption was 393 μW. The DC transfer characteristic between I_Y and I_X is shown in Figure 10. As it is seen, there is good linearity for current transfer when I_Y is varied from −10 mA to +10 mA. The linearity of voltage transfer between X and Z nodes was investigated by applying a DC voltage to the X node and connecting the Z node to a load of 10 kΩ. To compare with theory, Equation (17) was also calculated. The results of the calculations, which are shown in Figure 11, show good agreement between theory and simulations. The limit of voltage range in node X is −0.4 V to +0.4 V. Figure 10 shows a good linearity between X and Z nodes in the range of −0.4 V to +0.4 V. The maximum error was −70 mV, which occurred at 0.4 V. Figure 12 shows the THD of I_X for various amplitudes of input current at 1 kHz and 1 MHz frequencies. Favorably, the value of THD for I_X did not exceed 2.4%. In fact, by increasing the frequency, the gain of the λ effect cancelling circuit reduces, so its effect starts decreasing at higher frequencies. As it is shown, the value of THD at 1 kHz is larger than 1 MHz. Figure 13 shows the resulting THD of V_z for different amplitudes of input voltage. In this case, THD remained below 3.9%. Monte-Carlo simulations in 100 runs for mismatch of 3% between V_th and t_ox of all transistors are reported in

Table 4. Monte-Carlo Simulation Results.

Parameter	Maximum	Minimum	Mean
rY(Ω)	2.35k	233	745
rX(kΩ)	395	40	123
rZ(Ω)	347	143	224.3
β	1.47	0.651	1.02
α	0.938	0.920	0.930
Ix THD at 10 mA and 1 MHz(%)	3.27	1.43	2.46
Vz THD at 0.8 V p-to-p and 1 MHz(%)	8	2	3.53

. In addition, corner case simulation results are summarized in

Table 5. PVT Simulation results.

Parameter	P				V (Vdd-Vss)		T (°C)
	FF	SF	FS	SS	±0.99 V	±0.81 V	−20	25	80
rY(Ω)	956	965	964	972	894	1 k	804	959	1100
rX(kΩ)	113.7	113.8	114	113.88	98	129.4	93.2	113	147
rZ(Ω)	205	212	213	217	195	233	182.8	211.4	248.1
β	0.993	0.990	0.993	0.992	0.992	0.993	0.9924	0.9971	0.9927
α	0.933	0.952	0.932	0.931	0.935	0.928	0.934	0.932	0.929
THD at Iin = 1 mA and 1 MHz (%)	2.44	2.31	2.24	2.36	2.37	2.3	2.36	2.43	2.48
THD at Vx = 0.8 V p-p and 1MHz (%)	3.04	2.46	2.4	3.4	1.59	7.6	3.52	3.37	4.2

.

The application of the proposed VCII as a transimpedance amplifier [17] is examined in Figure 14a, while the X port is connected to a load of 100 Ω. The frequency performance is shown in Figure 14b, which shows a gain of 16.5 dB and BW of 1 MHz.

Comparison summary of the proposed VCII and other works is shown in

Table 6. Comparison between proposed circuit and some other previously reported VCII topologies.

	Proposed	[16]	[18]	[21]	[25]	[26]	[27]	[29]
Class	AB	A	A	A	A	AB	A	AB
α(DC, f) - 3dB	(0.953, 50 MHz)	(0.997, 217 MHz)	(0.995, 340 MHz)	(1.017, 330 kHz)	(0.992, 220 MHz)	(0.972, 55 MHz)	(0.968, 2.57 GHz) *(1, 1.92 GHz) **	(1, 100 GHz)
β(DC, f) - 3dB	(0.993, 11 MHz)	(0.998, 200 MHz)	(0.996, 14.6 MHz)	(1.035–108 dB 26 kHz–37 kHz)	(0.978, 22.4 MHz)	(0.996, 165 MHz)	(0.988, 794 MHz)	(0.987, 169.7 MHz)
Max IX	10 mA	17 μA	40 μA	100 nA	2 mA	0.5 mA	1.065 mA	1.22 mA
THD at IX	1 2.40%	2 0.10%	NA	NA	3 3.36%	3 1.10%	NA	4 1%
rx	120 kΩ	1.2 MΩ	0.8 MΩ	22 GΩ	370 kΩ	522 kΩ	74.28 kΩ	273.8 kΩ
rY	973 Ω	6.7 Ω	49 Ω	27 kΩ	2 mΩ	23 Ω	930 Ω	1.88 kΩ
rZ	217 Ω	0.7 Ω	79 Ω	27 kΩ	2 mΩ	160 Ω	705 Ω * 35 Ω **	1.75 kΩ
Vdd-Vss	±0.9 V	±1.65 V	±1.65 V	±0.3 V	±1.65 V	±0.9 V	±0.9 V	±0.9 V
Pd	0.393 mW	0.330 mW	0.7 mW	96 nW	0.320 mW	0.120 mW	0.622 mW * 0.664 mW **	0.179 mW
THD at VZ	5 3.90%	NA	NA	NA	6 2.48%	7 2.40%	NA	8 1%
#transistors	38	20	16	20	25	37	6 * 11 **	12
Tech.	0.18 μm	0.35 μm	0.35 μm	0.18 μm	0.35 μm	0.15 μm	0.18 μm	0.18 μm

¹ Iy = 10 mAp-p @1 MHz, ² Iy = 20 µAp-p @1 MHz ³ Iy = 1 mA p-p @1 MHz ⁴ 2.44 mAp-p@1 MHz ⁵ 0.8 Vp-p @1 MHz ⁶ 1 Vp-p @1 MHz 7 1.6 Vp-p @1 MHz ⁸ 1.78 Vp-p @1 MHz, * First circuit ** Second circuit.

. As it is seen, the proposed circuit provides the largest current drive capability ever reported. For a 29 µA bias current at M₆ and M₈, the circuit can provide ±10 mA to the X port, which is 345 times larger than the used bias current.

4. Conclusions

In this paper, the design of a class AB high drive VCII was presented. The current splitting method was used to reduce the required gate-source voltage of transistors in both CB and VB sections, resulting in reduced supply voltage and improved linearity in VB. This also led to reduced impedance for Y and Z ports. High linearity in the CB section was also provided by applying controlling circuitries, which eliminated the channel length modulation effect of mirroring transistors. As a result, high impedance at the X port was also provided. For low voltage operation, cascode current mirrors were avoided. In addition, in all branches, the maximum number of transistors between V_DD and V_SS was only four, resulting in low voltage operation.