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Open AccessConcept Paper

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

ECC Department, Nirma University, Ahmedabad 382481, India
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J. Low Power Electron. Appl. 2019, 9(2), 19; https://doi.org/10.3390/jlpea9020019
Received: 22 February 2019 / Revised: 21 May 2019 / Accepted: 21 May 2019 / Published: 17 June 2019
Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method. View Full-Text
Keywords: NoC based SoC; test scheduling; test time reduction; test bus architecture; test power; test clock frequency; ILP NoC based SoC; test scheduling; test time reduction; test bus architecture; test power; test clock frequency; ILP
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Parmar, H.; Mehta, U. ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC. J. Low Power Electron. Appl. 2019, 9, 19.

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