# A Recent Progress of Spintronics Devices for Integrated Circuit Applications

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## Abstract

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## 1. Introduction

## 2. Benchmarking Results for STT-MRAM, SOT-MRAM, and E-Field MRAM

## 3. Review for Recent Progress of STT-MRAM, SOT-MRAM, and E-Field MRAM

#### 3.1. Recent Progress of STT-MRAMs for NV Memory Applications

#### 3.1.1. MTJ Design with High Thermal Tolerance for STT-MRAM with CMOS BEOL Process Compatibility

_{a}) where the maximum TMR ratio is observed in the s-MTJs increases with increasing x up to 35at%B. In s-MTJ with x = 40at%B, the TMR ratio drastically decreases at T

_{a}= 400 °C, which may be related to the formation of a weak (001) texture in MgO/CoFeB stack with high B concentration [30]. On the other hand, as shown in Figure 2b,d, the TMR ratio of d-MTJs increases monotonically as T

_{a}increases up to 400 °C. In d-MTJ with x = 25at%B, TMR ratio reaches to 131%. As x increases, higher T

_{a}is required in order to get a higher TMR ratio. As seen above, the temperature dependence of TMR ratio in d-MTJ is significantly different from that in s-MTJ [29].

_{a}dependence of TMR ratio for s-MTJ and d-MTJ shown in Figure 2, we evaluated effective anisotropy energy density K

_{eff}t* from the areal difference between the out-of-plane and in-plane m–H curves as shown in Figure 3a. t* is the effective magnetic layer thickness, which is obtained by subtracting the magnetically dead layer thicknesses from the nominal free layer thickness as shown in Figure 3b. Figure 4 shows typical K

_{eff}t*-t* plots for the s-MTJ and the d-MTJ with x = 25, 30, and 35at.%B after annealing at T

_{a}= 400 °C. Positive and negative values of K

_{eff}t* means in-plane and perpendicular magnetic anisotropy, respectively. In both of s-MTJ and d-MTJ, K

_{eff}t* tends to increase as t* decreases. t* indicating the positive value of K

_{eff}t* becomes thick in the d-MTJ type compared with s-MTJ. The maximum K

_{eff}t* for s-MTJ and d-MTJ annealed at 400 °C is obtained by x = 35 and x = 25, respectively. Thus, high TMR ratios are obtained in s-MTJ and d-MTJ because high perpendicular magnetic anisotropy is realized even in high-temperature annealing at 400 °C.

_{eff}t* is determined by competition between interfacial anisotropy K

_{i}and shape anisotropy (−M

_{s}

^{2}/2µ

_{0}where M

_{S}is saturation magnetization), as expressed in Equation (1).

_{i}is interfacial anisotropy energy, N

_{z}and N

_{x}are demagnetization coefficients, K

_{b}is bulk anisotropy energy. In Equation (1), the second term is shape anisotropy, proportional to M

_{s}square. K

_{b}is negligibly small in the system. Figure 5 shows B content dependence of saturation magnetization M

_{s}evaluated from M–H curves for the s-MTJ and d-MTJ annealed at 400 °C. M

_{s}of d-MTJ is suppressed to about half of that of s-MTJ.

_{s}and Equation (1), in the s-MTJ, shape anisotropy is the dominant factor that determines perpendicular anisotropy because of larger M

_{s}(larger shape anisotropy). On the other hand, in the d-MTJ, K

_{i}is the dominant factor because of smaller M

_{s}and larger K

_{i}(about double that of s-MTJ thanks to double CoFeB/MgO interface). In order to improve perpendicular anisotropy, larger K

_{i}and smaller M

_{s}are desirable. However, with increasing B content in CoFeB, both M

_{s}of CoFeB and K

_{i}decreases [21].

_{s}between s-MTJ and d-MTJ is due to the difference in B diffusion state. As shown in Figure 6, the boron in the s-MTJ adsorbs into the Ta-capping layer. On the other hand, boron in the d-MTJ is located around the Ta insertion layer. The Ta insertion layer acts as a boron absorption layer. Also, the MgO-capping layer blocks boron diffusion from the CoFeB to the Ta-capping layer. As a result, in the d-MTJ, a large amount of boron remains in the CoFeB layer. This results in lower M

_{s}in the free layer of d-MTJ than in that of s-MTJ. These results indicate that boron composition of the CoFeB layer after annealing is a critical factor to realize thermal tolerance for annealing at a temperature of 400 °C, which is a standard requirement for the integration with CMOS in back-end-of line process.

_{s}caused by an uncompensated stray magnetic field from the reference layer as annealing temperature T

_{a}increased from 350 °C to 400 °C [18], resulting in asymmetry of thermal stability factor Δ between parallel (P) and antiparallel (AP) states, as shown in Figure 7 [18].

_{s}, we investigated T

_{a}dependence of spontaneous magnetic moment per unit area m

_{s}of each layer in reference layer (Figure 8) and a variation of composition depth profile after annealing at 400 °C.

_{a}from 350 °C to 400 °C. The MTJs annealed at 400 °C show larger H

_{s}(AP state becomes more stable) compared to those annealed at 350 °C. The variation of H

_{s}resulted because the m

_{s}of top Co/Pt multilayer with CoFeB insertion layer decreased and the m

_{s}of bottom Co/Pt multilayer decreased as T

_{a}increased from 350 °C to 400 °C. EDX line analysis revealed that Fe in the CoFeB layer underneath the MgO layer (in the reference layer) diffuses into Co/Pt multilayers in the SyF reference layer via annealing at T

_{a}= 400 °C, which could cause the variation of m

_{s}in the SyF reference layer. The results indicate that suppression of Fe diffusion in the CoFeB layer in the reference layer is important to achieve more robust MTJs against annealing.

#### 3.1.2. Recent Progress of STT-MRAMs

#### 3.2. Progress of SOT-MRAM and Future Issues for NV Memory Applications

_{SH}is defined as θ

_{SH}= J

_{S}/J

_{e}where J

_{e}and J

_{S}are applied charge current density flowing through the channel layer and a resultant transverse-flowing spin current density, respectively. A quantitative measurement method of θ

_{SH}is summarized in [68].

#### 3.3. Progress of VC-MRAM

_{b}, the interfacial perpendicular magnetic anisotropy of the p-MTJ is modulated [87], resulting in the change of energy barrier depth between P and AP state. When V

_{b}is negative (positive), interfacial perpendicular anisotropy increases (decreases). At above threshold voltage, precessional switching can be achieved under magnetic field.

## Author Contributions

## Funding

## Acknowledgments

## Conflicts of Interest

## Glossary

BEOL | back-end-of-line |

MTJ | magnetic tunneling junctions |

MRAM | magnetic random access memory |

SOT | spin-orbit torque |

STT | spin-transfer torque |

VC | voltage controlled |

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**Figure 1.**(

**a**) Memory cell structure for STT-MRAM and VC-MRAM. The memory cell structure consisting of one magnetic tunnel junction (MTJ) and one transistor yields in minimum cell size. There are many variations for the memory cell structure depending on the applications, in particular, for the STT-MRAM. (

**b**) Memory cell structure for SOT-MRAM, where one MTJ and two transistors are required at least.

**Figure 2.**Schematic for single CoFeB–MgO interface MTJ (s-MTJ) (

**a**) and double CoFeB–MgO interface MTJ (d-MTJ) (

**b**) stack structures. Annealing temperature T

_{a}dependence of tunnel magnetoresistance (TMR) ratio for s-MTJ (

**c**) and d-MTJ (

**d**) with B content of 25–40at. % in CoFeB free layer.

**Figure 3.**Magnetic moment per unit area versus in-plane and out-of-plane magnetic field (

**a**) and saturation magnetization Ms versus nominal free layer thickness t (

**b**).

**Figure 4.**K

_{eff}t* as a function of t* for s-MTJ and d-MTJ with B content of 25–35at.% annealed at 400 °C.

**Figure 5.**B content dependence of saturation magnetization M

_{s}for s-MTJ and d-MTJ with B content of 25–35at% annealed at 400 °C.

**Figure 6.**EELS line profiles of B, Fe, Co, Ta, Mg, and O elements for s-MTJ and d-MTJ annealed at 400 °C.

**Figure 7.**Schematic for potential curve at parallel (P) and antiparallel (AP) state (a) and resistance versus magnetic field curve. Shift field H

_{s}is defined as center of hysteresis curve.

**Figure 8.**(

**a**) Stack structure of a stack for magnetic tunnel junction (MTJ). (

**b**) Magnetic moment per unit area versus magnetic field curve of the stack MTJ. Arrows show a direction of magnetic moment for free layer m

_{s}

^{free}, top part of reference layer m

_{s}

^{ref1}, and bottom part of reference layer m

_{s}

^{ref2}.

**Figure 10.**Schematic diagrams of three types of SOT devices in which magnetization trajectory during switching is also shown as inset.

**Figure 11.**(

**a**) SOT device structure for field-free switching where the easy axis of magnetization, parallel to the major axis of ellipse, θ is canted from the x-axis. (

**b**) Resistance versus current density curve for the SOT device with θ = 0° (x-type) and 15°.

**Table 1.**Benchmarking results of STT-MAM, SOT-MRAM, and VC-MRAM as NV memories using spintronics devices compared with SRAM and eFlash as CMOS-based memories. The F denotes feature size of CMOS. Memory cell size is defined by F.

SRAM | STT-MRAM for SRAM | eFlash | STT-MRAM for eFlash | SOT-MRAM | VC-MRAM | |
---|---|---|---|---|---|---|

Cell size | 160–200 F^{2} | 70–100 F^{2} | 40 F^{2} | 50–60 F^{2} | 160 F^{2} | 50–60 F^{2} |

Operation voltage (V) | 0.6–1.2 | 0.6 | ≥10 | 0.6 | 0.6 | 2.2 |

Write current (A) | 10^{−5} | 10^{−5} | 10^{−5} | 10^{−5} | 10^{−4} | 10^{−5} |

R/W time (ns) | ≤2/≤2 | 5/10 | 10/20,000 | 25/200 | 5/≤2 | 10/≤2 |

Retention | Volatile | 1 month | >20 years | 15 years | ≤10 years | 1 month |

Endurance (cycles) | 10^{16} | 10^{14} | 10^{5} | 10^{8} | 10^{14} | - |

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Endoh, T.; Honjo, H. A Recent Progress of Spintronics Devices for Integrated Circuit Applications. *J. Low Power Electron. Appl.* **2018**, *8*, 44.
https://doi.org/10.3390/jlpea8040044

**AMA Style**

Endoh T, Honjo H. A Recent Progress of Spintronics Devices for Integrated Circuit Applications. *Journal of Low Power Electronics and Applications*. 2018; 8(4):44.
https://doi.org/10.3390/jlpea8040044

**Chicago/Turabian Style**

Endoh, Tetsuo, and Hiroaki Honjo. 2018. "A Recent Progress of Spintronics Devices for Integrated Circuit Applications" *Journal of Low Power Electronics and Applications* 8, no. 4: 44.
https://doi.org/10.3390/jlpea8040044