Next Article in Journal
Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller
Next Article in Special Issue
A Summary of the Special Issue “Emerging Network-on-Chip Architectures for Low Power Embedded Systems”
Previous Article in Journal / Special Issue
Global Adaptation Controlled by an Interactive Consistency Protocol
Open AccessArticle

Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer

Faculty of Arts, Science and Technology, University of Northampton, Northampton NN2 7AL, UK
*
Author to whom correspondence should be addressed.
Academic Editors: Davide Patti and Alexander Fish
J. Low Power Electron. Appl. 2017, 7(2), 14; https://doi.org/10.3390/jlpea7020014
Received: 31 January 2017 / Revised: 17 May 2017 / Accepted: 23 May 2017 / Published: 29 May 2017
(This article belongs to the Special Issue Emerging Network-on-Chip Architectures for Low Power Embedded Systems)
The disparity between memory and CPU have been ameliorated by the introduction of Network-on-Chip-based Chip-Multiprocessors (NoC-based CMPS). However, power consumption continues to be an aggressive stumbling block halting the progress of technology. Miniaturized transistors invoke many-core integration at the cost of high power consumption caused by the components in NoC-based CMPs; particularly caches and routers. If NoC-based CMPs are to be standardised as the future of technology design, it is imperative that the power demands of its components are optimized. Much research effort has been put into finding techniques that can improve the power efficiency for both cache and router architectures. This work presents a survey of power-saving techniques for efficient NoC designs with a focus on the cache and router components, such as the buffer and crossbar. Nonetheless, the aim of this work is to compile a quick reference guide of power-saving techniques for engineers and researchers. View Full-Text
Keywords: NoC; Cache; power efficiency; low power, CMPs NoC; Cache; power efficiency; low power, CMPs
Show Figures

Figure 1

MDPI and ACS Style

Ofori-Attah, E.; Bhebhe, W.; Agyeman, M.O. Architectural Techniques for Improving the Power Consumption of NoC-Based CMPs: A Case Study of Cache and Network Layer. J. Low Power Electron. Appl. 2017, 7, 14.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop