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Open AccessArticle

A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities

1
Department of Electrical and Computer Engineering, Ben-Gurion University of the Negev, Be'er Sheva 8410501, Israel
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Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel
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Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in IEEE S3S Conference 2014.
Academic Editors: David Bol and Steven A. Vitale
J. Low Power Electron. Appl. 2015, 5(2), 130-150; https://doi.org/10.3390/jlpea5020130
Received: 1 April 2015 / Revised: 3 June 2015 / Accepted: 8 June 2015 / Published: 23 June 2015
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2014)
The pursuit of continuous scaling of electronic devices in the semiconductor industry has led to two unintended but significant outcomes: a rapid increase in susceptibility to radiation induced errors, and an overall rise in power consumption. Operating under low voltage to reduce power only aggravates radiation related reliability issues. The proposed “SEU Hardening Incorporating Extreme Low Power Bitcell Design” (SHIELD) addresses these two major concerns simultaneously. It is based on the concept of gating the conventional cross-coupled inverters while introducing a novel “cut-off” network. This creates redundant storage nodes and eliminates the internal feedback loop during radiation particle impact. The SHIELD bitcell tolerates upsets with charge deposits over 1 pC. Simulations confirm its advantages in terms of leakage power, with more than twofold lower leakage currents than previous solutions when operated at a 700mV supply voltage in a 65 nm process. To validate the bitcell’s robustness, several test cases and special concerns, including multiple node upsets (MNU) and half-select, are examined. View Full-Text
Keywords: soft errors; SEU; critical charge; SRAM; low power; low voltage soft errors; SEU; critical charge; SRAM; low power; low voltage
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Chertkow, O.; Pescovsky, A.; Atias, L.; Fish, A. A Novel Low Power Bitcell Design Featuring Inherent SEU Prevention and Self Correction Capabilities. J. Low Power Electron. Appl. 2015, 5, 130-150.

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