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39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation

Department of Electrical & Computer Engineering, University of Virginia, 351 McCormick Rd., Charlottesville, VA 22904, USA
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J. Low Power Electron. Appl. 2014, 4(3), 252-267; https://doi.org/10.3390/jlpea4030252
Received: 8 July 2014 / Revised: 18 August 2014 / Accepted: 4 September 2014 / Published: 12 September 2014
(This article belongs to the Special Issue Low Power Wireless Sensing and Internet of Things)
A 39 fJ/bit IC identification system based on FET mismatch is presented and implemented in a 130 nm CMOS process. ID bits are generated based on the ΔVT between identically drawn NMOS devices due to manufacturing variation, and the ID cell structure allows for the characterization of ID bit reliability by characterizing ΔVT . An addressing scheme is also presented that allows for reliable on-chip identification of ICs in the presence of unreliable ID bits. An example implementation is presented that can address 1000 unique ICs, composed of 31 ID bits and having an error rate less than 10-6, with up to 21 unreliable bits. View Full-Text
Keywords: chip identification; low-power electronics; radio-frequency identification; wireless sensor networks; PUF chip identification; low-power electronics; radio-frequency identification; wireless sensor networks; PUF
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Bolus, J.F.; Calhoun, B.H.; Blalock, T.N. 39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation. J. Low Power Electron. Appl. 2014, 4, 252-267.

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