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CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations

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TowerJazz Corporation, Migdal Ha’Emek, 10556, Israel
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The Department of Materials Engineering, Technion-Israel Institute of Technology, Haifa 32000, Israel
J. Low Power Electron. Appl. 2012, 2(1), 1-29; https://doi.org/10.3390/jlpea2010001
Received: 12 December 2011 / Revised: 14 January 2012 / Accepted: 16 January 2012 / Published: 27 January 2012
(This article belongs to the Special Issue Industrial Aspects of Low Power Design Recent Trends and Methods)
Power reduction in CMOS platforms is essential for any application technology. This is a direct result of both lateral scaling—smaller features at higher density, and vertical scaling—shallower junctions and thinner layers. For achieving this power reduction, solutions based on process-device and process-integration improvements, on careful layout modification as well as on circuit design are in use. However, the drawbacks of these solutions, in terms of greater manufacturing complexity (and higher cost) and speed degradation, call for “optimized” solutions. This paper reviews the issues associated with transistor scaling and related solutions for leakage and power reduction in terms of topological design rules and layout optimization for digital and analog transistors. For standard cells and SRAMs cells, leakage aware layout optimization techniques considering transistor configuration, stressors, line-edge-roughness and more are presented. Finally, different techniques for leakage and power reduction at the circuit level are discussed. View Full-Text
Keywords: low leakage; low power; layout optimization; transistor scaling; leakage-related-stressors; design-aware leakage reduction low leakage; low power; layout optimization; transistor scaling; leakage-related-stressors; design-aware leakage reduction
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Shauly, E.N. CMOS Leakage and Power Reduction in Transistors and Circuits: Process and Layout Considerations. J. Low Power Electron. Appl. 2012, 2, 1-29.

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