A Physical Unclonable Function Based on a Differential Subthreshold PMOS Array with 9.73 × 10⁻⁴ Stabilized BER and 1.3 pJ/bit in 65 nm

Abstract

This paper introduces a physical unclonable function (PUF) based on a differential array of minimum-sized PMOS devices. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is effectively used to mask potentially unstable response bits. To further improve PUF reliability, spatial majority voting is also implemented, resulting in a near-zero (<$3.12\times {10}^{-9}$) bit error rate (BER) at 1.2 V and 25 $°\mathrm{C}$. Under variations in supply voltage (0.8–1.3 V) and temperature (0–75 $°\mathrm{C}$), the native bit error rate of 3.5% is reduced to $9.73\times {10}^{-4}$ after stabilization, consuming only 1.37 $\mathrm{p}\mathrm{J}$ per output bit.

1. Introduction

Physical unclonable functions (PUFs) play a crucial role in hardware security by providing hard-to-clone digital fingerprints from inherent and unpredictable manufacturing variability in integrated circuits [1,2,3,4,5,6]. From a behavioral perspective, a PUF can be modeled as a hardware primitive that generates unpredictable, unique, and stable output responses (keys), useful for device authentication or data encryption.

To ensure the unpredictability (entropy) of the PUF responses, output bits can be derived by comparing analog quantities that, although nominally identical, inevitably differ due to variations in the CMOS manufacturing process. A typical approach leverages inherent differences in CMOS threshold voltage (${\mathrm{V}}_{\mathrm{th}}$) [4,7]. However, this method alone cannot ensure stability, as the reliability of the PUF responses can be affected by the sensitivity of the analog circuit to supply voltage and temperature fluctuations. Beyond CMOS-based designs, PUFs exploiting non-volatile memories have also been proposed [8,9,10].

Various techniques have been proposed to improve the stability of raw PUFs, at the cost of additional hardware resources and/or increased processing overhead [7]. Adding redundancy through error correction codes (ECCs) is the most common stabilization technique [11,12], but this usually leads to a significant increase in silicon area [13]. Another effective approach is spatial majority voting (SMV), which combines multiple primitive bits to generate a single, more robust response bit [14]. SMV helps to mitigate voltage- and temperature-induced instability by statistically reducing the adverse impact of bit cells with higher sensitivity to voltage and temperature (V/T) variations. Similarly, the same PUF bit can be generated multiple times and then post-processed through a temporal majority voting (TMV) scheme to counteract on-chip noise [15]. Another error-reduction strategy is the key bit preselection, where only bits likely to be stable against V/T variations are chosen, and the remaining unstable ones are masked [16]. This can be implemented directly by evaluating the PUF response bits multiple times across the applicable V/T range, or indirectly by running a “tilt” test [16] to identify the instability level of the bit cells [17,18].

In this paper, we propose a PUF based on a differential PMOS array operating in the subthreshold regime. Each response bit is obtained by comparing the two analog outputs of the differential array through a dynamic comparator with a trimmable offset. This offset is also used to preselect and mask potentially noisy response bits. Additionally, SMV is applied to further improve the PUF stability under different temperature and voltage conditions. It is worth noting that our approach is essentially different from voltage-divider [19] and SRAM-based [20] PUFs. While those schemes rely on digital or mixed-signal principles, our design is intrinsically analog in nature, exploiting voltage comparison across resistive paths rather than relying on digital state retention or simple ratio-based dividers.

The proposed PUF was fabricated using a commercial 65 nm CMOS process and was experimentally evaluated. Our architecture ensures very high integration density since only two PMOS transistors are directly involved in generating each response bit, while the additional circuitry is shared across the entire design. This resource-sharing strategy significantly reduces per-bit overhead, offering a more scalable solution compared to SRAM-based or voltage-divider PUFs, where larger device counts or per-cell resources are required. Across a supply voltage range from 0.8 V to 1.3 V and temperature variations from 0 $°\mathrm{C}$ to 75 $°\mathrm{C}$, our PUF demonstrated a bit error rate (BER) of $9.73\times {10}^{-4}$, with energy consumption of 1.37 $\mathrm{p}\mathrm{J}$ per bit.

The rest of this manuscript is organized as follows. Section 2 details the primitive PUF design, while Section 3 describes the test chip implemented in a 65 nm CMOS and discusses measurement results. Moreover, a comparison with prior state-of-the-art works is also reported. Finally, conclusions are drawn in Section 4.

2. The Physical Unclonable Function (PUF) Primitive

As shown in Figure 1a, the core of our PUF primitive is a differential PMOS array that generates two output voltages, ${\mathrm{V}}_{\mathrm{L}}$ and ${\mathrm{V}}_{\mathrm{R}}$, in response to the input stimuli ${\mathrm{V}}_{\mathrm{R}1}\cdots {\mathrm{V}}_{\mathrm{R}4}$ and ${\mathrm{V}}_{\mathrm{C}1}\cdots {\mathrm{V}}_{\mathrm{C}4}$. Then, a dynamic comparator with an adjustable offset produces the PUF bit response by evaluating the voltage difference between ${\mathrm{V}}_{\mathrm{L}}$ and ${\mathrm{V}}_{\mathrm{R}}$ ($\Delta V_{\mathrm{LR}}$). The comparator offset can be finely tuned using the analog voltage signals VcalP and VcalN. Note that, during the calibration phase, the comparator inputs are provided externally.

2.1. PUF Core

As detailed in Figure 1b, the PUF core essentially consists of two arrays with four columns of four series-connected PMOS devices. The two PMOS arrays share two native transistors, N1– N2, which operate as a low-complexity voltage regulator [21] to maintain the node ${\mathrm{V}}_{\mathrm{X}}$ at a nearly constant value of about 500 $\mathrm{m}\mathrm{V}$. Devices D1 and D2 are diode-connected high-threshold-voltage (HVT) PMOS transistors used to decouple the two arrays.

The main source of entropy in our PUF implementation arises from the ${\mathrm{V}}_{\mathrm{th}}$ difference between two minimum-sized PMOS devices selected from two separate arrays. For a given address, a specific pair of PMOS transistors is selected by applying ${\mathrm{V}}_{\mathrm{R}i}={\mathrm{V}}_{\mathrm{HIGH}}$ to the i-th (where $i=1\cdots 4$) row selection signal, while the remaining rows are driven to ${\mathrm{V}}_{\mathrm{LOW}}$. At the same time, an NMOS transistor is turned on through the signals ${\mathrm{V}}_{\mathrm{C}1}\cdots {\mathrm{V}}_{\mathrm{C}4}$, thereby enabling a single PMOS stack per array. The PUF output is derived based on the voltages ${\mathrm{V}}_{\mathrm{L}}$ and ${\mathrm{V}}_{\mathrm{R}}$, which are determined by the equivalent resistances of their respective transistor stacks. As illustrated in the inset of Figure 1b, these resistances are dominated by the resistances of the selected PMOS devices (the resistance “R” of a selected PMOS is almost four orders of magnitude larger than the resistance “r” of an unselected PMOS), with their ${\mathrm{V}}_{\mathrm{th}}$ directly impacting the resistance values. Charge sharing is not an issue for our design, as ${\mathrm{V}}_{\mathrm{L}}$ and ${\mathrm{V}}_{\mathrm{R}}$ are deliberately maintained to be sensitive to voltage variations to ensure a robust comparison of the resistive paths in the selected PUF columns. The parallel paths of nonselected columns are effectively suppressed, given that their NMOS transistors are off throughout the PUF primitive output bit generation. By selecting the same row and the same column in both arrays, we obtain a total of 16 unique combinations. Note that we restrict the use of the same row selection for both arrays to compare devices with similar body-to-source and source-to-drain voltages, thus minimizing the DIBL and body effects that could potentially produce unwanted bias in the extracted ${\mathrm{V}}_{\mathrm{th}}$ of the transistors. Additionally, limiting the selection of corresponding columns between the two arrays ensures that each transistor contributes to only one unique bit response. This choice avoids any potential correlation between the PUF bit responses. Because corresponding rows and columns are selected at a time in the two arrays, a total of four bits is enough for challenge encoding: two bits are used to select one of the four rows, and two more bits to select one of the four columns.

2.2. Comparator

Each bit of the PUF response is provided by the dynamic comparator shown in Figure 1c. This comparator consists of two stages: a floating inverter amplifier (FIA) used to minimize the impact of the input common mode [22] and an output latch with added PMOS transistors for offset calibration. The calibration process involves introducing a voltage difference ${\mathrm{V}}_{\mathrm{L},\mathrm{ext}}$−${\mathrm{V}}_{\mathrm{R},\mathrm{ext}}$ with the required offset for the comparator and asserting signal ${\mathrm{En}}_{\mathrm{c}}$ (see Figure 1a). The voltage signals VcalP and VcalN are then adjusted to ensure that the comparator toggles reliably between logic ‘1’ and ‘0’.

It is worth noting that PUF cells were designed with minimum-size transistors and without mismatch-reduction techniques to maximize ${\sigma }_{{\mathrm{V}}_{\mathrm{th}}}$. While this increases variability (and thus entropy), it also leads to higher noise, especially under subthreshold bias. To address this trade-off, the offset-trimmable capability of the comparator (discussed in depth in Section 3.2) was used to implement a masking approach aimed at suppressing noisy bits and enhancing key reliability.

3. Results

3.1. Test Chip and Measurement Setup

Our design was fabricated in a commercial 65 nm, 1.2 V CMOS process. Measurements were performed on ten test chips, each integrating 32 PUF primitives with a 32-bit parallel-in serial-out (PISO) shift register to store the PUF output (D), as shown in Figure 2a. The challenge size is 128 bits, structured as 32 sub-challenges of 4 bits each. Every PUF primitive receives a 4-bit sub-challenge and generates a single response bit, resulting in a 32-bit overall response. Consequently, our design supports $2^{128}$ challenge–response pairs (CRPs). At the same time, since each PUF primitive can map its 4-bit input space into 16 uniquely selected output bits, the PUF chip encompasses a total of 32 × 16 = 512 unique response bits.

For each chip, 1000 randomly generated challenges were applied, with each challenge repeated 1000 times, yielding a total of one million response evaluations per chip. Figure 2b depicts the layout of the 8 × 4 PUF array (with magnified PUF core) and the 32-bit shift register. The area footprint of a PUF core, the full array, and the shift register are about $438.70\mu {\mathrm{m}}^2$, 45,286 ${\mu \mathrm{m}}^2$, and $3612\mu {\mathrm{m}}^2$, respectively. Figure 2c,d show the test chip micrograph and measurement setup, which comprises a TUL PYNQ-Z2 board (Tul Corporation, New Taipei City, Taiwan) to extract the PUF keys and a Temptronic ThermoSpot DCP-101 (InTest Thermal Solutions, Mansfield, MA, USA) for temperature conditioning. A PUF key consists of 32 bits, where each bit corresponds to a unique physical PUF primitive.

3.2. Bit Error Rate Characterization

The capability to trim the comparator offset is leveraged to mitigate the impact of on-chip noise, which can cause instability in some output bits when $\Delta V_{LR}$ is small. The following masking procedure is exploited to identify these noisy bits. First, a positive offset of $\delta$$\mathrm{m}\mathrm{V}$ is externally forced to the comparator through the proper VcalP and VcalN values (as extracted during the calibration procedure described in Section 2.2). The bit-stream responses to all addresses are recorded, generating a “positive-offset” map. This process is repeated with a negative offset of −$\delta$$\mathrm{m}\mathrm{V}$ to produce a “negative-offset” map.

Bits that show different logic values between the two maps—suggesting possible susceptibility to noise, since they are produced from $\Delta V_{LR}<\left|\mathrm{offset}\right|$ (voltage masking window)—are flagged as unstable. To enhance PUF robustness, such bits are masked by excluding the specific addresses that generate them. In contrast, bits that consistently exhibit the same logic value across both maps demonstrate better noise immunity, as they result from $\Delta V_{LR}$ exceeding the specified voltage masking window. For a standard PUF operation, the comparator offset is calibrated to approach 0 $\mathrm{m}\mathrm{V}$ to maximize the noise margin. This final calibration step requires fine-tuning the offset adjustment knobs (i.e., VcalP and VcalN in Figure 1c) when comparator inputs are externally short-circuited.

The masking scheme effectively improves the BER, as shown in Figure 3. Under golden key (GK) conditions ($V_{DD}$ = 1.2 $\mathrm{V}$, T = 25 $°\mathrm{C}$), our design shows an average native BER (in 10 samples) of 1.7%. The BER is enhanced by discarding possible noisy bits according to the above-described masking procedure. The average BER is reduced from 0.002 at the $\left|3\mathrm{m}\mathrm{V}\right|$ offset mask (voltage masking window = $6\mathrm{m}\mathrm{V}$) to $2.25\times {10}^{-6}$ at 9 $\mathrm{m}\mathrm{V}$ (voltage masking window = $18\mathrm{m}\mathrm{V}$), while the percentage of discarded bits increases from 6.25% to 25%, respectively. At a 14 $\mathrm{m}\mathrm{V}$ voltage masking window, the obtained BER was $2.84\times {10}^{-5}$, with about 19% discarded bits.

Figure 4 shows the impact of $V_{DD}$ (a) and temperature (b) variations on the BER. The shaded regions represent ±3$\sigma$ confidence intervals around the mean BER values at each measurement point, capturing the statistical spread across all samples. The initial PUF enrollment was performed under GK conditions, and the BER at each operating point was evaluated against that reference. The mean BER increases from 0.0169@1.2 $\mathrm{V}$ to 0.045@0.8 $\mathrm{V}$ and 0.027@1.3 $\mathrm{V}$, while maintaining a constant temperature of 25 $°\mathrm{C}$. At a constant supply voltage of 1.2 $\mathrm{V}$, the native BER reaches its worst case of 0.04 at 0 $°\mathrm{C}$. While our masking scheme improves the BER by discarding unstable noisy bits, this is not enough to significantly reduce the BER when supply or temperature variations occur. This implies that noise is not the only factor causing bit instability; key-bit flipping can also result from differences in the voltage/temperature dependence of the ${\mathrm{V}}_{\mathrm{th}}$ of selected transistors, which may invert the polarity of the ${\mathrm{V}}_{\mathrm{th}}$ mismatch [23]. In addition, other sources of instability may become relevant over time due to PUF aging, such as hot carrier injection (HCI) and bias temperature instability (BTI), both of which can cause shifts in ${\mathrm{V}}_{\mathrm{th}}$ and consequently lead to bit-flip events in the PUF response. These effects can be mitigated by implementing a periodic re-enrollment procedure, allowing the system to adapt to long-term variations and maintain the reliability of the PUF response.

To counteract the effect of inverted polarity of the ${\mathrm{V}}_{\mathrm{th}}$ mismatch, the spatial majority voting (SMV) scheme described in [24] was adopted. In SMV, each bit of the key depends on a group of affiliated bits. For a group of v bits, a fault tolerance of up to (v − 1)/2 bits is guaranteed, where v is an odd integer. SMV was applied to our design in post-processing for a value v = 3. By applying both 14 $\mathrm{m}\mathrm{V}$ voltage masking and SMV-3, the average BER is improved to $1.58\times {10}^{-4}$ at 0.8 $\mathrm{V}$ and to $8.5\times {10}^{-7}$ at 1.3 $\mathrm{V}$, as shown in Figure 4a. For 0 $°\mathrm{C}$ and 75 $°\mathrm{C}$, the average BER is about $4\times {10}^{-4}$ and $2.5\times {10}^{-4}$, respectively (see Figure 4b). Finally, under GK conditions the evaluated BER ranges between 0 and $3.12\times {10}^{-9}$ (which would correspond to one single-bit error within the number of performed tests). Note that during the measurements under GK conditions, no errors were obtained. Taking into account all examined variations in $V_{DD}$ (from 0.8 $\mathrm{V}$ to 1.3 $\mathrm{V}$) and temperature (from 0 $°\mathrm{C}$ to 75 $°\mathrm{C}$), the average native BER is 3.5%. After applying a 14 $\mathrm{m}\mathrm{V}$ voltage masking and SMV-3 stabilization scheme, the average BER is improved to $9.73\times {10}^{-4}$.

3.3. Uniqueness, Uniformity, and Randomness

In this section, our proposed PUF is assessed in relation to figures of merit related to uniqueness, uniformity, and randomness.

Uniqueness: The normalized (to the length of the PUF response) inter-die Hamming distance (HD) is used to estimate the ability to obtain unique responses for the same address across different PUF chips. From Figure 5, the mean (standard deviation) of the inter-PUF HD is 0.4784 (0.0156), which is quite close to the ideal value of 0.5.

Figure 5 also presents the intra-die HD for the native case, the 14 $\mathrm{m}\mathrm{V}$ voltage masking case, and the 14 $\mathrm{m}\mathrm{V}$ masking with SMV-3 case. The intra-die HD was measured across a $V_{DD}$ range of 0.8 $\mathrm{V}$ to 1.3 $\mathrm{V}$ and a temperature range of 0 $°\mathrm{C}$ to 75 $°\mathrm{C}$. Identifiability, defined as the inter/intra-HD ratio [2], has been improved from 13× with no stabilization techniques to 491× with the application of voltage masking and SMV.

Uniformity: It estimates the proportion of 1s and 0s in a PUF key, aiming for equal distribution (50%) to ensure random PUF responses. The Hamming Weight (HW) in the GK condition was evaluated to characterize uniformity. In our PUF, the mean measured HW is 0.504, which is very close to the ideal value (0.5), with a standard deviation of 0.009.

Randomness: The NIST SP 800-22 Revision 1a test suite (National Institute of Standards and Technology, Gaithersburg, MD, USA) was used to assess the randomness of the generated bit sequences. Ten chips were evaluated using 150 consecutive challenges, thus producing independent 4800-bit sequences per chip. As shown in

Table 1. NIST SP800-22 test suite results.

Test Name	Stream Length	Number of Runs	Average p-Value	Pass (%)
ine Frequency	4800	10	0.327	90
Block Frequency	4800	10	0.089	90
Cumulative Sums (Forward)	4800	10	0.076	80
Cumulative Sums (Reverse)	4800	10	0.052	80
Runs	4800	10	0.098	80
Longest Run of Ones	4800	10	0.17	90
FFT	4800	10	0.215	100
Approximate Entropy	4800	10	0.103	80
Serial	4800	10	0.177	80

, the average p-values for all tests exceeded the 0.01 threshold, and the NIST pass-rate criterion (≥80% across 10 runs) was satisfied up to a 4800-bit-stream length per chip. Beyond this length, the pass rate gradually decreases, which is reasonable for PUF applications with modest interrogation rates.

The autocorrelation function (ACF) of our PUF design was also evaluated, as shown in Figure 6. The ACF results demonstrated a 95% confident bound of ±0.00995, closely approximating the ideal value of zero [5].

3.4. Comparison

Table 2. Comparison with the state of the art.

	This Work	JSSC’22 [27]	JSSC’21 [25]	TVLSI’20 [24]	JSSC’20 [28]	JSSC’21 [29]	JSSC’22 [26]	TCAS-I’23 [30]	JSSC’22 [6]
Tech. [nm]	65	180	130	65	28	180	28	40	180
Area [$\mu {\mathrm{m}}^2$]	45,286	300,115	39,935	2750	${8000}^{\left(\mathrm{a}\right)}$	-	15,400	-	-
Area/bit [$\mu {\mathrm{m}}^2$]	18.93	102	8.4	4.38	26	11.48	0.88	19.77	0.66
Area/bit [F2]	4480	3148	497	1036	33,163	354	1125	12,356	20
Array size	512b	8 × 32	16 × 64	16 × 16	128b	64 × 16	-	128b	256 × 32
Uniqueness	0.4784	0.493	0.4873	0.4953	0.4994	0.4946	0.503	0.5027	-	-
Uniformity	0.504	-	-	0.498	0.506	-	0.503	-	-	-
Stabilization method	Offset mask + SMV3	-	HCI Burn-in	TMV + DBD + SMV	Delay calibration + TMV7	TMV11 + Remapping	-	DBD	Trimming + TMV11	Remapping + TMV11
Native BER@GK	1.69%	0.16%	0.29%	0.44%	1.40%	0.43%	1.80%	1.33%	0.937%
Native BER across V/T variations	3.5%	0.65% (b)  0.5% (c)	1.37% (0.7 V)  5.76% (120 C)	3.13%	8.4% (0.4 V)  4.5% (125 C)	3.51% (1.8 V)  4.2% (80 C)	6.70%	0.297%	2.26% (1.9 V) 4.54% (−20 C)
Stabilized BER across V/T variations	$9.73\times {10}^{-4}$	-	0%	0.69%	0.55% (b)  0.078% (c)	0.43% (1.8 V)  0.47% (80 C)	-	$4.88\times {10}^{-8}$	0.331% (1.9 V) 0.633% (−20 C)	0.726% (1.9 V)  1.362% (−20 C)
Masking ratio	19%	-	-	4%	-	-	-	14%	20%	0%
ACF@95%	0.00995	0.0472	0.0334	0.0197	0.041	0.0139	0.007	0.0424	0.007
VDD Range [V]	0.8–1.3	0.4–1.8	0.5–0.7	1–1.4	0.4–1.3	1–1.8	0.75–1.05	0.9–1.4	1.5–1.9
Temperature range [$°$C]	0–75	10–80	−40–120	−50–150	−40–125	0–80	−25–100	−40–125	−20–80
Energy/bit [J]	1.37p	-	2.07f@0.5V	2.98p	2.15p	465p	72f	0.186p	138p
Throughput [b/s]	8 K	-	23 M	8 M	-	0.65 K	12.6 M	69.9 M	1.6 K

^(a) Only array area is reported. ^(b) Obtained over a supply voltage sweep. ^(c) Obtained over a temperature sweep.

summarizes the performance of our PUF as compared to some state-of-the-art designs. With a competitive native BER across supply voltage and temperature variations of 3.5% and an energy consumption of 1.37 pJ per bit, our design can operate efficiently within a supply voltage range from 0.8 $\mathrm{V}$ to 1.3 $\mathrm{V}$, thus outperforming previous works [6,24,25,26], which are limited to narrower voltage operating ranges.

By discarding just 19% of key-bits and applying the SMV-3 stabilization scheme, the BER is lower than $3.12\times {10}^{-9}$ under GK conditions, or equal to $9.73\times {10}^{-4}$ when considering supply voltage and temperature variations, which is an overall improvement with respect to the state of the art. Although the design in [25] achieves a zero BER, it does so after hot carrier injection burn-in, which complicates the PUF enrollment phase.

The design presented in [30] was tested with a larger number of evaluations than our PUF solution and shows a V/T-stabilized BER of $4.88\times {10}^{-8}$. Although both [25,30] achieved a better BER after stabilization, they also exhibit a higher ACF@95%, implying higher correlation among PUF bits. The ACF exhibited by our PUF (0.00995) ranks second best among competitors, surpassed only by [6,26], which both report an ACF of 0.007.

Further BER improvements in our design can be achieved through more aggressive SMV schemes and/or by masking bits with higher comparator offsets at the cost of an increased masking ratio.

To allow a fairer comparison, Figure 7 shows the BERs for all the evaluated designs across voltage ($V_{DD,nom}$ − 0.1 V, $V_{DD,nom}$, $V_{DD,nom}$ + 0.1 V) and temperature (0 $°\mathrm{C}$, 25 $°\mathrm{C}$, and 75 $°\mathrm{C}$) variations. Our PUF exhibits the lowest BER at $V_{DD,nom}$ and $V_{DD,nom}$ − 0.1 V and ranks second at $V_{DD,nom}$ + 0.1 V. Moreover, across temperature extremes (0 $°\mathrm{C}$ and 75 $°\mathrm{C}$), our design maintains competitive BER performance, while achieving the lowest BER value at room temperature (25 $°\mathrm{C}$).

In summary, our PUF solution represents a good trade-off between energy efficiency, reliability (low BER), and security (low ACF). This is achieved at the expense of reduced throughput with respect to the designs presented in [24,25,26,30].

4. Conclusions

We proposed a PUF based on a differential PMOS array and a dynamic comparator with a trimmable offset. Our design achieved a zero BER (<$3.12\times {10}^{-9}$) at $V_{DD}$ = 1.2 $\mathrm{V}$ and T = 25 $°\mathrm{C}$ after applying a bit masking scheme and spatial majority voting. When taking into account supply voltage (0.8 $\mathrm{V}$–1.3 $\mathrm{V}$) and temperature (0 $°\mathrm{C}$–75 $°\mathrm{C}$) variations, the measured native BER was 3.5%, enhanced to $9.73\times {10}^{-4}$ through stabilization techniques, while consuming an energy per bit of about 1.37 pJ.