A Gate Driver for Crosstalk Suppression of eGaN HEMT Power Devices

Abstract

The eGaN HEMT power devices face serious crosstalk problems when applied to high-frequency bridge circuits, thereby limiting the switching performance of these devices. To address this issue, a gate driver is proposed in this paper that can suppress both positive and negative crosstalk of eGaN HEMT power devices, offering the advantages of simple control and easy integration. The basic idea is to suppress positive crosstalk by constructing a negative voltage capacitor, and to suppress negative crosstalk by reducing the impedance of the gate loop. To verify the capability of the proposed gate driver, double-pulse and synchronous Buck test platforms are constructed. The experimental results clearly demonstrate that the proposed gate driver reduces the positive and negative crosstalk spikes by 2.03 V and 1.54 V, respectively, ensuring that the positive and negative crosstalk spikes fall within a safe operating range. Additionally, the turn-off speed of the device is enhanced, leading to a reduction in switching loss.

1. Introduction

GaN power devices have many advantages, such as low on-resistance, excellent thermal conductivity, and fast switching speed [1,2,3,4]. The eGaN HEMT devices are increasingly favored by the market due to their excellent performance, including higher operating frequency, higher blocking voltage, and higher operating temperature [5,6,7,8,9]. In the application of eGaN HEMT power devices, the switching frequency of the power converter can reach several MHz, which improves the power density [10,11,12,13,14]. However, compared with Si devices, eGaN HEMT power devices have lower threshold voltages and smaller gate reverse voltage withstand capabilities, which are easily threatened by crosstalk voltage spikes triggered by higher dv/dt and di/dt in applications such as high-power bridge circuits, and may even lead to device misconduct or gate reverse breakdown conditions [15]. To guarantee the safe and stable operation of power devices, scholars have proposed different solutions to cope with the challenges posed by the crosstalk problem.

There are three main types of crosstalk suppression methods: reducing the amplitude of the device dv/dt and di/dt variations, minimizing the impedance of the drive loop, and using negative voltage turn-off. A specific analysis of these three types is as follows:

(1)

Reducing the amplitude of device dv/dt and di/dt variations [16,17,18]: The fundamental idea is to directly reduce the magnitude of the Miller current. In [17], a capacitor is proposed to be connected in parallel with the gate-source capacitance, which achieves good crosstalk suppression but affects the device’s turn-on speed. In [18], the study implements soft switching to suppress crosstalk voltage spikes by exploiting the critical conduction mode of the current; however, it is difficult to apply in high-power applications. These negative effects limit the practical value of crosstalk suppression circuits.

(2)

Minimizing the impedance of the drive loop [19,20,21]: The fundamental idea is to provide a low-impedance path for Miller current [19]. The effect of crosstalk can be counteracted by actively injecting a current into the gate, with the current flowing in the opposite direction to the Miller current [20]. Adding a Miller clamping circuit to supply a low-impedance branch is proposed to reduce crosstalk [21]. However, the two methods add extra transistors, increasing the power loss.

(3)

Using negative voltage turn-off [22,23,24,25,26,27,28,29]: The fundamental idea is to pull down the positive crosstalk voltage spike below the device threshold voltage to reduce the risk of device misconduct. It is an effective approach to suppress positive crosstalk, and the main measures include adding a negative voltage or a voltage divider circuit. By adding a negative voltage across the device’s gate-source, the positive crosstalk spike would be reduced; however, this approach introduces a larger negative crosstalk spike, which may damage the device [22]. In [23], a RCD (resistor–capacitor–diode) voltage divider circuit is proposed to suppress positive crosstalk, but it affects the turn-on speed of the devices and exacerbates negative crosstalk. The gate driver proposed in [24] enables negative voltage recovery, but does not address the problem of affecting the turn-on speed of the device. On this basis, the multi-level structure, due to the large voltage difference between each level, can suppress crosstalk through active clamping of negative voltage turn-off [25,26,27]. However, employing multiple power supplies and switching devices will increase the cost of circuit design and the complexity of control.

In summary, existing crosstalk suppression circuits have problems such as complicated control and exacerbated negative crosstalk. Therefore, this paper proposes a gate driver that suppresses positive crosstalk by constructing a negative voltage capacitor and suppresses negative crosstalk by minimizing the impedance of the drive loop. The circuit has the advantages of being simple to control and speeding up the device’s turn-off. This paper first analyses the mechanism of crosstalk and explains the operating modes of the proposed gate driver. On this basis, the design criteria for component parameters are presented. Finally, the proposed gate driver is validated by building a double-pulse and synchronous Buck test platform.

2. Crosstalk Mechanism Analysis

To facilitate the analysis of the crosstalk problem formation in eGaN HEMT power devices [22], a simplified equivalent half-bridge circuit is used as an example, as shown in Figure 1. According to Kirchhoff’s formula:

$$\left\{\begin{array}{l}{v}_{\mathrm{dsL}}=v_{\mathrm{gsL}}+v_{\mathrm{gdL}}\\ v_{\mathrm{gsL}}=R_{\mathrm{gL}}(C_{\mathrm{gdL}}{\displaystyle \frac{d{v}_{\mathrm{gdL}}}{dt}}-C_{\mathrm{gsL}}{\displaystyle \frac{d{v}_{\mathrm{gsL}}}{dt}})+v_{\mathrm{gL}}\\ v_{\mathrm{dsL}}=at\end{array}\right.$$

(1)

where a is the rate of change of v_dsL [22], v_gsL and v_gdL are the gate-source and gate-drain voltages of eGaN_L, respectively, C_gsL is the gate-source capacitance, and v_gL is the voltage of the eGaN_L driver IC.

The time-domain expression for crosstalk voltage v_gsL at the gate-source of eGaN_L is derived from Equation (1):

$$v_{\mathrm{gsL}}=(a{R}_{\mathrm{gL}}{C}_{\mathrm{gdL}}+v_{\mathrm{gL}})(1-e^{{\displaystyle \frac{-t}{R_{\mathrm{gL}}(C_{\mathrm{gsL}}+C_{\mathrm{gdL}})}}})$$

(2)

From the above equation, v_gL is 0 V, because the drive signal of the eGaN_L is at a low level at this moment, and the v_gsL increases with t. Then, when t = V_DC/a, the source voltage v_gsL reaches its maximum value, i.e., the maximum positive crosstalk voltage.

$$v_{\mathrm{gsLmax}}=a{R}_{\mathrm{gL}}{C}_{\mathrm{gdL}}(1-e^{{\displaystyle \frac{-V_{\mathrm{DC}}}{a{R}_{\mathrm{gL}}(C_{\mathrm{gsL}}+C_{\mathrm{gdL}})}}})$$

(3)

Based on the analysis above, it is evident that v_gsLmax is positively correlated with bus voltage V_DC, drive resistor R_gL, and gate-drain capacitance C_gdL, but negatively correlated with the gate-source capacitance C_gsL. So, the amplitude of v_gsLmax can be reduced by decreasing R_gL and increasing C_gsL. Equivalently, one can derive the negative crosstalk voltage spike on eGaN_L when eGaN_H is turned off.

3. Design of the Proposed Gate Driver

To solve the problems of the existing crosstalk suppression circuit, such as its complex structure and numerous control signals, this paper proposes a crosstalk suppression gate driver using only passive components. It employs capacitor discharge as the core principle to suppress positive crosstalk voltage spikes and reduces the impedance of the gate driver as the core principle to suppress negative crosstalk voltage spikes.

As shown in Figure 2, the crosstalk suppression gate driver consists of three units. The voltage regulator unit (G₁) includes diode D₃, voltage regulator diode D₄, and drive resistor R₄. The negative voltage unit (G₂) includes capacitor C₁, voltage regulator diode D₂, and resistor R₂. By selecting the appropriate capacitance value for capacitor C₁, negative voltage turn-off can be achieved, thereby inhibiting positive crosstalk. The low-impedance unit (G₃) comprises resistor R₁ and diode D₁. Selecting the appropriate resistance value for resistor R₁ can reduce the gate-source drive loop’s impedance to suppress negative crosstalk. Resistor R₃ is a current-limiting resistor, whose primary function is to ensure the safe operation of voltage regulator diodes D₂ and D₄.

In this paper, the eGaN_L is taken as an example to demonstrate how the proposed gate driver works. Figure 3 shows the drive signals v_H for eGaN_H and v_L for eGaN_L, along with the drain-source v_dsL and gate-source v_gsL voltage waveforms of eGaN_L. The working mechanism of the proposed gate driver can be described as follows.

M₁ [t₀~t₁] [t₄~t₅]: The circuit operating mode is shown in Figure 4a. At this stage, the drive voltage of eGaNH is low and it is turned off, while the drive voltage of eGaNL is high and it is turned on. Additionally, the bus voltage V_DC is applied on both ends of the eGaN_H drain-source pole. The drive voltage amplitude is equal to the sum of the current-limiting resistor R₃’s voltage drop, diode D₃’s voltage drop, the voltage regulator diode D₄’s regulated value, and the charging voltage of capacitor C₁. During this period, the drive voltage charges capacitor C₁, polarizing it with the left terminal negative and the right terminal positive.

M₂ [t₁~t₂]: The circuit operating mode is shown in Figure 4b. This phase is the transition phase of the eGaN_H and eGaN_L; the drive voltages of eGaN_H and eGaN_L are low, and they are turned off. The charge entering capacitor C₁ in the turn-on phase is released through resistor R₂ on the one hand, and through drive resistor R₄ and current-limiting resistor R₃ on the other, constituting two discharge circuits. Diode D₃ and voltage regulator diode D₄ are in the cut-off state, and the discharge loop forms a negative voltage across the C_gsL, which accelerates the turn-off of eGaN_L.

M₃ [t₂~t₃]: The circuit operating mode is shown in Figure 4c. At this stage, the drive voltage of eGaNH is high, and it is turned on. The drive voltage of eGaNL is low, keeping it off. The vdsL of eGaN_L gradually rises to the bus voltage V_DC. During this period, diodes D₁ and D₄ are in the cut-off state, blocking Miller current. Miller current, on the one hand, flows through resistors R₃ and R₄ to drive the GNDL; on the other hand, it flows through the gate-source capacitance C_gsL, capacitor C₁, and resistor R₂ to the GND_L. Currently, the voltage across capacitor C₁ counteracts the voltage across resistors R₃ and R₄, thereby reducing the positive crosstalk. After the positive crosstalk, the eGaN_L remains turned off, capacitor C₁ is discharged through resistor R₂, and the gate-source voltage returns to 0 V.

M₄ [t₃~t₄]: The circuit operating state is shown in Figure 4d. At this stage, the eGaNH begins to be turned off at t₃. The drive signal of eGaNL is low, and it is turned off. Consequently, the VDSL gradually decreases from the bus voltage VDC to 0 V. At this stage, diodes D₃ and D₂ are in the cut-off state, blocking the Miller current. In high-frequency conditions, the impedance of capacitor C₁ is very low and can be approximated as that of a wire. In this stage, resistance R₂ is short-circuited by capacitance C₁. Miller current flows through capacitor C₁, current-limiting resistor R₃, and drive resistor R₄ to load L on one hand, and through capacitor C₁, resistor R₁, and diode D₁ to load L on the other hand. At this time, the two branches of the Miller current are in a parallel relationship, which reduces the voltage drop compared to a single circuit composed of a large resistor, thereby mitigating negative crosstalk.

4. Component Parameters Design

The crosstalk suppression capability of the proposed gate driver directly depends on the parameter values of the components in the circuit. The derivation of the range of the main component parameters is presented as follows.

4.1. Voltage Regulator Diode D₂

When the eGaN_H is turned off and the eGaN_L is turned on, the eGaN_L drive voltage v_gL charges the capacitor C₁, and the voltage at the two terminals of C₁ is determined by the regulator value V_D2 of D₂, which is connected in parallel with it. Capacitor C₁ begins to discharge through resistor R₂ at t₁. It can be obtained:

$$\left\{\begin{array}{l}{v}_{\mathrm{C}1}(t_1)=V_{\mathrm{D}2}\\ v_{\mathrm{C}1}=R_2{C}_1{\displaystyle \frac{d{v}_{\mathrm{C}1}}{dt}}\end{array}\right.$$

(4)

The collation leads to:

$$v_{\mathrm{C}1}=V_{\mathrm{D}2}{e}^{-{\displaystyle \frac{t}{R_2{C}_1}}}$$

(5)

Then the voltage V_t2 across C₁ at t₂ is:

$$V_{\mathrm{t}2}=V_{\mathrm{D}2}{e}^{-{\displaystyle \frac{\Delta T_2}{R_2{C}_1}}}$$

(6)

where ΔT₂ is the duration of the transition phase (from t₁ to t₂).

Since the positive crosstalk suppression phase is much smaller than the time constant R₂C₁ of capacitor C₁ discharging through resistor R₂, it can be assumed that the voltage on capacitor C₁ is unchanged in this phase, and its value is the voltage of C₁ at t₂. The equivalent circuit is shown in Figure 5, the red arrow indicates the direction of current flow. From Figure 5:

$$\left\{\begin{array}{l}{v}_{\mathrm{gsL}}+v_{\mathrm{gdL}}=v_{\mathrm{dsL}}=at\\ i_1=C_{\mathrm{gdL}}{\displaystyle \frac{d{v}_{\mathrm{gdL}}}{dt}}-C_{\mathrm{gsL}}{\displaystyle \frac{d{v}_{\mathrm{gsL}}}{dt}}\\ \left(R_3+R_4\right)i_1-v_{\mathrm{gsL}}-V_{\mathrm{t}2}=0\end{array}\right.$$

(7)

The collation leads to:

$$v_{\mathrm{gsL}}=(a{R}_{\mathrm{gL}}{C}_{\mathrm{gdL}}-V_{\mathrm{t}2})(1-e^{-{\displaystyle \frac{t}{C_{\mathrm{issL}}{R}_{\mathrm{gL}}}}})$$

(8)

where R_gL = R₃ + R₄, C_issL = C_gsL + C_gdL. From Equation (8), v_gsL is positively correlated with t; when t→V_DC/a, v_gsL reaches its maximum value. Currently, it is necessary to meet the condition that the positive crosstalk voltage peak is less than the threshold voltage of the device.

$$aM{R}_{\mathrm{gL}}{C}_{\mathrm{gdL}}-M{V}_{\mathrm{D}2}{e}^{-{\displaystyle \frac{\Delta T_2}{R_2{C}_1}}}<V_{\mathrm{th}}$$

(9)

where Vth represents the device’s threshold voltage, M is for:

$$M=1-e^{-{\displaystyle \frac{V_{\mathrm{DC}}}{a{C}_{\mathrm{issL}}{R}_{\mathrm{gL}}}}}$$

(10)

Capacitor C₁ is discharged through resistor R₂ during t₂~t₃. To prevent the voltage of C₁ from aggravating the negative crosstalk, the voltage at both ends of C₁ needs to be restored to 0 V before t₃, when the negative crosstalk is generated. According to the RC discharge characteristics, the period ΔT₃ from t₂ to t₃ is defined as five times the discharge time constant R₂C₁:

$$\Delta T_3=5R_2{C}_1$$

(11)

Combining Equations (9) and (11) yields:

$$V_{\mathrm{D}2}>(a{R}_{\mathrm{gL}}{C}_{\mathrm{gdL}}-V_{\mathrm{th}}{M}^{-1})e^{{\displaystyle \frac{5\Delta T_2}{\Delta T_3}}}$$

(12)

The negative voltage of capacitor C₁ cannot exceed the reverse breakdown voltage of the device gate, so the value of V_D2 is as small as possible under the condition of satisfying Equation (12) to reduce the reverse voltage on the device gate.

4.2. Capacitor C₁

The value of capacitor C₁ needs to be selected considering the following two factors. The first factor is that the charge stored in C₁, Q_C1, should be larger than the total charge Q_GL of the gate capacitance of the device. When the device is turned off, the polarity of the voltage across C₁ is opposite to that of the gate parasitic capacitance, and C₁ must accommodate the Q_GL. The second factor is that the sum of the energy stored in C₁ and the energy required by the gate of the device should be smaller than the output energy of the driver IC, ensuring the reliable functioning of the driver IC.

For the first factor, to ensure that the amount of charge Q_C1 stored in C₁ at device turn-off is sufficient to counteract the total gate charge Q_GL of the eGaN_L, Q_C1 must satisfy the following condition.

$$Q_{\mathrm{C}1}=C_1{V}_{\mathrm{D}2}>Q_{\mathrm{GL}}$$

(13)

For the second factor, the following condition must be satisfied to ensure that the driver’s IC works properly.

$$P_{\mathrm{D}}>\alpha (P_{\mathrm{C}1}+P_{\mathrm{GL}})$$

(14)

where P_D is the supplied energy of the driver IC, P_C1 is the energy stored in C₁, P_GL is the energy required for the gate of the device, and α is the safety margin factor (α > 1). P_C1 and P_GL can be expressed as follows [30]:

$$\left\{\begin{array}{l}{P}_{\mathrm{C}1}={\displaystyle \frac{C_1{V_{\mathrm{D}2}}^2{f}_{\mathrm{s}}}{2}}\\ P_{\mathrm{GL}}=V_{\mathrm{GL}}{Q}_{\mathrm{GL}}{f}_{\mathrm{s}}\end{array}\right.$$

(15)

where f_s is the switching frequency of the eGaN_L, and V_GL is the drive voltage of the eGaN_L. Combining with Equations (13)–(15), the range of values of C₁ is determined as follows:

$${\displaystyle \frac{Q_{\mathrm{GL}}}{V_{\mathrm{D}2}}}<C_1<{\displaystyle \frac{2(P_{\mathrm{D}}-\alpha V_{\mathrm{GL}}{Q}_{\mathrm{GL}}{f}_{\mathrm{s}})}{\alpha {V_{\mathrm{D}2}}^2{f}_{\mathrm{s}}}}$$

(16)

Under the condition that Equation (16) is satisfied, the value of C₁ should be as small as possible. This will shorten the time for C₁ to discharge, enabling the eGaN device to operate at a higher switching frequency. Meanwhile, combining with Equation (11), the time constant of C₁ discharge, R₂C₁, and the device’s switching frequency f_s should satisfy the following equation:

$$5R_2{C}_1<{\displaystyle \frac{1}{f_{\mathrm{s}}}}$$

(17)

4.3. Resistor R₁

Due to the unidirectional conductivity of diode D₁, resistor R₁ and diode D₁ operate only in the negative crosstalk suppression stage. The forward voltage drop of diode D₁ is small and is ignored for ease of calculation. The equivalent circuit of the negative crosstalk phase is presented in Figure 6, the red arrow indicates the direction of current flow.

Writing Kirchhoff’s laws for Figure 6 yields:

$$\left\{\begin{array}{l}{C}_1{\displaystyle \frac{d{v}_{\mathrm{C}1}}{dt}}+C_{\mathrm{gdL}}{\displaystyle \frac{d{v}_{\mathrm{gdL}}}{dt}}=C_{\mathrm{gsL}}{\displaystyle \frac{d{v}_{\mathrm{gsL}}}{dt}}\\ v_{\mathrm{dsL}}=v_{\mathrm{gdL}}+v_{\mathrm{gsL}}=V_{\mathrm{DC}}-at\\ {\displaystyle \frac{v_{\mathrm{gsL}}+v_{\mathrm{C}1}}{R_1}}+{\displaystyle \frac{v_{\mathrm{gsL}}+v_{\mathrm{C}1}}{R_3+R_4}}=-C_1{\displaystyle \frac{d{v}_{\mathrm{C}1}}{dt}}\end{array}\right.$$

(18)

The collation leads to:

$$v_{\mathrm{gsL}}=-{\displaystyle \frac{a{C}_{\mathrm{gdL}}t}{B}}-{\displaystyle \frac{a{C_1}^2{C}_{\mathrm{gdL}}{R}_{\mathrm{B}}}{B^2{R}_{\mathrm{A}}}}(1-e^{-{\displaystyle \frac{B{R}_{\mathrm{A}}t}{C_1{C}_{\mathrm{issL}}{R}_{\mathrm{B}}}}})$$

(19)

where B = C₁ + C_issL, R_A = R₁ + R₃ + R₄, R_B = R₁ (R₃ + R₄). From Equation (19), the v_gsL of the eGaN_L increases with the increase in t, when t → V_DC/a, v_gsL reaches its maximum value v_gsLm:

$$v_{\mathrm{gsLm}}=-{\displaystyle \frac{V_{\mathrm{DC}}{C}_{\mathrm{gdL}}}{B}}-{\displaystyle \frac{a{C_1}^2{C}_{\mathrm{gdL}}{R}_{\mathrm{B}}}{B^2{R}_{\mathrm{A}}}}(1-e^{-{\displaystyle \frac{B{R}_{\mathrm{A}}{V}_{\mathrm{DC}}}{a{C}_1{C}_{\mathrm{issL}}{R}_{\mathrm{B}}}}})$$

(20)

Figure 7 shows the correlation between resistor R₁ and the peak negative crosstalk voltage v_gsLm, from which it can be obtained that the value of v_gsLm is positively correlated with R₁. Therefore, the smaller the resistance value of R₁, the better. At the same time, as R₁ decreases, the impedance of the gate driver decreases, increasing the device gate-source oscillation. This results in the positive oscillation being too large and exceeding the device threshold voltage, thereby increasing the risk of device misconduct. The relationship between the device gate-source oscillation and R₁ is shown in Figure 8. Therefore, both factors must be considered when selecting the value of R₁.

4.4. Other Component Parameters

For the resistor R₂, which, together with capacitor C₁, determines the discharge rate of C₁, it is also necessary to ensure that capacitor C₁ discharges the stored charge and returns to 0 V at t₃. With the value of capacitor C₁ determined, the following equation can be derived from Equation (11).

$$R_2={\displaystyle \frac{\Delta T_3}{5C_1}}$$

(21)

For the voltage regulator diode D₄, its regulated value, V_D4, and the forward conduction voltage drop, V_D3, of diode D₃, together form the drive voltage, V_GL, of the device. Therefore, it can be obtained that:

$$V_{\mathrm{D}4}=V_{\mathrm{GL}}-V_{\mathrm{D}3}$$

(22)

For the resistor R₃, it acts as a current-limiting resistor for the voltage regulator diodes D₂ and D₄, ensuring that the voltage regulator diodes can function properly. Therefore, the value of resistor R₃ can be determined by the following equation:

$$R_3={\displaystyle \frac{V_{\mathrm{ccL}}-V_{\mathrm{D}2}-V_{\mathrm{D}4}-V_{\mathrm{D}3}}{I_{\mathrm{Z}}}}$$

(23)

where V_D2 and V_D4 are, respectively, the regulated values of regulator diodes, and I_z is the current of the regulator diode during normal operation.

For the resistor R₄, since it and resistor R₃ together form the drive resistance R_gL of the device, it can be obtained that:

$$R_4=R_{\mathrm{gL}}-R_3$$

(24)

For diodes D₁ and D₃, their role is to enable unidirectional current flow in the branch. D₁ is used to prevent current from flowing through resistor R₁ and affecting the turn-on speed when the device is turned on. Diode D₃ is used to prevent capacitor C₁ from discharging rapidly through paths C₁-D₄-D₃-R₃, which affects the effectiveness of the negative voltage suppression and the reduction of positive crosstalk of C₁.

To adapt to the fast-switching characteristics of the eGaN HEMT, Schottky diodes are used for D₁ and D₃. The maximum reverse peak voltages V_RM1 and V_RM3 of the two diodes are selected based on the following: for D₁, the maximum reverse voltage is the sum of the device drive voltage V_GL and the maximum negative voltage of capacitor C₁, which is the regulated voltage value V_D2 of D₂; for D₃, the maximum reverse voltage is the maximum negative voltage of capacitor C₁. The following equation can be derived:

$$\left\{\begin{array}{l}{V}_{\mathrm{RM}1}>V_{\mathrm{GL}}+V_{\mathrm{D}2}\\ V_{\mathrm{RM}3}>V_{\mathrm{D}2}\end{array}\right.$$

(25)

For the auxiliary power supply V_ccL, in order to make D₂ work normally and the eGaN_L gate to reach the set drive voltage V_GL, it is necessary to satisfy the following:

$$V_{\mathrm{ccL}}=\beta (V_{\mathrm{GL}}+V_{\mathrm{D}2})$$

(26)

Considering that there will be some voltage drops inside the driver IC and on resistor R₃ when the device is operating, V_ccL needs to be designed with a margin factor β (β > 1).

5. Experimental Verification

The effect of the proposed gate driver on the suppression of both positive and negative crosstalk, as well as on the switching speed of the device, is tested using a double-pulse test platform. The performance of the proposed gate driver in practical engineering is validated by a synchronous Buck test platform. GS61008P was selected as the test device, which has a rated drain voltage of 100 V, a rated drain current of 90 A, and a total gate charge of 8 nC. To satisfy the test requirements, the oscilloscope is TDS3054C. The voltage and current waveforms are measured using a voltage probe (P6139B) and a current probe (TCPA300).

5.1. Double-Pulse Test

The setup of the double-pulse test platform is shown in Figure 9a, where eGaN_H is an active tube and eGaN_L is a passive tube; V_DC is the input power supply, which is 50 V; C_in is the DC link capacitor, which is 330 μF; L_D is the load inductance, which is 50 μH.

For the regulator diode D₂, the MMSZ5226BT1G with a regulated value of 3.3 V is selected according to Equation (12). For the regulator diode D₄, the MMSZ5232A with a regulated voltage of 5.6 V is selected, as recommended by the datasheet and Equation (22) for a 6 V drive voltage. Considering the reverse voltage stress on the diodes D₁ and D₃, Schottky diodes 1N5818 are selected for D₁ and D₃. According to the technical instruction recommendation, one 10 Ω drive resistor is set after the driver IC of the conventional gate driver for the control group [31]. According to Equations (16)–(24), the value of capacitor C₁ is 6.8 nF, and the values of resistors R₂ to R₄ are 59 Ω, 1 Ω, and 9 Ω, respectively. The supply voltage Vcc_L in the conventional gate driver is set to 6 V. According to Equation (26), the supply voltage Vcc_L in the proposed gate driver is set to 12 V.

During the switching process of the device, due to the interaction between the parasitic inductance and capacitance of the circuit, overshoot and ringing phenomena occur in the drain-source voltage of the device, increasing the risk of drain-source breakdown and thereby affecting the circuit’s safety. In this paper, the method of connecting an RC snubber in parallel with the drain and source of the device is adopted to reduce the ringing. The drain-source waveforms before and after adding the RC snubber are shown in Figure 10. From the results, it is evident that the maximum value of the ring is reduced by 33 V.

Figure 11 shows the gate voltage oscillation under different values of R₁ in the experiment. When R₁ is configured to 1 Ω, the positive gate voltage oscillation reaches 1.82 V, which exceeds the device’s threshold voltage of 1.7 V. Therefore, the device is at risk of misconduct. To prevent device misconduct and minimize negative crosstalk voltage, the value of R1 is ultimately set to 2 Ω.

The double-pulse test results of the devices under the conventional gate driver and the proposed gate driver are shown in Figure 12. A 2.03 V reduction in the positive crosstalk peak is achieved by the proposed gate driver compared to the conventional one, with its positive crosstalk peak falling below the 1.7 V threshold voltage of the GS61008P, thereby reducing the risk of device misconduct. The negative crosstalk spike of the proposed gate driver is reduced by 1.54 V compared to the conventional one, which validates the driver’s negative crosstalk suppression capability.

The proposed gate driver is also applicable to other eGaN devices with different gate charges, such as the GS66508P, which has a gate charge of 5.8 nC. Since the GS66508P can operate at higher voltage levels, larger crosstalk spikes may occur. To achieve better suppression, a regulator diode with a higher regulated voltage should be selected for D₂ to provide a larger negative voltage.

To investigate the effect of the proposed gate driver on the switching performance of the device under test, the switching waveforms of the device are compared under both the conventional gate driver and the proposed gate driver. The turn-on waveforms of the device under these two circuits are shown in Figure 13, from which it can be observed that the turn-on time of the device under the traditional gate driver is 11.43 ns, and the turn-on time under the proposed gate driver is 9.33 ns.

The turn-off waveforms of the device tested under these two gate drivers are shown in Figure 14, from which it can be seen that the turn-off time is 23.49 ns under the conventional gate driver and 13.78 ns under the proposed one. Under the proposed gate driver’s operation, the device’s turn-off speed is enhanced by approximately 41.34% compared to the conventional driver, as C1 enables negative-voltage turn-off of the device.

To investigate the impact of the proposed gate driver on the switching loss of the device, the switching loss of the device is calculated when tested with these two drivers. The turn-on loss is 12.09 μJ and 10.87 μJ in the conventional gate driver and the proposed one, respectively, indicating that the proposed circuit has little impact on the device’s turn-on loss; while the turn-off loss is 1.51 μJ and 0.35 μJ, respectively, indicating that the proposed gate driver is capable to significantly reduce the turn-off loss by 76.82%.

5.2. Synchronous Buck Test

The mechanism of the synchronous Buck test platform is shown in Figure 15a, where eGaN_H is the active tube and eGaN_L is the passive tube; V_DC is the input power supply, which is 50 V; C_in is DC link capacitor, which is 330 μF; L_D is the load inductance, which is 20 μH; C_o is the output voltage regulator capacitance, which is 150 μF; and R_L is the load resistor, which is 1.8 Ω. The synchronous Buck circuit operates at a 500 kHz frequency in the testing of this experiment.

The synchronous Buck test results are shown in Figure 16. The positive crosstalk peak value of the proposed gate driver is reduced by 1.37 V compared to the conventional gate driver, and the negative crosstalk peak value is decreased by 0.91 V. Crosstalk suppression capability is more evident in double-pulse tests than in synchronous Buck circuits. However, the result demonstrates that the proposed gate driver presents a positive crosstalk peak value of less than 1.7 V and a negative crosstalk voltage peak value of more than −10 V under both test conditions, which meets the safe operation requirements.

6. Discussion

To illustrate the characteristics of the proposed gate driver, this paper compares some typical crosstalk suppression circuits by evaluating them from three perspectives: reducing device turn-on speed, mitigating negative crosstalk, and increasing control complexity, as shown in

Table 1. Comparison of different suppression circuits.

Circuits	Reducing Device Turn-on Speed	Exacerbating Negative Crosstalk	Increasing Control Complexity
In [23]	Yes	Yes	No
In [24]	Yes	No	No
In [27]	No	No	Yes
In [28]	No	Yes	No
In [29]	No	No	Yes
This paper	No	No	No

.

• From the perspective of reducing the device turn-on speed, the circuits proposed in [23,24] require charging the auxiliary capacitor placed in parallel with the gate, which in turn reduces the device turn-on speed. The circuits proposed in [27,28,29] do not have auxiliary capacitors in parallel, which does not affect the device turn-on speed. In this paper, the structure without an auxiliary capacitor in parallel is also employed, and its effect on the device’s turn-on speed is negligible.
• From the perspective of exacerbating negative crosstalk, the circuits proposed in [23,28] do not provide an effective discharge path for the negative voltage capacitor, which will exacerbate the gate negative crosstalk and increase the risk of gate reverse breakdown. The circuit proposed in [29] uses an auxiliary MOSFET to clamp the negative voltage without exacerbating the negative crosstalk. The circuits proposed in [27] provide a discharge path for the negative voltage capacitor, allowing for negative voltage recovery without affecting gate-to-negative crosstalk. In this paper, this idea is also adopted to avoid exacerbating the gate negative crosstalk.
• From the perspective of increasing control complexity, the circuits proposed in [27,29] require the introduction of MOSFET, which increases the control complexity. In contrast, the circuits proposed in this paper and the other literature do not require additional control, which improves the ease of application.

7. Conclusions

This paper provides a brief analysis of the crosstalk problem in the half-bridge circuit. It proposes a gate driver that suppresses both positive and negative crosstalk, addressing the limitations of existing crosstalk suppression circuits that require additional control signals or exacerbate negative crosstalk. Double-pulse experiments are conducted to validate the crosstalk suppression capability of the proposed gate driver, which achieves shorter device turn-off time and lower loss compared to the conventional driver. By building a synchronous Buck circuit, the practical value of the proposed circuit is validated in real working conditions, which provides a basis for further improvement in the gate driver.