Ultra-Thin Al₂O₃ Grown by PEALD for Low-Power Molybdenum Disulfide Field-Effect Transistors

Abstract

The lack of ultra-thin, controllable dielectric layers poses challenges for reducing power consumption in 2D FETs. In this study, plasma-enhanced atomic layer deposition was employed to fabricate a highly reliable, ultra-thin aluminum oxide (Al₂O₃) dielectric layer with a thickness of 4 nm. The Al₂O₃ film grown on highly conductive silicon substrates demonstrated a maximum breakdown field of 5.98 MV/cm and a leakage current density as low as 2.48 × 10⁻⁷ A/cm² at 1 MV/cm. MoS₂ FETs incorporating this Al₂O₃ gate dielectric exhibited high-performance n-type characteristics at a low operating voltage of 1 V, achieving a subthreshold swing (SS) of 65 mV/dec, a threshold voltage (V_th) of −0.96 V, a high carrier mobility (μ) of 34.85 cm²·V⁻¹·s⁻¹, and an on/off current ratio exceeding 10⁶. These results highlight the potential of Al₂O₃ in enabling low-power 2D electronic devices for post-Moore applications.

1. Introduction

The dielectric layer in field-effect transistors (FETs) serves as the fundamental enabler of electrostatic control over channel carriers, making its optimization a cornerstone of semiconductor device physics [1,2,3,4,5]. This critical component operates at the quantum-mechanical frontier, where its thickness approaches atomic dimensions (<1 nm in state-of-the-art nodes) while simultaneously needing to satisfy contradictory requirements: achieving high capacitance density for strong gate control and maintaining robust insulation against leakage currents. Silicon dioxide (SiO₂) has dominated microelectronics as the primary gate dielectric for over five decades due to its exceptional insulating properties (bandgap ~ 9 eV), near-perfect Si/SiO₂ interface quality with ultra-low defect density (<10¹⁰ cm⁻² eV⁻¹), and superior process compatibility with thermal oxidation techniques [6,7,8]. However, the relentless scaling of silicon FETs into the sub-nanometer regime has exposed fundamental limitations of SiO₂’s intrinsically low dielectric constant (k ≈ 3.9). The central paradox of SiO₂ scaling arises from its thickness-dependent quantum tunneling behavior, mathematically described by the Wentzel-Kramers-Brillouin (WKB) approximation [9]:

$$J\propto \mathrm{e}\mathrm{x}\mathrm{p}(-{\displaystyle \frac{4\pi t\sqrt{2m^{\ast }\Phi }}{h}})$$

(1)

where J is tunneling current density, t is oxide thickness, m* is effective electron mass, and Φ is barrier height. At thicknesses below 2 nm, direct tunneling currents exceed 10² A/cm², comparable to semiconductor junction currents, rendering conventional oxides impractical for low-power applications. This creates an untenable trade-off: reducing t to maintain capacitance exponentially increases leakage power dissipation, while thicker layers degrade electrostatic control [10]. For 2 nm SiO₂ at 1 V operation, leakage power surpasses 10⁴ W/cm², inducing catastrophic thermal breakdown in dense integrated circuits (ICs). High-k dielectrics (k > 10) address this through enhanced physical thickness while maintaining equivalent oxide thickness (EOT), effectively suppressing Fowler-Nordheim tunneling by 3–5 orders of magnitude [7]. These limitations manifest in critical reliability issues, including thermal breakdown and yield losses driven by exponential increases in power dissipation at advanced nodes.

This technological impasse has driven industrial adoption of high-k gate dielectrics. Materials with enhanced permittivity enable equivalent capacitance at greater physical thicknesses through the relationship C = kε₀A/d, effectively suppressing quantum tunneling leakage while maintaining electrostatic control [1,11,12]. Recent advances in 2D material-based FETs further highlight high-k dielectrics’ critical role in achieving low-voltage operation and enhanced breakdown resilience: Xu et al. [13] demonstrated ultra-thin gadolinium oxychloride (GdOCl) nanosheets synthesized via chloride-assisted chemical vapor deposition (CVD), achieving a high dielectric constant (k = 15.3), exceptional breakdown field strength (>9.9 MV/cm), and minimal gate leakage current (~10⁻⁶ A/cm²). Yin et al. [14] developed 2D single-crystalline Gd₂O₅ through van der Waals epitaxy, exhibiting superior dielectric properties (k = 25.5) with a wide bandgap and ultra-low leakage current (~10⁻⁴ A/cm²). Chen et al. [15] reported CVD-grown Bi₂SiO₅ crystals with k > 30, a large bandgap (~3.8 eV), and van der Waals integration capability. Yi et al. [16] engineered surface-tension-assisted Ga₂O₃ dielectrics on MoS₂ via squeeze printing, achieving k ≈ 30 and a remarkable EOT of ~0.4 nm. Li et al. [17] fabricated 2D perovskite Sr₂Nb₃O₁₀ dielectrics (k = 24.6) with moderate bandgaps, demonstrating compatibility with diverse 2D channel materials. Despite these material innovations, atomic layer deposition (ALD), grown dielectric films remain the industrial standard due to their unmatched process controllability and scalability [18]. A critical challenge in high-k materials lies in the inherent trade-off between dielectric constant and bandgap (Eg)—higher k values typically correlate with reduced Eg, necessitating meticulous optimization of film quality to suppress leakage currents. Among high-k candidates, Al₂O₃ emerges as a premier gate dielectric due to its optimal combination of a wide bandgap (~8.7 eV), high k (~9), robust breakdown field (>10 MV/cm), strong interfacial adhesion, and exceptional thermal/chemical stability [19]. The self-limiting growth mechanism of plasma-enhanced ALD (PEALD) enables atomic-level thickness control (<±1% uniformity), producing pinhole-free Al₂O₃ films with sub-nanometer precision. Bolshakov et al. [20] used an atomic layer deposition process to deposit HfO₂ (~10 nm) and Al₂O₃ (~15 nm) on Si to fabricate MOS capacitors and performed a synthesis gas annealing study to achieve an optimal annealing temperature of 400 °C (1 h) to determine the effect of annealing on interface traps and obtained high-quality dielectric substrates for top-gate MoS₂ FETs. Jeong et al. [21] studied the effect of Al₂O₃ as a passivation layer on the performance of MoS₂ TFT, and it is proved that the passivation of Al₂O₃ film can improve the performance of MoS₂. Tanigawa et al. [22] mainly used the THALD method to study the capacitance-voltage (C-V) characteristics of atomic layer deposition Al₂O₃ film on sulfide MoS₂ film and TiN top-gate metal-insulator-semiconductor MOSFET with sulfide MoS₂ channel. Hong et al. [23] also tested MoS₂ with an Al₂O₃ passivation layer, and the threshold voltage of the drift of the passivation layer was reduced from 10 V to 7.4 V, which proved the protective effect of the Al₂O₃ dielectric layer on the MoS₂ device.

This work systematically investigates PEALD-optimized Al₂O₃ dielectric growth using trimethylaluminum [Al(CH₃)₃] (TMA) and oxygen plasma precursors. Process parameters were varied across growth temperatures: 100 °C, 150 °C, 200 °C, 250 °C, and 300 °C; oxygen plasma power: 20 W, 40 W, 60 W, 80 W, 100 W, and 120 W. The optimized Al₂O₃ film (200 °C, 80 W) demonstrated exceptional dielectric integrity even at 4 nm thickness, enabling high-performance MoS₂ FETs with high breakdown voltage (>5.98 MV/cm), low threshold voltage (V_t = −0.96 V), enhanced carrier mobility (μ > 34.85 cm²·V⁻¹·s⁻¹), near-ideal subthreshold swing (SS = 65 mV/dec), and ultrahigh on/off current ratio (>10⁶). These characteristics satisfy stringent requirements for low-power nanoelectronics, positioning PEALD-Al₂O₃ as a critical enabler for next-generation 2D material-based devices.

2. Results and Discussion

2.1. Characterization of Al₂O₃ Thin Films

Atomic layer deposition technology can precisely control film thickness by alternating the flow of precursors in the reaction chamber. To better explore the relationship between cycle number and thickness, Al₂O₃ films were grown firstly with 25, 35, 40, 60, 80, 100, and 125 cycles under the conditions of a growth temperature of 200 °C and oxygen plasma power of 80 W. Subsequently, the ellipsometer was used to test and fit the thickness of the samples (Figure S1), showing the relationship between cycle number and Al₂O₃ thickness. It can be observed that as the number of growth cycles increases, the thickness of the Al₂O₃ film increases linearly, with each cycle growing approximately ~ 0.1 nm of Al₂O₃, consistent with literature descriptions [24], proving the controllability of the PEALD thickness.

To investigate the suitable growth conditions for Al₂O₃ films, atomic force microscopy (AFM) characterization was conducted on 12.5 nm Al₂O₃ films deposited under varying growth parameters, with arithmetic mean roughness (Ra) values extracted through XEI software (Version 5.0.1) analysis of 2 × 2 μm² scan areas. To identify optimal growth conditions for Al₂O₃ thin films, AFM characterization was systematically conducted on 12.5 nm thick films deposited under temperature/power conditions with varied parameters: 100 °C/80 W, 200 °C/80 W, 200 °C/20 W, 200 °C/120 W, 300 °C/80 W. As illustrated in Figure 1a, the 200 °C/80 W sample demonstrated superior surface quality, lower than other conditions. This exceptional smoothness correlates with enhanced precursor decomposition efficiency at 200 °C, where thermal energy sufficiently activates TMA ligands without inducing excessive plasma-induced surface damage.

Figure 1b shows the XPS analysis of 12.5 nm thick films grown at 100 °C and 20 W, 200 °C and 80 W, and 300 °C and 120 W, and a 4 nm thick film grown at 200 °C and 80 W. The O1s peak for Al₂O₃ is at 531.1 eV, and the C-O peak from methyl groups in trimethylaluminum is at 532.4 eV [25]. It can be seen that under the same thickness, the 200 °C and 80 W condition has the fewest oxygen defects, further indicating the density of the Al₂O₃ film. A thickness-dependent increase in oxygen defect density was observed, with the oxygen vacancy concentration rising by ~14.64% as film thickness decreased from 12.5 nm to 4 nm. This phenomenon is attributed to cycle-dependent precursor reaction kinetics—reduced ALD cycles (from 125 to 40) limit complete ligand exchange between trimethylaluminum methyl groups and oxygen plasma, resulting in residual C-O bonding configurations. The reduction in the number of layers of Al₂O₃ results in a decrease in the proportion of Al-O bonds in the overall O1s spectra. Nevertheless, even the thinnest 4 nm films exhibited lower defect density compared to 12.5 nm counterparts grown under suboptimal conditions (150 °C/20 W).

2.2. Breakdown Field of Al₂O₃ Thin Films

To investigate the effect of different growth temperatures and oxygen plasma power on the electrical properties of Al₂O₃ films. Electrical experiments on Al₂O₃ films grown under different temperatures and power conditions were conducted. Figure 2a shows the breakdown voltage of 125-cycle Al₂O₃ films grown with an oxygen plasma power of 80 W at different temperatures (100 °C, 150 °C, 200 °C, 250 °C, and 300 °C). Among these, the breakdown voltage of the Al₂O₃ film grown at 200 °C is the highest, reaching 6.04 V. Figure 2b shows the breakdown voltage of 125-cycle Al₂O₃ films grown at 200 °C with different oxygen plasma power levels (20 W, 40 W, 60 W, 80 W, 100 W, and 120 W). The breakdown voltage is highest for the film grown with an oxygen plasma power of 80 W. Figure 2c shows the breakdown voltage of Al₂O₃ films grown under the optimal conditions of 200 °C and 80 W, with the number of cycles reduced to decrease the film thickness. It can be seen that the breakdown voltage of films with thicknesses of 2.5 nm and 3.5 nm does not exceed 1 V, which does not meet the requirements for gate dielectrics in field-effect transistors. However, when the thickness is 4 nm, the breakdown voltage increases significantly to 2.39 V. Figure 2d–f present statistical box plots of breakdown voltage reproducibility measured across ten discrete locations on PEALD-grown Al₂O₃ films under varying growth conditions, demonstrating exceptional process stability (details can be found in Figures S2–S4). The tight clustering of breakdown voltages highlights the superior thickness uniformity and defect-free morphology inherent to the PEALD growth mechanism.

2.3. Dielectric Properties of Al₂O₃ Thin Films

For capacitance-voltage (C-V) measurements, a parallel plate capacitor setup was used, as shown in Figure 3a. A 12.5 nm thick Al₂O₃ film was grown on heavily doped silicon, and Au electrodes were evaporated. The relative permittivity can be calculated using the formula:

$${\epsilon }_r={\displaystyle \frac{C\times d}{A\times {\epsilon }_0}}$$

(2)

where ε_r is the permittivity of Al₂O₃, C is the measured capacitance, d is the sample thickness, A is the area of the Au electrode, and ε₀ is the permittivity of free space [26,27]. Figure 3a shows the capacitance density of Al₂O₃ films grown under different conditions over a frequency range of 1 kHz to 1 MHz. It can be observed that the measured capacitance density decreases with increasing voltage and frequency, which is typically observed in incipient ferroelectric ceramics and asymmetric electrode configurations, mainly attributed to the reduction in dipole polarization at high frequencies [28]. Figure 3b shows the capacitance density of Al₂O₃ films grown under different conditions. It can be seen that for the same thickness of 12.5 nm, the film grown at 200 °C and 80 W has the highest capacitance density, reaching 0.6 μF/cm², further proving that these are the optimal growth conditions. As the film thickness decreases, the capacitance density of the Al₂O₃ film increases, reaching 1.73 μF/cm² at 4 nm.

The relative EOT was evaluated using the formula:

$$EOT={\displaystyle \frac{{\epsilon }_{{\mathrm{S}\mathrm{i}\mathrm{O}}_2}\times t}{{\epsilon }_r}}$$

(3)

where ε_SiO2 is the permittivity of SiO₂, t is the sample thickness, and ε_r is the relative permittivity of Al₂O₃ [10]. Figure 3c shows that as the thickness decreases, both the relative permittivity and the effective oxide thickness of the Al₂O₃ film decrease. This phenomenon likely arises from dead-layer effects, where interfacial defect layers (0.5–2 nm thick) form at dielectric/electrode interfaces (e.g., metal-oxide junctions) due to lattice mismatch, oxygen vacancy aggregation, and impurity interdiffusion. These structurally compromised regions exhibit constrained dipole polarization capability, rendering them an electrically inactive “dead layer” with diminished response to applied electric fields, consistent with literature reports.

Table 1. Summary of dielectric properties for Al₂O₃ dielectric.

Material	Method	D (nm)	Temp. (°C)	Ci (nF/cm)	Jleak (A/cm2)	Ref.
Al2O3	ALD	43	33	201	10−7	[29]
Al2O3	PVD	541	RT	117	-	[30]
Al2O3	PLD	80	RT	59.8	10−8	[31]
Al2O3	PEALD	140	150	57	10−9	[32]
Al2O3	ALD	15	400	420	-	[20]
Al2O3	ALD	5	250	660	10−8	[33]
Al2O3	PEALD	4	200	1730	10−7	This work

summarizes the characteristics of various gate dielectrics obtained through different methodologies, where d denotes the dielectric thickness, C_i represents the areal capacitance in the low-frequency region, and J_leak indicates the leakage current density at 1 MV/cm. For thin-film transistor architectures, an ideal gate dielectric material should exhibit high dielectric breakdown strength and near-zero leakage current density. In this context, Al₂O₃ films fabricated via plasma-enhanced atomic layer deposition technology demonstrate these desirable characteristics when employed as gate dielectrics in electronic devices, rendering them an excellent candidate. The 4-nm-thick Al₂O₃ dielectric layer developed in this work exhibits exceptional advantages compared with other reported works: its ultra-thin geometry combined with remarkably high low-frequency areal capacitance. This achievement stems from the exploration of optimal PEALD parameters and interface contact optimization of the Al₂O₃ dielectric layer, which effectively mitigates suppressed oxygen vacancy aggregation and reduces impurity interdiffusion at the dielectric/electrode interface. These synergistic effects substantially inhibit the formation of interfacial defect layers and significantly alleviate the “dead-layer” effect.

2.4. Characterization of Top-Gated MoS₂ FETs with Al₂O₃ Thin Films

To further investigate the application of ultra-thin Al₂O₃ films as dielectric layers in MOSFETs, MoS₂ field-effect transistors were fabricated with a 4 nm thick Al₂O₃ film as the dielectric layer. Figure 4a shows the fabrication process of the MOSFET, where a top-contact process was used. Au bottom electrodes were evaporated, MoS₂ was transferred, and a 4 nm thick Al₂O₃ dielectric layer was grown at 200 °C and 80 W. Subsequently, top Au electrodes were transferred onto the dielectric layer. Figure 4b shows the thickness of the MoS₂ material used. Figure 4c,d show the scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) images of the transistor, respectively. The morphology and elemental composition of the device can be observed, with the bottom and top electrodes being Au, the Al₂O₃ dielectric layer distributed uniformly, and the outline of the MoS₂ layer clearly visible.

2.5. Electrical Performance of MoS₂ FETs

To test the transistor’s performance, electrical measurements were conducted on the MoS₂ field-effect transistor. The transfer and output characteristics are shown in Figure 5a and Figure 5b, respectively. From Figure 5a, it can be seen that the MoS₂ transistor exhibits typical n-type behavior, with a threshold voltage estimated to be −0.96 V. The device achieves an on/off ratio greater than 10⁶, a high carrier mobility of 34.85 cm²·V⁻¹·s⁻¹, and a low subthreshold swing of 65 mV/dec within the measurement range of −1 to 1 V. Figure 5b shows the output characteristics, which exhibit linear behavior at low voltages, indicating good Ohmic contact between the electrodes and the MoS₂ and current saturation at high voltages. Owing to the low carrier concentration of MoS₂, there remains significant potential for enhancement in the metal-semiconductor contacts within the conventional top-contact architecture. The integration approach of bottom-contact electrodes allows the top gate to exert precise control over the semiconductor material that interfaces with the bottom electrodes. This capability serves as an effective means to optimize and improve the metal-semiconductor contacts, thereby addressing the existing limitations in the traditional architecture [34]. At the same time, the coincident area between the top gate electrode and the source leakage electrode is much smaller than the coincident area of the capacitor, and we measured that the coincident area between the electrodes in the MOSFET is less than 50 μm² (Figure 4c), and there is no breakdown of the 10 V voltage in the MOSFET leakage test (Figure S5).

3. Materials and Methods

The fabrication of MoS₂ MOSFETs commenced with bottom electrode patterning via proximity photolithography, followed by gold metallization through thermal evaporation to define source/drain contacts with a 5.5 μm channel width. Few-layer MoS₂ flakes were then mechanically exfoliated using PDMS stamps and precisely aligned onto the prefabricated Au electrodes. The Al₂O₃ films were deposited using alternating exposures of [Al(CH₃)₃] and oxygen plasma, with a growth rate of 0.14 nm per cycle. Each deposition cycle comprised the following steps: TMA exposure (0.06 s), Ar purging (12 s), oxygen plasma exposure (12 s), and final Ar purging (12 s), totaling 40 s per cycle. The process utilized Ar as the carrier gas under a chamber pressure of 0.01 Torr. Finally, top-gate Au electrodes were transfer-printed onto the Al₂O₃ surface using PDMS-mediated van der Waals assembly, completing the MOSFET architecture.

4. Conclusions

In summary, high-quality Al₂O₃ films were grown successfully using PEALD by controlling the growth temperature and oxygen plasma power. By growing high-quality Al₂O₃ films on silicon substrates, wide bandgap, high permittivity, low leakage current, and high breakdown strength were achieved, meeting the requirements for advanced low-power devices. Based on this, high-performance MoS₂ field-effect transistors were fabricated with low working voltage, extremely low subthreshold swing, and high on/off ratio, demonstrating their potential in low-power electronic applications.