Reinforcement-Learning-Based Synthesis of Custom Approximate Parallel Prefix Adders

Approximate hardware units compute a sufficiently accurate result rather than a fully accurate one using fewer transistors or equivalently logic gates than their accurate counterparts. This approach significantly saves energy while maintaining acceptable application-level quality. In this work, we focus on synthesizing custom approximate parallel prefix adders tailored to specific applications. The introduced reinforcement learning (RL) framework co-optimizes application performance and hardware complexity. An RL agent learns approximate addition strategies by exploring the entire design space and receiving feedback from hardware synthesis and application performance. Experimental results demonstrate that the synthesized adders can reduce area and power consumption by 12% and 10%, respectively, on average without compromising the error behavior of the application, or can significantly improve the application’s error metrics without degrading area and power consumption for a variety of practical applications.