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Article

High-Speed and Energy-Efficient Carry Look-Ahead Adder

1
School of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, Singapore
2
Department of Industrial Engineering, Technical University of Sofia, 1000 Sofia, Bulgaria
*
Author to whom correspondence should be addressed.
Academic Editors: Jongsun Park and Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(3), 46; https://doi.org/10.3390/jlpea12030046
Received: 2 June 2022 / Revised: 19 July 2022 / Accepted: 9 August 2022 / Published: 10 August 2022
The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA is not faster than other high-speed adders such as a conditional sum adder (CSA), a carry-select adder (CSLA), and the Kogge–Stone adder (KSA), which is the fastest parallel-prefix adder. Further, in terms of power-delay product (PDP) that characterizes the energy of digital circuits, the conventional CLA is not efficient compared to CSLA and KSA. In this context, this paper presents a high-speed and energy-efficient architecture for the CLA. Many adders ranging from ripple carry to parallel-prefix adders were implemented using a 32-28 nm CMOS standard digital cell library by considering a 32-bit addition. The adders were structurally described in Verilog and synthesized using Synopsys Design Compiler. From the results obtained, it is observed that the proposed CLA achieves a reduction in critical path delay by 55.3% and a reduction in PDP by 45% compared to the conventional CLA. Compared to the CSA, the proposed CLA achieves a reduction in critical path delay by 33.9%, a reduction in power by 26.1%, and a reduction in PDP by 51.1%. Compared to an optimized CSLA, the proposed CLA achieves a reduction in power by 35.4%, a reduction in area by 37.3%, and a reduction in PDP by 37.1% without sacrificing the speed. Although the KSA is faster, the proposed CLA achieves a reduction in power by 39.6%, a reduction in PDP by 6.5%, and a reduction in area by 55.6% in comparison. View Full-Text
Keywords: arithmetic circuits; digital circuits; logic design; adder; high-speed; low power; CMOS arithmetic circuits; digital circuits; logic design; adder; high-speed; low power; CMOS
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MDPI and ACS Style

Balasubramanian, P.; Mastorakis, N.E. High-Speed and Energy-Efficient Carry Look-Ahead Adder. J. Low Power Electron. Appl. 2022, 12, 46. https://doi.org/10.3390/jlpea12030046

AMA Style

Balasubramanian P, Mastorakis NE. High-Speed and Energy-Efficient Carry Look-Ahead Adder. Journal of Low Power Electronics and Applications. 2022; 12(3):46. https://doi.org/10.3390/jlpea12030046

Chicago/Turabian Style

Balasubramanian, Padmanabhan, and Nikos E. Mastorakis. 2022. "High-Speed and Energy-Efficient Carry Look-Ahead Adder" Journal of Low Power Electronics and Applications 12, no. 3: 46. https://doi.org/10.3390/jlpea12030046

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