A g_m/I_D-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

Abstract

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the $g_m/I_D$ approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach.

1. Introduction

At present, the Internet of things (IoT) paradigm is certainly playing a crucial role in the electronic market. It is estimated that more than 30 billion devices are operating in a wide range of applications that span from health-care to agriculture or from industrial manufacturing to automotive, if only to mention the most significant [1]. As is well known, an IoT node is required to have sensing, processing and wireless capabilities [2,3]. Sensing means that the IoT node is interfaced with different kinds of sensors whose analog signals (e.g., temperature, pressure, humidity, CO${}_2$, light, acceleration, etc.) must be read correctly by a proper sensing circuitry. Processing means that the IoT node converts the sensor signals into digital words that are subsequently elaborated, as requested by the given application. Wireless means that the IoT node can send/receive data to/from other nodes or a central processing unit. In addition to these features, it is not uncommon to deal with applications that require energetically autonomous IoT nodes, a section of which is dedicated to the energy harvesting from the environment [4,5,6] and to the management of such harvested power [7,8,9,10]. Whatever the overall application or the specific sub-circuit of the IoT node, energy efficiency is one of paramount factors to survive in the semiconductor market and therefore, wise energy management is a critical task to be addressed during the design phase.

As far as the analog section is concerned, the optimization of the power consumption is mainly accomplished by reducing the operating voltage (1 V or less). This makes the analog section compatible with the same sub-100 nm CMOS process adopted for the digital circuitry, which, in general, occupies the larger amount of silicon area. In the ultra-low-power context, the bias current must also be reduced but at the expense of an increased noise level and of a slower operating speed. In this scenario, the design is not a straightforward task because the technology scaling, the low supply voltage and the low bias current introduce many degenerative effects.

In particular, the reduction in the MOSFET intrinsic gain ($g_m{r}_d\sim 10$), in the dynamic-range and in the signal-to-noise ratio can severely affect the circuit performance [11,12,13,14,15,16,17,18].

Among the different analog circuits that coexist in an IoT node, the operational transconductance amplifier (OTA) is a very common and versatile analog building block [19,20,21,22,23]. For its characteristics, it suits the sensing section, where high precision and moderate bandwidth are required. Due to the reduction in the power supply voltage, multistage topologies are often adopted in these amplifiers, and the optimization of the power consumption must face with noise, dynamic range and speed trade-offs [24,25,26,27,28,29,30,31,32,33,34,35,36]. Ultra-low-power amplifiers cut down the power consumption by biasing all the transistors in the sub-threshold region; however, the speed requirements are more arduous to fulfill also because the slew-rate effects produce serious limitations.

In this paper, we propose a new strategy for the design of ultra-low-power CMOS OTAs using the $g_m/I_D$ approach. Because of its wide knowledge and diffusion, we focus our attention on the three-stage OTA based on the reverse nested Miller compensation with a feed-forward stage (RNMC-FF) and to the case of large capacitive loads. Differently from the past works reported in the literature [37,38,39,40,41,42,43,44,45,46,47,48,49], the proposed design strategy (a) optimizes the speed/dissipation of the amplifier taking into account the settling time and the slew-rate effects; (b) despite being developed for large capacitive loads, it also holds for low-capacitive loads; and (c) despite being developed for the transistors biased in the sub-threshold region, it also holds for the saturation one.

The paper is structured as follows. In Section 2, the OTA topology is presented at the block schematic level and at the transistor-level implementation. Section 3 discusses the design strategy focusing the attention on the $g_m/I_D$ approach, to the sub-threshold region, to the settling time (in terms of small- and large-signal behavior), to the noise specification, and to the optimization of the overall power dissipation. In Section 4, an RNMC-FF three-stage OTA was designed and validated through simulations. Finally, in Section 5, conclusions are drawn.

2. The Three-Stage OTA

The design strategy, which will be introduced in the next section, was applied to the three-stage OTA whose simplified block schematic is shown in Figure 1.

The OTA is made up of three main transconductors, $G_{\mathrm{m}i}$, whose output terminals are connected to the respective i-th node of the overall amplifier. In general, the first transconductor, $G_{\mathrm{m}1}$, is a differential-input stage that better rejects external disturbances. The second and the third transconductors, $G_{\mathrm{m}2}$ and $G_{\mathrm{m}3}$, are implemented using an inverting stage and a non-inverting one. The stability is achieved using the reverse nested Miller compensation (RNMC) made up of a main compensation capacitor, $C_{\mathrm{C}1}$, connected between nodes 3 and 1, and a secondary compensation capacitor, $C_{\mathrm{C}2}$, connected between nodes 2 and 1. It is worth noting that, under equal design specifications, RNMC topologies are intrinsically faster than nested Miller compensated counterparts, since the inner capacitor of the RNMC network is not connected to the output node [50,51].

Some RNMC topologies also adopt a nulling resistor to improve the compensation in terms of bandwidth/consumption performance [51]. However, its resistance must be made proportional to the reciprocal of the amplifier transconductances that, in an ultra-low-power design, can be in the order of few microsiemens or less. Therefore, the resulting resistance would be in the order of hundreds of kiloohms and this, in turn, would worsen both area and noise performance. For this reason, in our design, we preferred not to use any nulling resistor and maintained the simplest possible compensation network.

An additional transconductor, $G_{\mathrm{mf}}$, makes a feed-forward (FF) path that allows some simplifications in the transfer function and helps the final stage drive large capacitive loads. In general, this additional stage is obtained without any further current dissipation but by simply connecting the bias transistor of the third stage to the output node of the first transconductor. Equivalent output resistances, $R_{\mathrm{o}1}$, $R_{\mathrm{o}2}$ and $R_{\mathrm{o}3}$ (not shown in the figure), are assumed as placed between the output node of each i-th transconductor and the ground, respectively. Similarly, parasitic capacitors, $C_{\mathrm{o}1}$ and $C_{\mathrm{o}2}$, are assumed to be in parallel to $R_{\mathrm{o}1}$ and $R_{\mathrm{o}2}$. However, in our models, we can neglect these output resistances and parasitic capacitors, provided that $G_{\mathrm{m}i}{R}_{\mathrm{o}i}\gg 1$ and $C_{\mathrm{C}1},C_{\mathrm{C}2}\gg C_{\mathrm{o}1},C_{\mathrm{o}2}$, respectively.

A transistor-level implementation of the block schematic depicted in Figure 1 is shown in Figure 2. In particular, the circuit is designed using a 65 nm CMOS process and is optimized for operating at the $V_{\mathrm{DD}}=1\mathrm{V}$ taking advantage of the three types of complementary transistors that differ for the threshold voltage.

Low-threshold (LVT) transistors are used for the two input devices of the differential pair. In this manner, we optimize the common-mode input range that is bounded by

$$V_{\mathrm{GS}3,6}-V_{\mathrm{SG}1,2}+V_{\mathrm{SD}1,2}^{\mathrm{sat}}\le V_{\mathrm{cm},\mathrm{in}}\le V_{\mathrm{DD}}-V_{\mathrm{SD}5}^{\mathrm{sat}}-V_{\mathrm{SG}1,2}.$$

(1)

High-threshold (HVT) transistors are used for the current mirror M9-M10. This makes the gate–source voltage of M9 similar to the source–drain bias voltage of M10 and reduces the systematic error of the current mirror due to channel-length modulation. High-threshold transistors are also used in M12 and M14 of the slew-rate (SR) enhancer but their role shall be discussed in the following. Regular-threshold (RVT) transistors are used for the remaining active devices of the OTA.

With respect to the transistor transconductances, the stage transconductances of the block schematic in Figure 1 are $G_{\mathrm{m}1}=g_{m1,2}$, $G_{\mathrm{m}2}=g_{m6}$, $G_{\mathrm{m}3}=g_{m8}(g_{m10}/g_{m9})=r{g}_{m8}$ and $G_{\mathrm{mf}}=g_{m11}$. Bias currents $2I_1$ and $I_2$ are provided through current mirrors M5-MBP and M7-MBP, respectively. As we mentioned before, the feed-forward transconductor, $G_{\mathrm{mf}}$, is implemented by simply connecting the gate of M11 to node $v_1$. This also sets the bias current of the third stage to $I_3={(W/L)}_{11}/{(W/L)}_6{I}_2$. The current across M8 is set to $I_3/r$ through the 1-to-r current mirror M9-M10.

3. Design Strategy of the Three-Stage OTA for Sub-Threshold Region

Whether the analog system is powered by an energy harvesting/scavenging mechanism or by a battery, in analog IoT applications, there are very tight power and energy constraints. Especially when the power of the IoT system is harvested from the outside, the designed circuits cannot exceed the driving capability of the instantaneous current provided by the power source. Consequently, in the designing of the low-power IoT interface circuit, special attention must be paid to optimizing the power consumption [1]. Typical available power levels in IoT are in the order of a few micro-Watts, thus implying that the transistors operate in weak inversion (or sub-threshold).

The proposed design strategy makes use of the $g_m/I_D$ parameter that allows to easily relate the transconductance of a single transistor (or of the amplification stage) to its bias current,  [52,53]. The $g_m/I_D$ parameter permits to describe the MOSFET behavior in short channel devices (even in moderate and weak inversion regions) and to overcome the limitations of the simple square-law MOSFET model.

Thanks to these properties, the $g_m/I_D$ parameter was recently exploited to develop new and interesting design strategies, many of them based on process datasets generated from simulation sweeps (i.e., look-up tables) [54,55,56,57,58]. These strategies allow to investigate a complex design space, made of a large number of degrees of freedoms, in a reasonable simulation time. In this way, the designer can find the optimum point required by the circuit specifications. On the one hand, this approach has the evident advantage of being easily implemented in an automated design procedure, however, on the other hand, the designer risks losing sight of the intimate operation of the circuit, since no design equations are provided.

In contrast to the aforementioned design strategies, we used the $g_m/I_D$ parameter to overcome the limitations of the square-law MOSFET model and the subsequent optimization procedure was conducted by properly manipulating the design equations derived in the next sessions. Moreover, the use of the $g_m/I_D$ parameter also allows to define the same design strategy independently of the bias region of the transistors, that is, whether they are in the saturation region or the sub-threshold one.

Figure 3 reports the plot of $\Gamma =g_m/I_D$ versus the gate–source overdrive ($V_{GS}-V_{\mathrm{TH}}$) for the two regular-threshold complementary devices of our 65 nm CMOS process. The remaining transistors of this process exhibit similar plots. In the case of other nanometer CMOS technologies, the $g_m/I_D$ ratio behaves similarly and there are no practical differences with respect to the curves in Figure 3. In the figure, we labeled the sub-threshold region and the saturation one just because of the sign of the gate–source overdrive. In the following, we shall refer to these two regions even if this abrupt transition does not actually exist, since sweeping the gate–source overdrive from negative to positive values, the channel under the oxide moves smoothly from the weak-inversion region towards the moderate- and strong-inversion regions.

In the analog scenario of a base-band application, a transistor is generally biased in the saturation region but with a small overdrive (i.e., $V_{GS}-V_{\mathrm{TH}}\le 100\mathrm{mV}$). This corresponds to the moderate-inversion region where $\Gamma$ is in the range of 8–16 V${}^{-1}$. When the speed is of maximum concern for the application, the saturation region becomes mandatory and the overdrive is even increased up to well above 100 mV so that $\Gamma$ may reduce below 5 V${}^{-1}$ (strong-inversion region). Conversely, in the ultra-low-power context, the transistor is biased in the sub-threshold region where $\Gamma$ can be as high as 30 V${}^{-1}$ (weak-inversion region). The choice between a low or a high $g_m/I_D$ ratio depends mainly on the application. As known, the sub-threshold region allows good power efficiency but for limited speed requirements. On the contrary, the saturation region allows higher speed requirements but at the expense of poorer power efficiency. Whatever is the region, the key point is that the choice of the $g_m/I_D$ ratio is the starting point in the design of analog circuits [59].

3.1. Small-Signal Analysis and Stability Requirements

Referring to the block schematic in Figure 1 the transfer function of the open-loop gain can be written as

$$T\left(s\right)=\frac{\beta a_0}{1+\frac{s}{{\omega }_d}}·\frac{1+b_{1}s+b_2{s}^2}{1+a_{1}s+a_2{s}^2}$$

(2)

where $\beta$ is the feedback factor (not shown in the figure), $a_0=G_{\mathrm{m}1}{R}_{\mathrm{o}1}{G}_{\mathrm{m}2}{R}_{\mathrm{o}2}{G}_{\mathrm{m}3}{R}_{\mathrm{o}3}$ is the DC gain of the amplifier and ${\omega }_d={\left(R_{\mathrm{o}1}{G}_{\mathrm{m}2}{R}_{\mathrm{o}2}{G}_{\mathrm{m}3}{R}_{\mathrm{o}3}{C}_{\mathrm{C}1}\right)}^{-1}$ is the dominant pole set by the Miller effect on $C_{\mathrm{C}1}$. Since $\beta a_0\gg 1$, the frequencies that play a meaningful role for the stability of the amplifier, lie for $\omega \gg {\omega }_d$ and, thus, the open-loop gain can be simplified into:

$$T\left(s\right)=\frac{1}{s/\mathrm{GBW}}·\frac{1+b_{1}s+b_2{s}^2}{1+a_{1}s+a_2{s}^2}$$

(3)

where $\mathrm{GBW}=\beta a_0{\omega }_d=\beta G_{\mathrm{m}1}/C_{\mathrm{C}1}$ the gain–bandwidth product of the OTA. Finally, assuming the usual and convenient constraint $G_{\mathrm{mf}}=G_{\mathrm{m}3}$ [51,60], the remaining coefficients are:

$$\begin{array}{cc}\hfill a_1& =\frac{C_{\mathrm{C}2}}{G_{\mathrm{m}3}}\left(1+\frac{C_{\mathrm{L}}}{C_{\mathrm{C}1}}\right)\hfill \end{array}$$

(4)

$$\begin{array}{cc}\hfill a_2& =\frac{C_{\mathrm{C}2}{C}_{\mathrm{L}}}{G_{\mathrm{m}2}{G}_{\mathrm{m}3}}\hfill \end{array}$$

(5)

$$\begin{array}{cc}\hfill b_1& =0\phantom{\frac{C_{\mathrm{L}}}{G_{\mathrm{m}3}}}\hfill \end{array}$$

(6)

$$\begin{array}{cc}\hfill b_2& =-\frac{C_{\mathrm{C}1}{C}_{\mathrm{C}2}}{G_{\mathrm{m}2}{G}_{\mathrm{m}3}}\hfill \end{array}$$

(7)

The stability of the amplifier can be achieved using the global separation factors introduced in [60] and used in [61,62]. Without going into theoretical detail, our three-stage OTA can be considered as a feedback circuit with two nested loops, each of which must be frequency compensated. Referring to the block schematic in Figure 1, the internal loop is represented by the amplification stages in the direct path between nodes 1 and OUT, with capacitor $C_{\mathrm{C}1}$ acting as the feedback element. The external loop is identified by the amplification stages in the path between nodes IN and OUT, with the overall feedback factor, $\beta$ (not shown in the figure) acting as the feedback element. The internal separation factor, ${\widehat{K}}_i$, is responsible for the stability of the internal loop while the external separation factor, ${\widehat{K}}_e$, is responsible for the stability of the external one.

As long as the zeros of the open-loop gain are placed above the $\mathrm{GBW}$ of the OTA, the two global separation factors are defined by [60]

$$\begin{array}{cc}\hfill {\widehat{K}}_e& =\frac{{\left(1+b_1\mathrm{GBW}\right)}^2}{a_1\mathrm{GBW}+b_2{\mathrm{GBW}}^2}\hfill \end{array}$$

(8)

$$\begin{array}{cc}\hfill {\widehat{K}}_i& =\frac{{\left(a_1\mathrm{GBW}+b_2{\mathrm{GBW}}^2\right)}^2}{a_2{\mathrm{GBW}}^2\left(1+b_1\mathrm{GBW}\right)}\hfill \end{array}$$

(9)

For the overall circuit to be stable, both the global separation factors must be set to larger than unity (i.e., ${\widehat{K}}_e>1$ and ${\widehat{K}}_i>1$). Among the various possibilities, setting ${\widehat{K}}_e={\widehat{K}}_i=2$ turns the denominator of the closed-loop transfer function into a third-order Butterworth polynomial with a cut-off frequency ${\omega }_0=2\mathrm{GBW}/\left(1+b_1\mathrm{GBW}\right)$. In similar fashion, as demonstrated in [62], setting ${\widehat{K}}_e=8/3$ and ${\widehat{K}}_i=9/4$ optimizes the step response of the OTA, since it minimizes the settling time for a given $\mathrm{GBW}$.

In our specific case, $b_1=0$ and (8) and (9) simplify into:

$$\begin{array}{cc}\hfill {\widehat{K}}_e& =\frac{1}{a_1\mathrm{GBW}+b_2{\mathrm{GBW}}^2}\hfill \end{array}$$

(10)

$$\begin{array}{cc}\hfill {\widehat{K}}_i& =\frac{{\left(a_1\mathrm{GBW}+b_2{\mathrm{GBW}}^2\right)}^2}{a_2{\mathrm{GBW}}^2}\hfill \end{array}$$

(11)

however, multiplying the square of (10) by (11), we obtain the simpler and equivalent set of equations:

$$\begin{array}{cc}\hfill {\widehat{K}}_e\left(a_1\mathrm{GBW}+b_2{\mathrm{GBW}}^2\right)& =1\hfill \end{array}$$

(12)

$$\begin{array}{cc}\hfill {\widehat{K}}_e^2{\widehat{K}}_i{a}_2{\mathrm{GBW}}^2& =1\hfill \end{array}$$

(13)

Substituting (4)–(7) and $\mathrm{GBW}=\beta G_{\mathrm{m}1}/C_{\mathrm{C}1}$ into (12) and (13), the two equations that govern the stability become:

$$\begin{array}{cc}\hfill {\widehat{K}}_e\left(1+\frac{C_{\mathrm{L}}/C_{\mathrm{C}2}}{C_{\mathrm{C}1}/C_{\mathrm{C}2}}-\frac{\beta G_{\mathrm{m}1}}{G_{\mathrm{m}2}}\right)& =\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}·\frac{G_{\mathrm{m}3}}{\beta G_{\mathrm{m}1}}\hfill \end{array}$$

(14)

$$\begin{array}{cc}\hfill {\widehat{K}}_e^2{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}& =\frac{G_{\mathrm{m}2}}{\beta G_{\mathrm{m}1}}·\frac{G_{\mathrm{m}3}}{\beta G_{\mathrm{m}1}}·{\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\right)}^2\hfill \end{array}$$

(15)

where we placed emphasis on four normalized parameters, i.e., $C_{\mathrm{C}1}/C_{\mathrm{C}2}$, $C_{\mathrm{L}}/C_{\mathrm{C}2}$, $G_{\mathrm{m}2}/\left(\beta G_{\mathrm{m}1}\right)$ and $G_{\mathrm{m}3}/\left(\beta G_{\mathrm{m}1}\right)$.

Closed-form solutions can be obtained solving (14) and (15) for $G_{\mathrm{m}2}/\left(\beta G_{\mathrm{m}1}\right)$ and $G_{\mathrm{m}3}/\left(\beta G_{\mathrm{m}1}\right)$, with respect to the normalized capacitances $C_{\mathrm{C}1}/C_{\mathrm{C}2}$ and $C_{\mathrm{L}}/C_{\mathrm{C}2}$. Therefore, the small-signal analysis and the stability requirements lead to the two design equations:

$$\begin{array}{cc}\hfill \frac{G_{\mathrm{m}2}}{\beta G_{\mathrm{m}1}}& =\frac{\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+{\widehat{K}}_e{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}}{\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}}\hfill \end{array}$$

(16)

$$\begin{array}{cc}\hfill \frac{G_{\mathrm{m}3}}{\beta G_{\mathrm{m}1}}& =\frac{{\widehat{K}}_e^2{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}\right)}{{\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\right)}^2\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+{\widehat{K}}_e{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}\right)}\hfill \end{array}$$

(17)

As a final remark, we have to recall that the zeros of the open-loop gain must be placed above the $\mathrm{GBW}$ of the OTA. In our case, the constraint $\mathrm{GBW}<\sqrt{|b_2|}$ must be satisfied, or:

$$\frac{G_{\mathrm{m}3}}{\beta G_{\mathrm{m}1}}·\frac{G_{\mathrm{m}2}}{\beta G_{\mathrm{m}1}}·\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}>1$$

(18)

Substituting (16) and (17) into (18), we obtain the equivalent condition:

$${\widehat{K}}_e^2{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}1}}>1$$

(19)

that is easily guaranteed.

3.2. Settling Time, Slew Rate and Gain–Bandwidth Product

The speed of an amplifier can be defined either in terms of its settling time, $t_s$, or in terms of its gain–bandwidth product, $\mathrm{GBW}$. In single-pole amplifiers that operate under small-signal condition, the two quantities are clearly related as $t_s=|lnϵ|/\mathrm{GBW}$, where $ϵ$ is the maximum allowed settling error. The situation is not so straightforward when slew-rate ($\mathrm{SR}$) limitations occur or in multi-pole feedback amplifiers. As known, the $\mathrm{SR}$ affects the time response in a non-linear fashion, making the final settling time a function of the input step amplitude. In addition, in multi-pole feedback amplifiers, if the compensation network is not well designed, undesired overshoots or oscillations can severely slow down even the benefits of a promising $\mathrm{GBW}$. Furthermore, this problem is even more relevant when the transistors of the amplifier are biased in the sub-threshold region, as in the case of the ultra-low-power context.

Recently, in [60,63], the authors obtained an approximated but useful design equation that estimates the settling time when slew-rate limitations occur in the first stage of the amplifier. With respect to the small-signal settling time, $t_{s0}$, the settling time under slew-rate limitations is:

$$t_s=t_{s0}+\frac{1}{\mathrm{GBW}}\left[\frac{\Delta V_{\mathrm{o}}}{\nu }-\left(1+ln\frac{\Delta V_{\mathrm{o}}}{\nu }\right)\right](\mathrm{for}\Delta V_{\mathrm{o}}>\nu )$$

(20)

where $\Delta V_{\mathrm{o}}$ is the amplitude of the step at the output node of the OTA and $\nu =I_{\mathrm{o}}/\left(\beta G_{\mathrm{m}1}\right)$ is the equivalent saturation limit of the first stage, where $I_{\mathrm{o}}$ is the maximum current that this stage can deliver at its output node.

The small-signal settling time, $t_{s0}$, depends on the $\mathrm{GBW}$ of the amplifier and on the values of the global separation factors, ${\widehat{K}}_e$ and ${\widehat{K}}_i$. As demonstrated in [62], choosing ${\widehat{K}}_e=8/3$ and ${\widehat{K}}_i=9/4$ makes the small-signal settling time lower than that of a single-pole amplifier with the same $\mathrm{GBW}$. In other words, under small-signal condition, the amplifier settles in $t_{s0}\le |lnϵ|/\mathrm{GBW}$ and, to our purposes, (20) can be simplified into:

$$t_s\approx \frac{|lnϵ|+\left[\frac{\Delta V_{\mathrm{o}}}{\nu }-\left(1+ln\frac{\Delta V_{\mathrm{o}}}{\nu }\right)\right]}{\mathrm{GBW}}(\mathrm{for}\Delta V_{\mathrm{o}}>\nu )$$

(21)

that relates the settling time, the slew-rate effects and the gain–bandwidth product.

Equation (21) can be used to obtain the necessary $\mathrm{GBW}$ from a settling-time specification. In fact, supposing that our circuit in Figure 2 is required to settle in $t_s$ seconds within a given percentage error, $ϵ$. The transconductance and the maximum output current of the first stage are $G_{\mathrm{m}1}=g_{m1,2}$ and $I_{\mathrm{o}}=2I_1$, respectively. Assuming that the source-coupled pair, M1–M2, is biased with a known $\Gamma =g_m/I_D$, the equivalent saturation limit results $\nu =2I_1/\left(\beta g_{m1,2}\right)=2/(\beta \Gamma )$. Substituting this latter value in (21) and considering for the output step, $\Delta V_o$, the maximum possible value, $V_{\mathrm{DD}}$, we obtain for the $\mathrm{GBW}$ the design equation:

$$\mathrm{GBW}=\frac{|lnϵ|+\left[\frac{\beta \Gamma V_{\mathrm{DD}}}{2}-\left(1+ln\frac{\beta \Gamma V_{\mathrm{DD}}}{2}\right)\right]}{t_s}$$

(22)

In regard to the slew-rate limitations, a final consideration must be pointed out. The design equation in (21) is valid if the slew-rate limitation resides in the first stage. If this condition is not satisfied, the amplifier can experience a positive feedback connection during its slewing period that leads to large overshoots and degrades the settling-time performance [60,64]. To prevent this situation, as usually done in sub-threshold OTAs, slew-rate enhancers [65,66,67,68] or class-AB topologies [26,69,70,71] must be used for the stages after the first one. In fact, a slew-rate enhancer is adopted for the last stage of the OTA in Figure 2, where the large capacitive load can dominate the slew-rate limitation. The slew-rate enhancer works as follows. Transistors M12–M13 act as a current comparator that senses the output node of the second stage, $v_2$. The current comparator is sized so that, when node $v_2$ is in its quiescent state, transistor M14 is off. Conversely, when node $v_2$ goes down, M12 increases its current so that transistor M14 is switched on and helps M11 discharge the capacitive load.

3.3. Noise Analysis and First-Stage Transconductance

Noise is expressed in terms of input equivalent noise spectral density and, as known, in multi-stage amplifiers it mainly depends on the first stage. Neglecting for simplicity the flicker noise, the general expression of the noise spectral density is:

$$S_{n,\mathrm{in}}=2·4k_{B}T·\frac{2}{3}\frac{1}{G_{\mathrm{m}1}}\left(1+c\right)$$

(23)

where $k_B=13.8·{10}^{-24}\mathrm{J}/\mathrm{K}$ is the Boltzmann’s constant, T is the absolute temperature and c is a coefficient that depends on the topology of the first stage.

Referring to Figure 2, in our specific case, $c=g_{m3,4}/g_{m1,2}\approx 1$ where the latter approximation assumes that the current mirror M3–M4 shares the same $g_m/I_D$ ratio with the differential pair, M1–M2. Solving (23) for $G_{\mathrm{m}1}$, we obtain the design equation:

$$G_{\mathrm{m}1}\approx \frac{32}{3}·\frac{k_{B}T}{S_{n,\mathrm{in}}}$$

(24)

that establishes the minimum first-stage transconductance on the basis of noise specifications.

3.4. Gain–Bandwidth Product and Current Dissipation

As mentioned previously, especially when the power of the IoT system is harvested from the outside, the designed circuits cannot exceed the driving capability of the power source. In low-power interface circuits, the most critical section is represented by the amplifiers used inside since they affect the power consumption significantly [1]. Therefore, the design of the OTA cannot be separated from the optimization of its power dissipation.

The overall current dissipation of the OTA can be minimized for a given $\mathrm{GBW}$ specification. We assume that $\Gamma =g_m/I_D$ is a starting point for the transistors of our amplifier. Specifically, $\Gamma$ is a known quantity set by the designer on the basis of the application [59], and in the ultra-low-power context, it is certainly high (i.e., $\Gamma >20{\mathrm{V}}^{-1}$).

To simplify our discussion, we assume that all the transistors in our amplifier are biased with the same $\Gamma$; however, it is quite effortless to adapt the following analysis when different $\Gamma$ are used. Referring to Figure 2, the total current required to bias the amplifier is:

$$I_T=2I_1+I_2+\left(1+\frac{1}{r}\right)I_3=\left[2+\frac{I_2}{I_1}+\left(1+\frac{1}{r}\right)\frac{I_3}{I_1}\right]I_1$$

(25)

where, as far as the current mirror ratio, r, is concerned, the higher this value is then the lower the total current is since the current in the branch M8–M9 is reduced. However, if the current in M9 is too small, the internal pole at the drain of M8 (whose resistive contribution is $1/g_{m9}$) may decrease too much and degrade the phase margin. As a rule of thumb, a good trade-off for r is between 3 and 6 and in the following, we assume this as a known parameter. Solving (25) for $I_1$ and substituting the result into $\mathrm{GBW}=\beta G_{\mathrm{m}1}/C_{\mathrm{C}1}=\beta \Gamma I_1/C_{\mathrm{C}1}$, leads to:

$$\mathrm{GBW}=\frac{\Gamma \beta I_T}{C_{\mathrm{C}1}\left[2+\frac{I_2}{I_1}+\left(1+\frac{1}{r}\right)\frac{I_3}{I_1}\right]}=\frac{\frac{\Gamma I_T}{C_{\mathrm{C}2}}}{\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\left[\frac{2}{\beta }+\frac{G_{\mathrm{m}2}}{\beta G_{\mathrm{m}1}}+\left(1+\frac{1}{r}\right)\frac{G_{\mathrm{m}3}}{\beta G_{\mathrm{m}1}}\right]}$$

(26)

where, for the latter expression, we considered $G_{\mathrm{m}i}=\Gamma I_i$. Finally, using (16)–(17), we obtain:

$$\mathrm{GBW}=\frac{\frac{\Gamma I_T}{C_{\mathrm{C}2}}}{\frac{2}{\beta }\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+F_c\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\right)+\frac{{\widehat{K}}_e^2{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}\left(1+\frac{1}{r}\right)}{F_c\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\right)}}$$

(27)

where we defined the function:

$$F_c\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\right)=\frac{\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\left(\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+{\widehat{K}}_e{\widehat{K}}_i\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}\right)}{\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}+\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}}$$

(28)

Since the load capacitor, $C_{\mathrm{L}}$, is specified by the application, in the proposed design strategy, we first choose $C_{\mathrm{C}2}$ to be as small as possible but sufficiently higher than the other parasitic capacitive contributions, and then we find the ratio $C_{\mathrm{C}1}/C_{\mathrm{C}2}$ that maximizes the $\mathrm{GBW}$ in (27). This latter operation can be done analytically only for $C_{\mathrm{L}}\gg C_{\mathrm{C}1},C_{\mathrm{C}2}$ or, from a practical point of view, when $C_{\mathrm{C}2}$ can be chosen to be at least two orders of magnitude less than $C_{\mathrm{L}}$. In this case, we can simplify $F_c(C_{\mathrm{C}1}/C_{\mathrm{C}2})\approx {\widehat{K}}_e{\widehat{K}}_i{C}_{\mathrm{C}1}/C_{\mathrm{C}2}$ and the solution that optimizes the $\mathrm{GBW}$ results:

$$\frac{C_{\mathrm{C}1}}{C_{\mathrm{C}2}}\approx \sqrt{\frac{{\widehat{K}}_e\left(1+\frac{1}{r}\right)\frac{C_{\mathrm{L}}}{C_{\mathrm{C}2}}}{\frac{2}{\beta }+{\widehat{K}}_e{\widehat{K}}_i}}$$

(29)

In any other case, the ratio $C_{\mathrm{C}1}/C_{\mathrm{C}2}$ that maximizes the $\mathrm{GBW}$ has to be numerically determined from (27).

3.5. The Design Procedure in the Sub-Threshold Region

In the proposed design procedure, we assume that the power supply, $V_{\mathrm{DD}}$, the load capacitor, $C_{\mathrm{L}}$, and the feedback factor, $\beta$, are established on the basis of the specific application. Other OTA specifications, in general, concern speed requirements (given either in terms of minimum $\mathrm{GBW}$ or in terms of maximum settling time within a given percentage error, $ϵ$) and maximum equivalent input noise. However, as we shall discuss in the following, the design steps that make use of the $\mathrm{GBW}$ specification are a subset of the design steps that make use of the settling-time specification. Therefore, without loss of generality, the proposed design procedure assumes that speed requirements are specified in terms of maximum settling time. As far as the noise is concerned, we shall not consider it for the moment as it will be discussed at the end of the section.

The first step in the design procedure is to choose the transistors’ bias region in terms of $\Gamma =g_m/I_D$. The simplest option is to choose the same $\Gamma$ for all the active devices of the OTA. However, if the designer has the necessity of using different $\Gamma$ for different amplification stages (or groups of transistors), the design procedure can be adapted without much effort. Clearly, in our ultra-low-power context, any value of $\Gamma$ higher than $20{\mathrm{V}}^{-1}$ represents a good design choice. In this step, we also choose the secondary compensation capacitor, $C_{\mathrm{C}2}$, and the ratio r of the current mirror M9–M10. As discussed in Section 3.4, capacitor $C_{\mathrm{C}2}$ has to be set as small as possible provided that, at the end of the procedure, it must result to be sufficiently higher than the other parasitic capacitive contributions. For the current mirror ratio, r, a value between 3 and 6 represents a reasonable choice.

As a second step, using (22), we evaluated the required $\mathrm{GBW}$ from the settling-time specifications. Obviously, if the speed requirements are already given in terms of $\mathrm{GBW}$ we shall use this latter value, instead.

In the third step, we have to assign a proper value to the separation factors and find the optimum ratio $C_{\mathrm{C}1}/C_{\mathrm{C}2}$. In the process, we must consider that setting ${\widehat{K}}_e=8/3$ and ${\widehat{K}}_i=9/4$ optimizes the small-signal settling time, while setting ${\widehat{K}}_e={\widehat{K}}_i=2$ optimizes the closed-loop bandwidth of the amplifier. In our specific case, $C_{\mathrm{L}}$ is large (i.e., about two orders of magnitude higher than $C_{\mathrm{C}2}$) and we can use the approximate Equation (29) to evaluate $C_{\mathrm{C}1}/C_{\mathrm{C}2}$. Otherwise, we have to use (27) to calculate numerically the ratio $C_{\mathrm{C}1}/C_{\mathrm{C}2}$ that maximizes the $\mathrm{GBW}$. Since $C_{\mathrm{C}2}$ is known, we easily evaluate $C_{\mathrm{C}1}$ and, subsequently:

$$G_{\mathrm{m}1}=\frac{C_{\mathrm{C}1}\mathrm{GBW}}{\beta }.$$

(30)

In the fourth step, we use (16)–(17) to evaluate the ratios $G_{\mathrm{m}2}/\left(\beta G_{\mathrm{m}1}\right)$ and $G_{\mathrm{m}3}/\left(\beta G_{\mathrm{m}1}\right)$, and then, the remaining transconductances $G_{\mathrm{m}2}$ and $G_{\mathrm{m}3}$. Of course, we also have $G_{\mathrm{mf}}=G_{\mathrm{m}3}$.

Finally, in the fifth step, we evaluate the stage currents from $I_i=G_{\mathrm{m}i}/\Gamma$.

If noise specification is given, a minimum value for $G_{\mathrm{m}1}$ is established from (24). If this minimum value is higher than that obtained from (30), the procedure shall use the transconductance value sets by the noise specification. This can be accomplished by simply evaluating the maximum between (30) and (24) in the computation of $G_{\mathrm{m}1}$ in the third step of the procedure.

A Matlab script containing the aforementioned design procedure is reported in the Appendix A. The section ‘Specifications’ can be changed by the designer on the basis of the final application. In Section ‘Step 1’, the designer chooses the parameters gamma, CC2 and r. Similarly, in ‘Step 3’ the designer sets the separation factors, Ke and Ki. The remaining part of the script evaluates the amplifier parameters. Note that the procedure can be implemented without any advanced computational tool and that the script is provided just to summarize the steps. In addition, in contrast to those procedures based on more advanced ad hoc tools (such as that offered in [72]), a fine tuning at the circuit simulator level is in general required to finalize the design.

4. OTA Design and Validation Results

The three-stage OTA discussed in the previous sections is designed using a 65 nm CMOS process provided by STMicroelectronics. The power supply is set to 1 V.

As far as the specifications are concerned, the OTA is required to settle in 10 $\mathsf{\mu }$s within the 1-% error, when fed back in unity-gain configuration (i.e., $\beta =1$) and with a load capacitor of 100 pF. These values are inserted in the Matlab script in the Appendix A. The input noise spectral density is specified as 200 $\mathrm{nV}/\sqrt{\mathrm{Hz}}$, however, in the design, it will not play any role as it leads to a minimum transconductance smaller than that set by (30).

To improve the efficiency, we set $\Gamma =30{\mathrm{V}}^{-1}$. We also set $C_{\mathrm{C}2}=150\mathrm{fF}$, $r=4$, ${\widehat{K}}_e=8/3$ and ${\widehat{K}}_i=9/4$. The design procedure leads to the OTA parameters in

Table 1. OTA parameters: results from the design procedure.

Parameter	Value
$G_{\mathrm{m}1}$	$3.97\mathsf{\mu }\mathrm{A}/\mathrm{V}$
$G_{\mathrm{m}2}$	$23.4\mathsf{\mu }\mathrm{A}/\mathrm{V}$
$G_{\mathrm{m}3}$	$26.0\mathsf{\mu }\mathrm{A}/\mathrm{V}$
$G_{\mathrm{mf}}$	$26.0\mathsf{\mu }\mathrm{A}/\mathrm{V}$
$I_1$	132 nA
$I_2$	779 nA
$I_3$	865 nA
$C_{\mathrm{C}1}$	$2.5\mathrm{pF}$
$C_{\mathrm{C}2}$	$150\mathrm{fF}$

. With these parameters, the expected $\mathrm{GBW}$ is 253 kHz.

The circuit is designed in the Cadence environment following the transistor-level schematic in Figure 2. The transistors’ aspect ratios are sized according to the values in Table 1 and are reported in

Table 2. Transistors’ aspect ratios of the OTA (W and L are expressed in microns).

Transistor	Aspect Ratio
M1 *, M2 *	$10/0.25$
M3, M4	$3/0.25$
M5	$6/0.5$
M6	$18/0.25$
M7	$16.5/0.5$
M8	$4.5/0.25$
M9 ${}^{†}$	$6/0.25$
M10 ${}^{†}$	$24/0.25$
M11	$18/0.25$
M12 ${}^{†}$	$0.5/8$
M13	$10/0.5$
M14 ${}^{†}$	$1/1$
MBN	$5/0.5$
MBP	$3/0.5$

* Low-threshold transistor; † High-threshold transistor.

.

The simulated Bode plot of the open-loop gain of the OTA is shown in Figure 4 where the magnitude and the phase are depicted. The two black lines, in the magnitude graph and in the phase one come from the simulation for typical transistor models. The colored regions (violet and green, respectively) are the results of a 400-run Monte Carlo simulation that includes both intra-die (local) and inter-die (global) variations. In the format $\mu \pm \sigma$, the OTA exhibits a DC gain of $82.9\pm 0.24\mathrm{dB}$, a $\mathrm{GBW}$ is $240\pm 27.0\mathrm{kHz}$ and a phase margin of $58.3\pm 2.8\mathrm{deg}$.

The time response to a step input in a unity-gain configuration is reported in Figure 5. Specifically, Figure 5a shows the response to a $\pm 100\mathrm{mV}$ input step and Figure 5b shows the response to a $\pm 500\mathrm{mV}$ input step. Moreover, in these cases, the black lines come from the simulation for typical transistor models while the colored regions are the results of a 400-run Monte Carlo simulation that includes both intra-die (local) and inter-die (global) variations. In the format $\mu \pm \sigma$, for the $\pm 100\mathrm{mV}$ case, the rising step settles in $2.64\pm 0.35\mathsf{\mu }\mathrm{s}$ and the falling step in $3.84\pm 0.48\mathsf{\mu }\mathrm{s}$. When the step increases up to $\pm 500\mathrm{mV}$, slew-rate limitations slow down the OTA response that settles in $6.37\pm 0.94\mathsf{\mu }\mathrm{s}$ and in $6.68\pm 0.57\mathsf{\mu }\mathrm{s}$ for the rising and the falling step, respectively.

Finally, in Figure 6, for the various cases, we plot the distributions of the settling times that come out from the 400-run Monte Carlo simulation. The cases with $\pm 100$-mV steps are reported in Figure 6a,b and the cases with $\pm 500$ mV steps are reported in Figure 6c,d. The distributions confirm again the goodness of the proposed design procedure.

Comparison with Other Recent Sub 1-V Amplifiers

A comparison with a small but significant selection of recent sub 1 V amplifiers has been carried out and the results are summarized in

Table 3. Performance comparison of sub 1 V Amplifiers.

	[26]	[27]	[28]	[29]	This Work
Tech	180 nm	350 nm	180 nm	65 nm	65 nm
Year	2016	2017	2020	2020	2021
Input-driven	Bulk	Gate	Bulk	Bulk	Gate
$V_{\mathrm{DD}}$ (V)	0.7	0.9	0.3	0.25	1.0
$I_{\mathrm{DD}}$ ($\mathsf{\mu }$A)	36.3	27.0	0.043	0.104	2.12
Power ($\mathsf{\mu }$W)	25.4	24.3	0.013	0.026	2.12
$C_{\mathrm{L}}$ (pF)	20	10	30	15	100
$\mathrm{GBW}$ (kHz)	3000	1000	3.1	9.5	253
IFOM${}_s$	1653	370	2146	1370	11,934
FOM${}_s$	2361	412	7154	5481	11,934

.

The selection includes the gate-driven and bulk-driven three-stage OTAs, where the latter group exhibits lower supply voltages. Power dissipations range from few tens of nano-Watts to few tens of micro-Watts. To have an effective comparison, the “speed” of the OTAs was measured in terms of the $\mathrm{GBW}$ instead of using the settling time. This is because the step response was partially characterized in some of the papers used for the comparison. The comparison was made in terms of the two well-known figures-of-merit (FOMs), defined as

$$\begin{array}{cc}\hfill {\mathrm{IFOM}}_s& =\frac{\mathrm{GBW}\times C_{\mathrm{L}}}{I_{\mathrm{DD}}}\left[\frac{\mathrm{MHz}\times \mathrm{pF}}{\mathrm{mA}}\right]\hfill \end{array}$$

(31)

$$\begin{array}{cc}\hfill {\mathrm{FOM}}_s& =\frac{\mathrm{GBW}\times C_{\mathrm{L}}}{V_{\mathrm{DD}}\times I_{\mathrm{DD}}}\left[\frac{\mathrm{MHz}\times \mathrm{pF}}{\mathrm{mW}}\right]\hfill \end{array}$$

(32)

both measuring the goodness of the trade-off between the speed, the load capacitor and the current/power dissipation. From the last two rows of Table 3, it is apparent that the OTA designed with the proposed approach has the best performance even compared to the most recent ultra-low-voltage bulk-driven amplifiers.

5. Conclusions

In this paper we proposed a new strategy for the design of ultra-low-power CMOS OTAs, using the $g_m/I_D$ approach and for the IoT scenario. The design strategy allowed to optimize the speed/dissipation in terms of settling time, including slew-rate effects. Despite the fact that procedure was cut out for large capacitive loads and for transistors biased in the sub-threshold region, it is suitable also for low-capacitive loads or for transistors biased in the saturation region. The procedure was validated through the design of the well-known three-stage RNMC-FF OTA, starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfied the specifications (even under Monte Carlo analysis) thus proving the correctness of the proposed design strategy.