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Article

A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs

by
Sanguk Lee
,
Jinsu Jeong
,
Bohyeon Kang
,
Seunghwan Lee
,
Junjong Lee
,
Jaewan Lim
,
Hyeonjun Hwang
,
Sungmin Ahn
and
Rockhyun Baek
*
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Gyeongbuk, Republic of Korea
*
Author to whom correspondence should be addressed.
Nanomaterials 2023, 13(5), 868; https://doi.org/10.3390/nano13050868
Submission received: 11 February 2023 / Revised: 24 February 2023 / Accepted: 24 February 2023 / Published: 26 February 2023
(This article belongs to the Special Issue Current Advances in Nanoelectronics, Nanosensors and Devices)
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Abstract

:
This study proposed a novel source/drain (S/D) extension scheme to increase the stress in nanosheet (NS) field-effect transistors (NSFETs) and investigated the scheme by using technology-computer-aided-design simulations. In three-dimensional integrated circuits, transistors in the bottom tier were exposed to subsequent processes; therefore, selective annealing, such as laser-spike annealing (LSA), should be applied. However, the application of the LSA process to NSFETs significantly decreased the on-state current (Ion) owing to diffusionless S/D dopants. Furthermore, the barrier height below the inner spacer was not lowered even under on-state bias conditions because ultra-shallow junctions between the NS and S/D were formed far from the gate metal. However, the proposed S/D extension scheme overcame these Ion reduction issues by adding an NS-channel-etching process before S/D formation. A larger S/D volume induced a larger stress in the NS channels; thus, the stress was boosted by over 25%. Additionally, an increase in carrier concentrations in the NS channels improved Ion. Therefore, Ion increased by approximately 21.7% (37.4%) in NFETs (PFETs) compared with NSFETs without the proposed scheme. Additionally, the RC delay was improved by 2.03% (9.27%) in NFETs (PFETs) compared with NSFETs using rapid thermal annealing. Therefore, the S/D extension scheme overcame the Ion reduction issues encountered in LSA and significantly enhanced the AC/DC performance.

1. Introduction

Advanced semiconductor technologies have driven scaling and performance enhancement from planar transistors to fin-shaped field-effect transistors (FinFETs) [1,2,3,4,5,6]. So far, in FinFETs, a larger effective channel width can be achieved by increasing the fin height, and the gate controllability over the channel has been improved by scaling the fin width [4,5,6]. However, the scaling of the fin-shaped channel has some shortcomings, as the fin formation process involves nonuniform fin width and line edge roughness variations [7,8,9]. Conversely, the nanosheet (NS) channels of nanosheet FETs (NSFETs) are less sensitive to process variations because they are formed by epitaxial growth [10,11]. Additionally, because the gate metal surrounds the NS channels, the gate controllability over the channel is enhanced, and improved gate controllability effectively suppresses the off-state current (Ioff). Moreover, because the channel width in the same footprint can be take a wider form than that in FinFETs, a higher on-state current (Ion) can be achieved [10,12]. As a result, NSFETs have a higher Ion/Ioff ratio than FinFETs and are the most suitable device structure for sub-3 nm nodes and beyond.
Recently, three-dimensional integrated circuits (3D ICs) have been extensively investigated to increase the number of transistors in a given area [13,14]. Three-dimensional ICs constitute one of the key technologies that can realize the highest degree of integration among currently developed technologies because transistors can be integrated on the top and bottom layers. In 3D ICs, the thermal budget during top-tier device fabrication is crucial because the thermal process in the top-tier device influences the bottom-tier device [15,16]. Therefore, the thermal budget of each process should be managed such that subsequent processes do not damage bottom-tier devices [16]. Consequently, 3D ICs require low-temperature or selective heating processes to prevent performance degradation in bottom-tier devices [17]. However, conventional source/drain (S/D) activation processes, such as rapid thermal annealing (RTA), heat the entire wafer. Therefore, the performance of bottom-tier devices inevitably deteriorates at high temperatures, resulting in performance degradation [17,18].
Because laser-spike annealing (LSA) activates S/D dopants within local and selective areas in a short time, LSA has been extensively used to moderate thermal issues. In addition, LSA using multiple beams, which can control the depth of the activation area by using different wavelengths, is also being actively studied to anneal the confined area requiring activation. Therefore, LSA can be a promising candidate for resolving performance and reliability issues encountered in 3D ICs [17,18,19].
Additionally, a small number of S/D dopants that deeply diffuse during thermal processing can cause significant performance degradation in advanced nodes, including 3D ICs [20]. For example, deeply diffused S/D dopants increase variability, leading to performance variations and a reduction in yields. Therefore, minimizing the S/D dopant diffusion is crucial to reduce variations and degradations in device behaviors. Currently, LSA is considered to be able to replace RTA in advanced nodes because it can suppress S/D dopant diffusion into the channels thanks to its short dwell time [21]. Accordingly, LSA forms an ultra-shallow junction near the interface of the channel to the S/D; thus, it is expected to suppress short-channel effects (SCEs) and performance degradation. In addition, parasitic capacitance can be significantly decreased because the overlap capacitance between the gate metal and S/D is reduced. Hence, LSA enables various technologies that are not feasible with previous technology nodes, owing to S/D dopant diffusion. Furthermore, diffusionless S/D dopants enable various device structures, which can improve AC/DC characteristics.
This study proposed an S/D extension scheme that can considerably improve the AC/DC characteristics of NSFETs by utilizing the diffusionless S/D activation of LSA for the first time. The S/D extension scheme significantly enhanced the diffusionless advantage of LSA. As a result, higher stress is induced in the NS channels so that carrier mobility can be improved. In addition, carrier concentrations in the NS channels are increased largely because the additional NS etching process extends S/D under the inner spacer regions. The effects of the proposed S/D extension scheme were comprehensively investigated by using a well-calibrated technology computer-aided design (TCAD).

2. Device Structure and Simulation Methodology

We used Synopsys’s Sentaurus to investigate the electrical and mechanical characteristics of the proposed scheme in sub-3 nm node NSFETs [22]. The following models were considered for accurate simulation:
  • The drift-diffusion model was used to solve for the carrier concentration and electrostatic potential, coupled with the density-gradient model to reflect the quantum confinement effects [23,24].
  • The Slotboom bandgap narrowing model was used because the bandgap narrows in highly doped silicon and silicon-germanium alloys [25,26].
  • Mobility models were used to consider the scattering effects (mobility degradation at the interface, inversion, and accumulation layer mobility models) [27,28].
  • The mobility models of electric fields (low-field ballistic mobility and high-field saturation models) were used to consider the quasi-ballistic transport and velocity saturation [29,30].
  • Recombination models (Auger and Shockley–Read–Hall) were used to consider carrier generation and recombination.
  • The deformation potential model was used because the band structure and effective mass of the electron/hole change according to the tensile/compressive stress [31].
The structures of NSFETs using the LSA and proposed S/D extension scheme are shown in Figure 1. Contact poly pitch (CPP) was set to 42 nm, and the fin pitch (FP) was set to 70 nm. NSFETs with buried oxides (BOX) were used to rule out the effects of the parasitic bottom transistor in the punch-through stopper (PTS) region [32,33], and the PTS region was doped at 5 × 1018 cm−3. The S/D doping concentration for the N- and PFETs was set to 4 × 1020 cm−3, and Si0.98C0.02 (Si0.5Ge0.5) was used to induce tensile (compressive) stress in NFETs (PFETs). The contact resistance was set to 1 nΩ/cm2, and the inner spacer thickness (TIS) was set to 5 nm [34]. The physical parameters were well calibrated on the basis of using advanced 5 nm node FinFETs, as shown in [35]. Physical parameters (ballistic coefficient and saturation velocity) that greatly affect the carrier transport were adjusted to calibrate the drain current. The annealing conditions were changed to match the electrical characteristics in the subthreshold region. The drain bias was set to |0.7| V (50 mV) for saturation (linear) operation. The geometric parameters used in the TCAD simulations are listed in Table 1.
The process flow of the proposed S/D extension scheme is shown in Figure 1b. After the dummy gate formation, sacrificial SiGe layers are partially etched to form the inner spacer. Next, the inner spacer is formed by filling the cavities with low-k material. As a result, the exposed surfaces of NS channels are filled by the low-k. Meanwhile, low-k deposited at the edge of the NS channels is etched during the S/D recess process (the structure (1) of Figure 1b). The feasibility of the proposed scheme can be improved by adopting low-k materials with high selectivity to silicon. Because a selectivity difference between the low-k and the silicon allows selective etching, only the NS channel can be etched by using the dry etch process (see the NS-channel-etching process in Figure 1b). Thereafter, S/D can be grown from the etched NS channels into the S/D region, resulting in extended S/D. Therefore, the junction between the S/D and the NS channels moves to the center of the NS with an increase in the etching depth of the NS channel (TSi_E), as shown in Figure 1a. Etching TSi_E greater than the inner spacer thickness (TIS) can remove the NS channels as well as the SiGe sacrificial layers. Therefore, TSi_E is split from 0 to 4 nm because the optimal TIS for performance optimization is 5 nm [34]. Additionally, TSi_E is split only for NSFETs with the LSA process because a slight S/D extension results in severe SCEs in the RTA process.
During the additional NS-channel-etching process, the proposed S/D extension scheme etches the exposed silicon regions of NS channels and PTS. Therefore, when the bottom oxide is not formed, an unintended S/D recess depth can increase the punch-through current [33,36]. However, these issues can be completely solved by forming the BOX. This is because BOX physically blocks an unintended leakage path through the PTS region. Therefore, it is desirable to use NSFETs with BOX in order to prevent an increase in punch-through current that is due to the proposed scheme.
We simulated two device structures assuming the following: (1) the RTA and (2) the LSA process conditions. First, NSFETs with RTA were simulated on the basis of our previous data [35], and the S/D annealing conditions were split into RTA and LSA. Because the S/D dopant gradient along the channel length direction is approximately 3–5 nm/dec in advanced devices [37], the RTA condition for the TCAD simulation was set to match the dopant gradient of advanced devices. S/D dopants were diffused under the same annealing conditions for both N- and PFETs. However, the phosphorus concentration gradient was considerably higher than that of boron, as shown in Figure 2a. This is because phosphorus has a slightly higher diffusivity than boron [38]. Additionally, because the S/D annealing process was performed before removing the SiGe sacrificial layer, Ge diffusion into the NS channel increased the phosphorus diffusivity. Second, the LSA process conditions were set on the basis of our LSA hardware data and applied to the TCAD process simulation.
Figure 2b shows the phosphorus dopant concentrations as a function of the depth. The experiment was designed to investigate the dopant diffusions according to the activation process, and the dopant profile of phosphorus was measured by using secondary ion mass spectroscopy (SIMS). Phosphorus dopants were implanted into the wafer with a dose of 5 × 1014 cm−2 and an energy of 40 keV. The black line in Figure 2b represents the ion implantation results before the dopant activation processes, and the depth with a peak concentration of phosphorus ion (CP) was 60.7 nm. The blue line in Figure 2b shows the phosphorus profiles after the RTA thermal treatment. Phosphorus dopants were largely diffused, and the CP was moved from 60.7 nm to 34.2 nm. Accordingly, because the RTA process can diffuse S/D dopants deeply into the channels, RTA should be avoided for advanced logic devices.
On the other hand, the CP after LSA was 58.5 nm, and the difference from the phosphorus profile before thermal annealing was negligible. The diffusionless phosphorus profile can be achieved because the LSA activates the S/D dopants within a short dwell time. Therefore, a super-steep junction can be assumed for the TCAD simulation thanks to the diffusionless features. Therefore, a super-steep junction of less than 1 nm/dec was reflected, and fully activated S/D dopants were assumed for the TCAD simulation.

3. Results and Discussion

The transfer curves of NSFETs according to TSi_E are shown in Figure 3. Ioff was matched at 1 nA for a performance comparison. To simplify the notation, we defined NSFETs by using the RTA process as NS-RTA and NSFETs using the LSA process as NS-LSA. The drain current of the NS-RTA has a higher Ion than that of the NS-LSA when TSi_E is lower than 2 nm. However, the Ion of NS-LSA significantly increased as TSi_E increased; hence, NS-LSA with a TSi_E of 2–4 nm outperformed NS-RTA. Additionally, although TSi_E decreased the channel length, no significant SCEs were observed, owing to the diffusionless features of LSA. Therefore, the S/D extension scheme with the LSA can effectively improve the DC characteristics of NSFETs compared with the RTA.
As shown in Figure 4, Ion increases as TSi_E increases, where Ion is the drain current value extracted at |Vgs| = 0.7 V and |Vds| = 0.7 V. In NS-LSA at TSi_E = 0 nm, Ion degraded by over 15% compared with NS-RTA. However, the Ion of NS-LSA could be improved by applying the proposed S/D extension scheme, and a considerably higher Ion was observed when TSi_E was larger than 2 nm. Ion increased by 5.92% (17.1%) for the NFETs (PFETs) compared with the NS-RTA. Additionally, Ion increased by up to 21.7% (37.4%) in NFETs (PFETs) compared with NS-LSA (TSi_E = 0 nm). Therefore, the benefit of using LSA with the S/D extension scheme makes it the best solution to boost the performance of NS-LSA. Notably, NS-LSA, which did not apply the proposed scheme (TSi_E = 0 nm), exhibited a much lower Ion than NS-RTA.
The subthreshold swing (SS) according to TSi_E and the conduction band energy (EC) of NFETs along the channel length direction to explain the reason for the Ion degradation in NS-LSA at TSi_E = 0 nm are shown in Figure 5. The LSA minimized S/D dopant diffusion, and the SS was improved in NS-LSA compared with NS-RTA (Figure 5a). Because a high-energy barrier height (Φb) is maintained thanks to the diffusionless S/D dopant in NS channels of NS-LSA, excellent gate controllability over the NS channels improved SS. Therefore, it is critical for advanced devices to suppress the S/D dopant diffusion because the lowered Φb results in SCEs and SS degradation. The SS was improved by 2 mV/dec (5 mV/dec) in the n-type (p-type) NS-LSA at TSi_E = 0 nm compared with NS-RTA. However, SS significantly degraded as TSi_E increased because the channel length was decreased during NS channel etching. Although the activation of S/D dopants was almost diffusionless, the shorter distance between the source and the drain induced degradation behavior. Consequently, the SS of NS-LSA exceeded that of NS-RTA when TSi_E was greater than 2 nm, as shown in Figure 5a.
Although LSA provided better a SS value through its excellent gate controllability, Ion did not improve in NS-LSA (TSi_E = 0 nm) compared with RTA (Figure 4). This is because the high- Φb owing to the lower dopant concentration in the S/D extension region resulted in a significant Ion reduction (Figure 5b). Φb was increased by 82 meV in NS-LSA; hence, Φb offset the improvement in SS. Therefore, a novel process scheme must be introduced to enable the use of the LSA. The reason for the increase in Ion for NS-LSA is shown in Figure 6 and Figure 7.
The increase in Ion with a large TSi_E was induced by strain effects along the channel length direction (SZZ). As the NS channels are etched, the S/D volume increases and the channel length decreases; thus, higher stress was induced in the NS channels (Figure 6a). The proposed S/D extension scheme effectively induced higher stress in the NS channels. The stress difference under the inner spacer region was small compared with that under RTA and LSA with TIS_E = 0 nm; however, SZZ significantly increased when TSi_E increased from 0 to 4 nm (Figure 6b). The average |SZZ| at the center of the NS channels (top, middle, and bottom) is shown in Figure 6c; the SZZ values for the volume from −5 to 5 nm were averaged. As TSi_E increased, an increase in stress of over 25% was induced for both N-/PFETs. The stress induced in the channel dominantly affects electron/hole mobility. In particular, the tensile stress along the channel length direction increases the electron mobility, and the compressive stress increases the hole mobility. Because the average tensile (compressive) stress over the NS channels was improved in NFETs (PFETs), higher stress can significantly increase electron (hole) mobility.
Carrier density was also a crucial factor for Ion enhancement. Figure 7 shows the electron density (eDensity) profiles according to the TSi_E in NFETs, and eDensity profiles were extracted at an on-state bias (Vgs = Vds = 0.7 V). In NS-LSA (TSi_E = 0 nm), eDensity under the inner spacer was not large, because the S/D dopants were not largely diffused into the NS channels. On the other hand, eDensity under the inner spacer greatly increased as TSi_E increased, and this is because a high-doped S/D region replaced the region with low-doped NS channel regions. This is greatly related to the extension region resistance because the parasitic resistance varies according to the extension region with low carrier concentrations. As a result, carrier concentrations in the NS channels of NS-LSA (TSi_E = 4 nm) increased the Ion compared to NS-LSA (TSi_E = 0 nm). Therefore, it can be concluded that the main factors increasing the Ion in the proposed S/D extension structure are the stress-boosting and carrier concentrations.
Although the Lg decreases according to the scaling of NSFETs, the TIS cannot be freely scaled, owing to the trade-offs between the parasitic resistance and the parasitic capacitance [36]. Therefore, TIS would be maintained at around 5 nm for sub-3 nm nodes and beyond, and the parasitic resistance could be the main factor hindering the scaling of the NSFETs. This is because the ratio of the extension region over the total NS channel region highly increases as the Lg scales down. As a result, controlling the parasitic resistance is the core technology for the further scaling of NSFETs. Because the proposed scheme controls the parasitic resistance by replacing the high-resistance regions with low-resistance regions, the proposed scheme can be used as a core technology for the further scaling of NSFETs.
Because the proposed scheme decreased the distance between the gate and the S/D, the electric field between the gate metal and the S/D significantly increased. The overlap capacitance (Cov) increased according to TSi_E, so the deeply formed S/D extension increased the gate capacitance (Cgg), as shown in Figure 8a. Therefore, NS-LSA with TSi_E = 0 nm can maximize the diffusionless advantage in terms of gate capacitance, but a decrease in the Ion offsets the reduction in the parasitic capacitance. The RC delay according to TSi_E is shown in Figure 8b. In the NFETs, the RC delay significantly decreased as TSi_E increased; however, a slight increase in the RC delay was observed at TSi_E = 4 nm. This is because the SCEs and parasitic capacitance degraded the RC delay. However, in PFETs with TSi_E = 4 nm, the RC delay can be improved by 9.2% compared with that using RTA. Compared with NS-RTA, Cgg was increased by 6.1% in NS-LSA (TSi_E = 4 nm), but Ion was improved by 17.1%. As a result, RC delay degradation owing to the parasitic capacitance could be suppressed.
Although NS-LSA at TSi_E = 0 nm exhibited the smallest Cgg, RC delay cannot be improved, owing to the unintended high Φb. A 24.2% RC delay degradation was observed when compared to RTA. This means that the LSA process can cause negative effects on device behaviors. Therefore, using the LSA process alone has no advantages in terms of AC/DC performances, but it is advantageous when used with a new process and device structures. The proposed S/D extension scheme, which adds only one process step, effectively decreased the RC delay by up to 9.27% through stress-boosting and high carrier concentrations in NS channels. Therefore, the S/D extension scheme is expected to be widely used to improve performance for further scaling.

4. Conclusions

This study proposed a novel S/D extension scheme using the LSA process for NSFETs, which increased Ion by boosting the channel stress and carrier concentrations. The LSA process activated S/D dopants without diffusion, so a new process scheme that was not feasible, owing to the S/D dopant diffusions, can be applied. NS-LSA (TSi_E = 0) had an ultra-shallow S/D-NS junction, and the Cgg was improved thanks to the Cov reduction. However, the Ion was degraded by 15.8% (20.3%) in NFETs (PFETs) owing to its high-energy barrier height. Although the SS was slightly degraded as the TSi_E increased, a great increase in Ion was observed thanks to the higher stress and carrier concentrations compared with the NS-LSA (TSi_E = 0 nm). On the other hand, the proposed S/D extension scheme shifted the junction toward the center of the NS channels. A large S/D volume induced higher stress and more carriers in NS channels compared to NS-RTA. Consequently, Ion increased by up to 5.92% (17.1%) in NFETs (PFETs) thanks to the strain effects, compared with NS-RTA. Furthermore, although the Cgg increased, owing to the increase in the overlap capacitance, as TSi_E increased, a better enhancement in Ion improved the RC delay by 2.03% (9.27%) in NFETs (PFETs) compared with NS-RTA. Hence, the proposed S/D extension scheme is expected to be a key technology for improving the performance of NSFETs in heterogeneous 3D ICs.

Author Contributions

Conceptualization, S.L. (Sanguk Lee); methodology, S.L. (Sanguk Lee); formal analysis, S.L. (Sanguk Lee); investigation, S.L. (Sanguk Lee), J.J., B.K., H.H. and S.A.; writing—original draft preparation, S.L. (Sanguk Lee); writing—review and editing, J.J., S.L. (Seunghwan Lee), J.L. (Junjoung Lee) and J.L. (Jaewan Lim); supervision, R.B.; project administration, R.B.; funding acquisition, R.B. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the National Research Foundation of Korea (NRF) grant, funded by the Republic of Korea government (MSIT) (no. NRF-2022R1C1C1004925, NRF-2020M3F3A2A02082436); the MOTIE (Ministry of Trade, Industry, and Energy) (no. 20019450, 20020265); the KSRC (the Korea Semiconductor Research Consortium) support program for the development of the future semiconductor devices; and the BK21 FOUR Program.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

The EDA tool was supported by the IC Design Education Center, Republic of Korea.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Ghani, T.; Armstrong, M.; Auth, C.; Bost, M.; Charvat, P.; Glass, G.; Hoffmann, T.; Johnson, K.; Kenyon, C.; Klaus, J.; et al. A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors. In Proceedings of the IEEE International Electron Devices Meeting, Washington, DC, USA, 8–10 December 2003; pp. 11.6.1–11.6.3. [Google Scholar]
  2. Mistry, K.; Chau, R.; Choi, C.-H.; Ding, G.; Fischer, K.; Ghani, T.; Grover, R.; Han, W.; Hanken, D.; Hattendorf, M.; et al. A 45 nm Logic Technology with High-K+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193 nm Dry Patterning, and 100% Pb-Free Packaging. In Proceedings of the 2007 IEEE International Electron Devices Meeting, San Francisco, CA, USA, 10–12 December 2007; pp. 247–250. [Google Scholar]
  3. Cheng, K.; Khakifirooz, A.; Kulkarni, P.; Ponoth, S.; Kuss, J.; Shahrjerdi, D.; Edge, L.F.; Kimball, A.; Kanakasabapathy, S.; Xiu, K.; et al. Extremely Thin SOI (ETSOI) CMOS with Record Low Variability for Low Power System-on-Chip Applications. In Proceedings of the Technical Digest—International Electron Devices Meeting (IEDM), Baltimore, MD, USA, 7–9 December 2009; pp. 49–52. [Google Scholar]
  4. Auth, C.; Allen, C.; Blattner, A.; Bergstrom, D.; Brazier, M.; Bost, M.; Buehler, M.; Chikarmane, V.; Ghani, T.; Glassman, T.; et al. A 22 nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors. In Proceedings of the 2012 Symposium on VLSI Technology (VLSIT), Honolulu, HI, USA, 12–14 June 2012; Volume 980, pp. 131–132. [Google Scholar]
  5. Lin, C.; Greene, B.; Narasimha, S.; Cai, J.; Bryant, A.; Radens, C.; Narayanan, V.; Linder, B.; Ho, H.; Aiyar, A.; et al. High Performance 14 nm SOI FinFET CMOS Technology with 0.0174 μm2 Embedded DRAM and 15 Levels of Cu Metallization. In Proceedings of the International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 15–17 December 2014; pp. 74–76. [Google Scholar]
  6. Xie, R.; Montanini, P.; Akarvardar, K.; Tripathi, N.; Haran, B.; Johnson, S.; Hook, T.; Hamieh, B.; Corliss, D.; Wang, J.; et al. A 7 nm FinFET Technology Featuring EUV Patterning and Dual Strained High Mobility Channels. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016; Volume 12, pp. 47–50. [Google Scholar]
  7. Bae, G.; Bae, D.; Kang, M.; Hwang, S.M.; Kim, S.S.; Seo, B.; Kwon, T.Y.; Lee, T.J.; Moon, C.; Choi, Y.M.; et al. 3nm GAA Technology Featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications. In Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 1–5 December 2018; pp. 28.7.1–28.7.4. [Google Scholar] [CrossRef]
  8. He, X.; Fronheiser, J.; Zhao, P.; Hu, Z.; Uppal, S.; Wu, X.; Hu, Y.; Sporer, R.; Qin, L.; Krishnan, R.; et al. Impact of Aggressive Fin Width Scaling on FinFET Device Characteristics. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017; pp. 20.2.1–20.2.4. [Google Scholar]
  9. Maszara, W.P.; Lin, M. FinFETs-Technology and Circuit Design Challenges. In Proceedings of the 2013 Proceedings of the ESSCIRC (ESSCIRC), Bucharest, Romania, 16–20 September 2013; pp. 3–8.
  10. Loubet, N.; Hook, T.; Montanini, P.; Yeung, C.-W.; Kanakasabapathy, S.; Guillom, M.; Yamashita, T.; Zhang, J.; Miao, X.; Wang, J.; et al. Stacked Nanosheet Gate-All-around Transistor to Enable Scaling beyond FinFET. In Proceedings of the 2017 Symposium on VLSI Technology, Kyoto, Japan, 5–8 June 2017; Volume 5, p. T230. [Google Scholar]
  11. Harsha Vardhan, P.; Amita; Ganguly, S.; Ganguly, U. Threshold Voltage Variability in Nanosheet GAA Transistors. IEEE Trans. Electron Devices 2019, 66, 4433–4438. [Google Scholar] [CrossRef]
  12. Barraud, S.; Lapras, V.; Previtali, B.; Samson, M.P.; Lacord, J.; Martinie, S.; Jaud, M.; Athanasiou, S.; Triozon, F. Performance and Design Considerations for gate-all-around stacked-NanoWires FETs. In Proceedings of the 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2–6 December 2017; pp. 1–4. [Google Scholar]
  13. Shi, J.; Nayak, D.; Ichihashi, M.; Banna, S.; Moritz, C.A. On the Design of Ultra-High Density 14 nm Finfet Based Transistor-Level Monolithic 3d Ics. In Proceedings of the 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, PA, USA, 11–13 July 2016; pp. 449–454. [Google Scholar] [CrossRef]
  14. Davis, W.R.; Wilson, J.; Mick, S.; Jian, X.; Hao, H.; Mineo, C.; Sule, A.M.; Steer, M.; Franzon, P.D. Demystifying 3D ICs: The Pros and Cons of Going Vertical. IEEE Des. Test Comput. 2005, 22, 498–510. [Google Scholar] [CrossRef]
  15. Vandooren, A.; Witters, L.; Franco, J.; Mallik, A.; Parvais, B.; Wu, Z.; Li, W.; Rosseel, E.; Hikkavyy, A.; Peng, L.; et al. Key Challenges and Opportunities for 3D Sequential Integration. In Proceedings of the 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 15–18 October 2018; pp. 2–5. [Google Scholar]
  16. Fenouillet-Beranger, C.; Previtali, B.; Batude, P.; Nemouchi, F.; Cassé, M.; Garros, X.; Tosti, L.; Rambal, N.; Lafond, D.; Dansas, H.; et al. FDSOI Bottom MOSFETs Stability versus Top Transistor Thermal Budget Featuring 3D Monolithic Integration. Solid. State. Electron. 2015, 113, 2–8. [Google Scholar] [CrossRef]
  17. Yang, C.; Shieh, J.; Hsieh, T.; Huang, W.; Wang, H.; Wu, T.; Hou, Y.; Chen, Y.; Lee, Y.; Chen, M.; et al. Enabling Low Power BEOL Compatible Monolithic 3D + Nanoelectronics for IoTs Using Local and Selective Far-Infrared Ray Laser Anneal Technology. In Proceedings of the 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 7–9 December 2015; pp. 205–208. [Google Scholar]
  18. Fenouillet-Beranger, C.; Acosta-Alba, P.; Mathieu, B.; Kerdiles, S.; Samson, M.; Previtali, B.; Rambal, N.; Lapras, V.; Ibars, F.; Roman, A.; et al. Ns Laser Annealing for Junction Activation Preserving Inter-Tier Interconnections Stability within a 3D Sequential Integration. In Proceedings of the 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Burlingame, CA, USA, 10–13 October 2016; pp. 1–2. [Google Scholar]
  19. Henning, A.K.; Rajendran, B.; Cronquist, B.; Or-Bach, Z. Thermal Considerations for Monolithic Integration of Three-Dimensional Integrated Circuits. In Proceedings of the 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), Monterey, CA, USA, 7–10 October 2013; pp. 3–4. [Google Scholar] [CrossRef]
  20. Yoon, J.S.; Rim, T.U.; Kim, J.S.; Kim, K.H.; Baek, C.K.; Jeong, Y.H.A. Statistical Variability Study of Random Dopant Fluctuation on Gate-All-around Inversion- Mode Silicon Nanowire Field-Effect Transistors. Appl. Phys. Lett. 2021, 103507, 6–11. [Google Scholar] [CrossRef] [Green Version]
  21. Hsu, W.; Wen, F.; Wang, X.; Wang, Y.; Dolocan, A.; Roy, A.; Kim, T.; Tutuc, E.; Member, S.; Banerjee, S.K. Laser Spike Annealing for Shallow Junctions in Ge CMOS. IEEE Trans. Electron Devices 2017, 64, 346–352. [Google Scholar] [CrossRef]
  22. Sentaurus, Version O-2019.12-SP1; Synopsys Inc.: Mountain View, CA, USA, 2019.
  23. Ancona, M.G.; Tiersten, H.F. Macroscopic Physics of the Silicon Inversion Layer. Phys. Rev. B 1987, 35, 7959–7965. [Google Scholar] [CrossRef] [PubMed]
  24. Ancona, M.G.; Iafrate, G.J. Quantum Correction to the Equation of State of an Electron Gas in a Semiconductor. Phys. Rev. B 1989, 39, 9536–9540. [Google Scholar] [CrossRef] [PubMed]
  25. Slotboom, J.W.; de Graaff, H.C. Measurements of Bandgap Narrowing in Si Bipolar Transistors. Solid State Electron. 1976, 19, 857–862. [Google Scholar] [CrossRef]
  26. Klaassen, D.B.M.; Slotboom, J.W.; de Graaff, H.C. Unified Apparent Bandgap Narrowing in N- and p-Type Silicon. Solid. State. Electron. 1992, 35, 125–129. [Google Scholar] [CrossRef]
  27. Shur, M.S. Low Ballistic Mobility in Submicron HEMTs. IEEE Electron Device Lett. 2002, 23, 511–513. [Google Scholar] [CrossRef]
  28. Canali, C.; Majni, G.; Minder, R.; Ottaviani, G. Electron and Hole Drift Velocity Measurements in Silicon and Their Empirical Relation to Electric Field and Temperatures. IEEE Trans. Electron Devices 1976, 23, 1113. [Google Scholar] [CrossRef]
  29. Ando, T. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging? Materials 2012, 5, 478–500. [Google Scholar] [CrossRef] [PubMed] [Green Version]
  30. Mujtaba, S.A. Advanced Mobility Models for Design and Simulation of Deep Submicron MOSFETs. Ph.D. Dissertation, Department Electrical Engineering Stanford University, Stanford, CA, USA, 1996. [Google Scholar]
  31. Bardeen, J.; Shockley, W. Deformation Potentials and Mobilities in Non-Polar Crystals. Phys. Rev. 1950, 80, 72–80. [Google Scholar] [CrossRef]
  32. Zhang, J.; Pancharatnam, S.; Adams, C.; Wu, H.; Zhou, H.; Shen, T.; Xie, R.; Sankarapandian, M.; Wang, J.; Watanabe, K.; et al. Full Bottom Dielectric Isolation to Enable Stacked Nanosheet Transistor for Low Power and High Performance Applications. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019; pp. 250–253. [Google Scholar] [CrossRef]
  33. Jeong, J.; Yoon, J.S.; Lee, S.; Baek, R.H. Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-Nm Node SoC Application. IEEE Access 2020, 8, 35873–35881. [Google Scholar] [CrossRef]
  34. Loubet, N.; Kal, S.; Alix, C.; Pancharatnam, S.; Zhou, H.; Durfee, C.; Belyansky, M.; Haller, N.; Watanabe, K.; Devarajan, T. A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices. In Proceedings of the 2019 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 7–11 December 2019; pp. 242–245. [Google Scholar]
  35. Yoon, J.S.; Jeong, J.; Lee, S.; Lee, J.; Lee, S.; Baek, R.H.; Lim, S.K. Performance, Power, and Area of Standard Cells in Sub 3 Nm Node Using Buried Power Rail. IEEE Trans. Electron Devices 2022, 69, 894–899. [Google Scholar] [CrossRef]
  36. Lee, S.; Jeong, J.; Yoon, J.S.; Lee, S.; Lee, J.; Lim, J.; Baek, R.H. Sensitivity of Inner Spacer Thickness Variations for Sub-3-Nm Node Silicon Nanosheet Field-Effect Transistors. Nanomaterials 2022, 12, 3349. [Google Scholar] [CrossRef] [PubMed]
  37. Mochizuki, S.; Colombeau, B.; Yu, L.; Dube, A.; Choi, S.; Stolfi, M.; Bi, Z.; Chang, F.; Conti, R.A.; Liu, P.; et al. Advanced Arsenic Doped Epitaxial Growth for Source Drain Extension Formation in Scaled FinFET Devices. In Proceedings of the 2018 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 1–5 December 2018; pp. 35.2.1–35.2.4. [Google Scholar] [CrossRef]
  38. Zangenberg, N.R.; Fage-Pedersen, J.; Hansen, J.L.; Larsen, A.N. Boron and Phosphorus Diffusion in Strained and Relaxed Si and SiGe. J. Appl. Phys. 2003, 94, 3883–3890. [Google Scholar] [CrossRef]
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Figure 1. (a) Conventional and proposed structures of NSEFTs and their cross-sectional views. (b) The process flow of the S/D extension scheme. The added process step and etched NS region are highlighted in the red text and dashed yellow boxes.
Figure 1. (a) Conventional and proposed structures of NSEFTs and their cross-sectional views. (b) The process flow of the S/D extension scheme. The added process step and etched NS region are highlighted in the red text and dashed yellow boxes.
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Figure 2. (a) Phosphorus and boron profiles along the source-drain direction after annealing. (b) SIMS profile of phosphorus for the calibration of the LSA and RTA processes.
Figure 2. (a) Phosphorus and boron profiles along the source-drain direction after annealing. (b) SIMS profile of phosphorus for the calibration of the LSA and RTA processes.
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Figure 3. Transfer curves of NSFETs according to the TSi_E for (a) NFETs and (b) PFETs.
Figure 3. Transfer curves of NSFETs according to the TSi_E for (a) NFETs and (b) PFETs.
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Figure 4. Ion according to TSi_E for N-/PFETs. The dashed line denotes the Ion of NS-RTA and NS-LSA (TSi_E = 0 nm), and the difference in Ion when using LSA versus RTA is indicated as a red/blue arrow.
Figure 4. Ion according to TSi_E for N-/PFETs. The dashed line denotes the Ion of NS-RTA and NS-LSA (TSi_E = 0 nm), and the difference in Ion when using LSA versus RTA is indicated as a red/blue arrow.
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Figure 5. (a) SS values according to TSi_E for N-/PFETs; the SS values of NS-RTA were indicated as star symbols. (b) Conduction band energy of n-type NS-RTA (black line) and NS-LSA (red line), and the conduction band energy was extracted at the center of the NS channels along the channel length direction.
Figure 5. (a) SS values according to TSi_E for N-/PFETs; the SS values of NS-RTA were indicated as star symbols. (b) Conduction band energy of n-type NS-RTA (black line) and NS-LSA (red line), and the conduction band energy was extracted at the center of the NS channels along the channel length direction.
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Figure 6. (a) Stress profile along the channel length direction (SZZ) in NS-LSA. (b) Stress along the NS channel length direction in NFETs. (c) Averaged |SZZ| value in NS channels below the gate metal.
Figure 6. (a) Stress profile along the channel length direction (SZZ) in NS-LSA. (b) Stress along the NS channel length direction in NFETs. (c) Averaged |SZZ| value in NS channels below the gate metal.
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Figure 7. (a) Electron concentration in the NS channels according to the TSi_E and (b) electron density profile along the channel length direction. Areas with a large difference in carrier concentrations are highlighted with dashed boxes.
Figure 7. (a) Electron concentration in the NS channels according to the TSi_E and (b) electron density profile along the channel length direction. Areas with a large difference in carrier concentrations are highlighted with dashed boxes.
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Figure 8. (a) Gate capacitance and (b) RC delay of NSFETs according to the TSi_E. The dashed line indicates the RC delay of NS-RTA, and the solid symbol indicates the optimum point showing the lowest RC delay.
Figure 8. (a) Gate capacitance and (b) RC delay of NSFETs according to the TSi_E. The dashed line indicates the RC delay of NS-RTA, and the solid symbol indicates the optimum point showing the lowest RC delay.
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Table
Table 1. Fixed and variable geometric parameters for sub-3 nm node NSFETs.
Table 1. Fixed and variable geometric parameters for sub-3 nm node NSFETs.
Fixed ParametersValues
Contact poly pitch (CPP)42 nm
Fin pitch (FP)60 nm
Gate length (Lg)12 nm
Spacing thickness (Tsp)10 nm
NS thickness (Tch)5 nm
Interfacial layer/HfO2 thickness (TIL/THK)0.6 nm/1.1 nm
Inner spacer thickness (TIS)5 nm
S/D doping concentration (NSD)4 × 1020 cm−3
PTS doping concentration (NPTS)5 × 1018 cm−3
Variable ParametersValues
Etch depth of the NS channel (TSi_E)0–4 nm
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Lee, S.; Jeong, J.; Kang, B.; Lee, S.; Lee, J.; Lim, J.; Hwang, H.; Ahn, S.; Baek, R. A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs. Nanomaterials 2023, 13, 868. https://doi.org/10.3390/nano13050868

AMA Style

Lee S, Jeong J, Kang B, Lee S, Lee J, Lim J, Hwang H, Ahn S, Baek R. A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs. Nanomaterials. 2023; 13(5):868. https://doi.org/10.3390/nano13050868

Chicago/Turabian Style

Lee, Sanguk, Jinsu Jeong, Bohyeon Kang, Seunghwan Lee, Junjong Lee, Jaewan Lim, Hyeonjun Hwang, Sungmin Ahn, and Rockhyun Baek. 2023. "A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs" Nanomaterials 13, no. 5: 868. https://doi.org/10.3390/nano13050868

APA Style

Lee, S., Jeong, J., Kang, B., Lee, S., Lee, J., Lim, J., Hwang, H., Ahn, S., & Baek, R. (2023). A Novel Source/Drain Extension Scheme with Laser-Spike Annealing for Nanosheet Field-Effect Transistors in 3D ICs. Nanomaterials, 13(5), 868. https://doi.org/10.3390/nano13050868

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