A Shared DC-Bus Multi-Channel Drive Architecture for Ultrasonic Motors

Abstract

Conventional multi-channel ultrasonic motor (USM) drive systems commonly adopt a one-motor–one-driver architecture, in which each drive channel requires an independent isolated power supply and inverter stage. As the number of motors increases, the system volume and structural complexity grow significantly. To address this issue, this paper proposes a shared DC-bus multi-channel drive architecture for traveling-wave USM. In the proposed scheme, multiple half-bridge power stages are connected in parallel to a common high-voltage DC-bus to achieve centralized energy supply and distributed driving. A DC-side midpoint reference network is introduced to establish an AC voltage reference under a unipolar DC supply, while an independent series matching inductor is employed in each channel to shape the half-bridge output into a quasi-sinusoidal motor-terminal voltage through resonant filtering. Based on the equivalent electrical model of the USM, a unified analytical model is established to analyze the voltage formation mechanism under shared DC-bus conditions. Time-domain simulations and experimental tests are carried out on a two-channel prototype operating at a 150 V DC-bus and a 40 kHz switching frequency. The results demonstrate stable quasi-sinusoidal output voltages, preserved phase consistency, and limited inter-channel coupling during parallel operation. Compared with conventional independent-supply solutions, the proposed architecture achieves an approximately 27% reduction in overall system volume for a three-motor configuration, demonstrating good scalability for compact multi-channel USM drive systems.

1. Introduction

A USM employs piezoelectric ceramics as the driving element and generates mechanical output through high-frequency vibration and frictional coupling [1]. Owing to its compact structure, immunity to electromagnetic interference, high torque at low speed, and high positioning resolution [2], the USM has been widely applied in precision positioning platforms [3], optical focusing devices [4], and micro-manipulation systems. For a traveling-wave USM, stable operation generally requires the application of two-phase alternating voltages with relatively high amplitude and a precise phase relationship in the tens-of-kilohertz frequency range to establish a stable traveling-wave vibration state in the stator. These operating characteristics impose stringent requirements on the drive system in terms of output voltage capability, phase consistency, and frequency stability [5,6,7].

With the development of multi-degree-of-freedom actuators and multi-actuator systems, multi-channel USM drive systems have attracted increasing attention [8,9,10,11]. In practical engineering implementations, a commonly adopted solution is the “one-motor–one-driver” architecture, in which each USM channel is equipped with an independent isolated step-up power supply and a dedicated power inverter stage [12]. Although this configuration provides advantages in electrical isolation and channel independence, the number of isolation transformers and associated magnetic components increases linearly with the number of drive channels [13]. Consequently, the overall system volume, structural complexity, and cost rise significantly, which makes this architecture less suitable for compact and highly integrated multi-motor applications [14].

To meet the driving requirements of piezoelectric ultrasonic loads, extensive research has been conducted in the fields of power ultrasonic supplies and piezoelectric actuator drivers, with particular emphasis on power conversion topologies [15], impedance matching networks [16], and control and tuning strategies [17]. These efforts have led to relatively mature solutions for improving single-channel driving performance [18,19]. However, in application scenarios involving multi-channel USM drive systems, most existing studies still adopt independently powered channels as a basic premise [20]. The influence of centralized power-supply architectures on drive consistency and system stability under multi-channel operation has received comparatively limited attention. In particular, when multiple drive channels share a common DC-bus, potential inter-channel coupling effects and their impact on output voltage characteristics have not yet been sufficiently investigated through system-level analysis and experimental validation.

Motivated by the above considerations, this paper proposes a shared high-voltage DC-bus-based multi-channel USM drive architecture. In the proposed scheme, a unified high-voltage DC-bus serves as a common energy source for multiple drive channels, while several half-bridge power stages are connected in parallel to realize centralized power supply and distributed driving. By introducing a common DC-side midpoint reference network and configuring an independent series matching inductor in each drive channel, the half-bridge output under a unipolar DC supply is able to generate an equivalent bipolar high-frequency excitation at the USM terminals. Meanwhile, the series resonant behavior of the matching network shapes the drive voltage into a quasi-sinusoidal waveform suitable for USM operation. In this manner, multi-channel scalability can be achieved without replicating isolated step-up power modules as the number of channels increases, thereby reducing the number of magnetic components and the overall system volume at the architectural level.

Based on the equivalent electrical model of a traveling-wave USM, a unified analytical model incorporating the half-bridge power stage, midpoint reference network, series matching network, and motor load is established to analyze the voltage formation mechanism under a shared DC-bus configuration. System-level time-domain simulations are carried out to evaluate the driving characteristics under both single-channel operation and multi-channel parallel operation. Furthermore, a dual-channel hardware prototype is developed to experimentally assess the proposed architecture in terms of output waveform consistency, midpoint reference stability, and inter-channel interaction under practical load conditions.

2. System Architecture and Operating Principle

To realize multi-channel USM driving under a shared DC-bus configuration, a centralized power-supply and distributed-driving architecture is developed, and its overall structure is illustrated in Figure 1. The system consists of a control unit, gate-driving circuits with half-bridge power stages, a DC-side midpoint reference network, series matching networks, and USM loads. A shared high-voltage DC-bus is employed to provide a unified energy source for multiple drive channels. Meanwhile, an auxiliary step-down branch derived from the same DC-bus supplies the low-voltage power required by the control unit and the gate-driving circuits.

In the proposed architecture, the control unit operates in the low-voltage control domain and is responsible for generating synchronized high-frequency driving signals for multiple channels, while configuring the phase relationships required for traveling-wave USM operation. After level shifting and dead-time insertion by the gate-driving circuits, the control signals are applied to the half-bridge power stages of each channel. The output node of each half-bridge is connected to the corresponding USM through a series matching inductor. In addition, a local midpoint reference network is configured on the DC side of each channel to provide a return path for high-frequency commutation currents and to establish a stable reference potential in the AC sense. Through the resonant shaping effect between the matching network and the equivalent impedance of the USM, the high-frequency square-wave voltage generated by the half-bridge is transformed into a quasi-sinusoidal excitation at the motor terminals, satisfying the driving requirements of the USM.

2.1. Control Unit and Two-Phase PWM Excitation Generation

In the proposed shared DC-bus-based multi-channel USM drive system, the control unit is responsible for generating the high-frequency PWM control signals required for USM operation and for ensuring synchronous configuration among different drive channels. The control unit operates in the low-voltage control domain, and its functionality is limited to timing generation and phase relationship configuration. It does not participate in energy conversion or modulation of the high-voltage power devices.

In this study, an STM32F103 series microcontroller (STMicroelectronics, Geneva, Switzerland) is selected as the control core. Its hardware timers, driven by an external 72 MHz quartz crystal oscillator, are utilized to generate multi-channel PWM signals through timer-based frequency division, ensuring stable frequency generation and precise phase synchronization among different channels. Since the PWM switching frequency is obtained by dividing a much higher system clock, the relative frequency error and phase deviation introduced by the crystal oscillator are significantly reduced, and the effects of long-term drift and temperature variation can be considered negligible under the operating conditions of this study. To satisfy the requirement of orthogonal electrical excitation for traveling-wave USM operation, each drive channel outputs two PWM signals with identical frequency and a fixed phase difference of 90°, thereby providing the two-phase orthogonal excitation required by the USM [21].

The driving frequency is determined based on the electrical characteristics of the traveling-wave USM within the target operating range. According to the analysis of the USM input impedance as a function of frequency, the motor exhibits a relatively low input impedance around 40 kHz, which is favorable for efficient energy transfer [22]. Operating in this frequency region allows the driving system to achieve higher electromechanical conversion efficiency while avoiding excessive reactive power. Therefore, the switching frequency of all drive channels is uniformly set to 40 kHz. A detailed analysis of the impedance–frequency characteristics of the USM and the corresponding equivalent modeling is presented in Section 2.4.1.

To facilitate subsequent electrical equivalent modeling and analysis of the driving mechanism, a fixed-duty-cycle driving strategy is adopted at the control level. The PWM duty cycle is set to 50%, resulting in symmetric high-frequency square-wave signals generated by the control unit. Figure 2 illustrates the typical timing waveforms of the two-phase PWM control signals. As shown, Phase A and Phase B maintain identical frequency and duty cycle while preserving a constant 90° phase difference, thereby providing high-frequency control inputs with consistent amplitude and well-defined phase relationships for the subsequent power-driving stages.

2.2. Gate-Driving Circuit and Half-Bridge Switching Logic

In the proposed multi-channel USM drive system, the gate-driving circuit is located between the control unit and the half-bridge power stage. Its primary function is to convert the PWM signals generated by the control unit into appropriate gate-driving signals for the power switching devices, while introducing dead time during switching transitions to ensure safe and reliable operation of the half-bridge power stage under high-frequency conditions.

Unlike some drive schemes in which two complementary PWM signals are required to independently control the high-side and low-side switches, the half-bridge gate-driving approach adopted in this study requires only a single PWM input signal. Based on this input, the gate driver generates two complementary gate-driving outputs for the high-side (HO) and low-side (LO) switches. This approach features a simplified structure that is well matched to the half-bridge power-stage topology employed in this work and is capable of meeting the requirements of high-frequency commutation and drive consistency for USM applications.

Figure 3 illustrates the timing relationship of the gate-driving signals. When the input PWM signal is at a high logic level, the HO output is driven high while the LO output remains low. Conversely, when the input PWM signal is at a low logic level, the LO output is driven high and the HO output remains low, thereby establishing a strictly complementary driving relationship between HO and LO. This complementary logic ensures that only one power switching device is in the on-state at any given time, satisfying the fundamental operating requirements of the half-bridge power stage.

To prevent shoot-through during switching transitions, a dead time is inherently introduced by the employed gate driver (IR2104. Infineon Technologies, Munich, Germany). The dead time is internally generated by the driver and is approximately 520 ns according to the device specifications. As indicated by the dashed regions in Figure 3, both HO and LO remain in the off-state during the dead-time interval. This interval provides sufficient transition time for device turn-off and enhances the reliability of the half-bridge power stage during high-frequency operation.

2.3. Half-Bridge Power Stage and Midpoint Reference Network

As shown in Figure 4, each driving phase in the proposed system employs a half-bridge power stage composed of upper and lower power switching devices, with the DC side connected in parallel to a shared high-voltage DC-bus $V_{\mathrm{d}\mathrm{c}}$. In this work, N-channel power MOSFETs (IRF830. MINOS TECHNOLOGY LIMITED, Hong Kong, China) are used as the switching devices for both the upper and lower switches of the half-bridge. The output node of each half-bridge is connected to the USM load through a series matching inductor. The two-phase power channels are identical in both topology and parameter configuration, and are driven by control signals with a fixed phase difference of 90°, thereby satisfying the orthogonal excitation requirement of a traveling-wave USM.

Under the shared unipolar DC supply condition, a midpoint reference network is introduced on the DC side to establish a stable reference potential in the AC sense. As illustrated in Figure 4, this network consists of symmetrical divider resistors $R_1$ and $R_2$, together with parallel capacitors $C_1$ and $C_2$. The resistors define the DC reference level of the midpoint, while the capacitors stabilize the midpoint reference potential under high-frequency operation. With the aid of this midpoint reference network, the half-bridge output voltage can be uniformly expressed with respect to the midpoint reference, thereby providing a clear voltage baseline for subsequent equivalent analysis.

The values of the midpoint divider resistors and stabilizing capacitors are selected based on stability and impedance considerations. The divider resistors $R_1$ and $R_2$ are set to 10 kΩ to establish a stable midpoint voltage while maintaining low static power dissipation. The stabilizing capacitors $C_1$ and $C_2$ are chosen such that their capacitive reactance

$$X_C={\displaystyle \frac{1}{2\pi fC}},$$

(1)

is much smaller than the equivalent load impedance seen from the midpoint at the operating frequency, thereby ensuring effective suppression of high-frequency voltage fluctuations. Based on this criterion, a capacitance value of 1 µF is adopted.

Under ideal switching conditions, where device conduction voltage drops and dead-time effects are neglected, the operating states of the half-bridge can be described as follows. When the upper switch is turned on and the lower switch is turned off, the output node is clamped to the positive rail of the DC-bus. Conversely, when the lower switch is turned on and the upper switch is turned off, the output node is switched to the negative rail of the DC-bus. Taking the midpoint reference $v_{\mathrm{m}}\approx V_{\mathrm{d}\mathrm{c}}/2$ as the voltage baseline, the half-bridge output voltage can be represented as a symmetrical square wave with an amplitude of $\pm V_{\mathrm{d}\mathrm{c}}/2$, whose time-domain expression is given by

$$v_o(t)=\left\{\begin{array}{c}+{\displaystyle \frac{V_{\mathrm{d}\mathrm{c}}}{2}},\hspace{1em}0\le t<{\displaystyle \frac{T}{2}}\hfill \\ -{\displaystyle \frac{V_{\mathrm{d}\mathrm{c}}}{2}},\hspace{1em}{\displaystyle \frac{T}{2}}\le t<T\hfill \end{array}\right.,\hspace{1em}{v}_o(t+T)=v_o(t),$$

(2)

where T denotes the switching period. It should be noted that the above analysis is based on an ideal switching assumption, in which the voltage drops of the power devices, dead-time effects, and parasitic elements are neglected for simplicity. In practical implementations, these non-ideal factors mainly introduce small deviations in the output voltage amplitude and waveform shape. However, since the operating frequency is fixed and the analysis in this study focuses on the fundamental voltage formation mechanism and comparative behavior under single- and multi-channel operation, the influence of these non-ideal effects does not affect the validity of the proposed model or the conclusions drawn. This is further verified by the experimental results presented in Section 4.

Because the series matching network and the USM exhibit pronounced frequency-selective characteristics around the operating frequency, the response at the load side to the half-bridge square-wave excitation is dominated by its fundamental component. By performing a Fourier expansion of (2), the amplitude of the fundamental component can be expressed as

$$V_1={\displaystyle \frac{4}{\pi }}·{\displaystyle \frac{V_{dc}}{2}}={\displaystyle \frac{2}{\pi }}{V}_{dc}.$$

(3)

Therefore, in the vicinity of the operating frequency, the half-bridge power stage can be equivalently represented as an AC voltage source with an amplitude of $V_1$. Together with the subsequent series matching inductor and the equivalent input impedance of the USM, a unified analytical model is established. Based on this equivalent representation, the next subsection further analyzes the quasi-sinusoidal shaping mechanism of the driving voltage introduced by the series matching network.

2.4. USM Equivalent Model and Matching Parameter Selection

2.4.1. Selection of Equivalent Parameters of the USM

To reasonably describe the electrical behavior of the USM under the shared DC-bus drive architecture in system-level analysis, and to provide a unified modeling basis for subsequent matching network parameter selection and simulation analysis, it is necessary to establish an equivalent representation of the input electrical characteristics of the traveling-wave USM within the target operating frequency range. In conjunction with the control strategy and driving method described in Section 2.1, the equivalent electrical parameters of the USM are determined under two-phase orthogonal high-frequency excitation conditions.

In the drive system, the operating frequency of each channel is uniformly set to 40 kHz by the control unit. To characterize the electrical behavior of the USM in this target frequency range, a frequency sweep test is performed on the selected USM, and the variation in its input impedance magnitude with driving frequency is measured. Figure 5 presents the measured impedance magnitude of the USM as a function of frequency. It can be observed that the input impedance reaches a relatively low level in the vicinity of 40 kHz, indicating favorable energy acceptance characteristics under high-frequency electrical excitation. This observation is consistent with the driving frequency selection described in Section 2.1.

Based on the above frequency characteristics and the design premise that the drive system operates at a fixed frequency of 40 kHz under steady-state conditions, the USM is approximated by a parallel R–C equivalent model at the target operating frequency, as shown in Figure 6. In this model, the equivalent capacitance represents the dominant capacitive behavior of the USM around the operating frequency, while the equivalent resistance accounts for energy loss. According to the impedance characteristics near 40 kHz observed in Figure 5, the equivalent parameters of the USM are selected as follows:

$$C_{eq}=6\mathrm{n}\mathrm{F},R_{eq}=2\mathrm{k}\mathsf{\Omega }.$$

(4)

This parameter set effectively captures the main impedance features and loss characteristics of the USM under steady-state excitation at 40 kHz and is employed in the subsequent system-level simulations.

It should be noted that the equivalent parameters of an USM generally vary with the driving frequency, and a complete frequency-domain characterization can be obtained through more sophisticated parameter identification methods. However, since the focus of this study is on the shared DC-bus drive architecture and its multi-channel operating characteristics rather than on detailed frequency-domain modeling of the motor itself, the specific procedures for frequency sweeping and parameter extraction are not discussed in detail. Instead, a set of equivalent parameters corresponding to the operating frequency of 40 kHz is adopted for system-level analysis. This modeling approach is commonly used in engineering-oriented studies of USM drive systems and is sufficient for capturing the dominant electrical behavior under steady-state excitation conditions [1].

2.4.2. Selection Principle of the Series Matching Inductor

The purpose of introducing a series matching inductor between the half-bridge power stage and the USM is to establish a near-resonant operating condition in the vicinity of the selected operating frequency. This enhances the effective transfer of the fundamental component of the half-bridge square-wave output to the motor terminals, while suppressing the influence of high-frequency harmonic components on the terminal voltage waveform.

Neglecting higher-order loss factors, the matching inductor $L_{\mathrm{m}}$ and the equivalent motor capacitance $C_{\mathrm{e}\mathrm{q}}$ form a series resonant circuit, whose resonant frequency can be expressed as

$$f_0={\displaystyle \frac{1}{2\pi \sqrt{L_m{C}_{eq}}}}.$$

(5)

To obtain a low equivalent impedance around the operating frequency, the matching inductor is selected such that the resonant frequency $f_0$ is close to the driving frequency. Based on the equivalent capacitance adopted in this study, the nominal value of the matching inductor is determined to be 2.7 mH under the operating frequency of 40 kHz. This parameter is kept unchanged in the subsequent simulations and experiments to validate the waveform consistency and stability of the proposed drive architecture under both single-channel and multi-channel operating conditions.

3. Simulation Validation and Analysis

To validate the feasibility and electrical characteristics of the proposed shared DC-bus multi-channel USM drive architecture, time-domain simulations were performed using the Multisim [14.0] software platform (National Instruments, Austin, TX, USA), based on the equivalent circuit models established in Section 2. The simulations focus on the output behavior of the half-bridge power stage, the role of the DC-side midpoint reference network, and the waveform shaping effect of the series matching network. In addition, the output consistency under multi-channel operation is evaluated.

The simulations were carried out in the transient analysis mode of Multisim, which allows accurate time-domain observation of voltage and current waveforms in power electronic circuits. The simulation model and parameter settings strictly follow the analytical framework described in Section 2. To ensure comparability among the simulation results, all parameters adopted in the simulations are kept identical. Their specific values are summarized in

Table 1. Key parameters of the proposed USM drive system.

Parameter	Symbol	Value
Equivalent capacitance of USM	$C_{\mathrm{e}\mathrm{q}}$	6 nF
Equivalent resistance of USM	$R_{\mathrm{e}\mathrm{q}}$	2 kΩ
DC-bus voltage	$V_{\mathrm{d}\mathrm{c}}$	150 V
Driving frequency	$f_0$	40 kHz
PWM duty cycle	D	50%
Midpoint divider resistors	$R_1,R_2$	10 kΩ
Midpoint stabilizing capacitors	$C_1,C_2$	1 μF
Series matching inductor	$L_m$	2.7 mH

.

3.1. Single-Channel Simulation Results and Analysis

To verify the fundamental electrical characteristics of the proposed shared DC-bus drive architecture under single-channel operation, time-domain simulations are performed for an individual drive channel. The simulation model is consistent with the analytical framework established in Section 2, and the parameter values adopted in the simulations are listed in Table 1.

Figure 7 illustrates the voltage measurement configuration of the proposed drive architecture under single-channel operation. As shown in Figure 7, the output voltage $V_0\left(t\right)$ is measured between the half-bridge output and the DC-side midpoint reference formed by the midpoint network connected to the shared DC-bus. Based on the measurement configuration shown in Figure 7, the simulated output voltage waveform of the half-bridge power stage is presented in Figure 8. Under single-channel operation, owing to the action of the midpoint reference network, the half-bridge output exhibits a symmetric bipolar square-wave characteristic with an amplitude of approximately $\pm V_{\mathrm{d}\mathrm{c}}/2$. This result confirms that, under a unipolar DC-bus supply, an equivalent bipolar excitation can be established at the half-bridge output through the midpoint reference network, thereby providing a suitable voltage source for subsequent waveform shaping.

Figure 9 presents the simulated motor terminal voltages of the A/B phases of the USM under single-channel operation. The two-phase voltages exhibit identical amplitudes and maintain a phase difference of 90°. After passing through the series matching network, the motor terminal voltages show stable quasi-sinusoidal waveforms. Compared with the square-wave output of the half-bridge power stage, the high-frequency harmonic components at the motor terminals are effectively suppressed, indicating that the combined effect of the series matching inductor and the equivalent motor capacitance provides significant waveform shaping around the operating frequency. Based on the steady-state simulation results, the peak-to-peak value of the motor terminal voltage is approximately $V_{\mathrm{p}\mathrm{p}}\approx 288\mathrm{V}$.

The above single-channel simulation results demonstrate that, under the parameter conditions listed in Table 1, the proposed shared DC-bus drive architecture can generate a motor terminal voltage with well-defined amplitude and concentrated spectral content in single-channel operation. This operating condition is therefore used as the reference case for the analysis of output consistency under multi-channel parallel operation in the subsequent subsection.

3.2. Multi-Channel Parallel Simulation Results

Building on the single-channel simulations, this subsection evaluates the output consistency of the proposed shared DC-bus multi-channel drive architecture under parallel multi-channel operation. The simulation model consists of multiple identical drive channels connected in parallel, sharing the same DC-bus and midpoint reference network, while all other parameters remain the same as those listed in Table 1.

It should be noted that the simulations in this section are performed using an idealized circuit model, in which all channels are configured with identical electrical parameters. This assumption is adopted to focus on the fundamental operating characteristics of the proposed shared DC-bus architecture and to facilitate a clear evaluation of its intrinsic consistency. In practical implementations, slight parameter mismatches among different channels may exist due to component tolerances, wiring parasitics, or load variations. The influence of such non-ideal factors, including their impact on inter-channel coupling and output consistency, is further investigated and discussed in Section 3.3 through additional simulation analysis.

Figure 10 shows the simulated four-phase motor terminal voltages for a two-motor parallel configuration, where the four traces correspond to the A/B phases of the two motors. The waveforms exhibit identical amplitudes and stable phase relationships, and the multi-channel results remain consistent with the single-channel case.

3.3. Multi-Channel Robustness Analysis Under Parameter Variations

To further evaluate the robustness of the proposed shared DC-bus multi-channel drive architecture, additional simulations were carried out by introducing parameter variations among different drive channels. In practical implementations, slight deviations in equivalent impedance and matching components are unavoidable due to component tolerances and operating condition differences.

In this study, the nominal case corresponds to identical channel parameters, under which all drive channels exhibit the same output voltage amplitude of approximately 288 V. To emulate parameter mismatch, the equivalent parameters of individual channels were slightly perturbed while keeping the control strategy and DC-bus voltage unchanged. The resulting output voltage amplitudes of different channels are shown in Figure 11.

As illustrated in Figure 11, when parameter variations are introduced, the output voltage amplitudes of individual channels decrease slightly to the range of 270–280 V. This behavior is mainly caused by the deviation from the optimal resonance condition of the series matching network, which reduces the voltage amplification capability. Nevertheless, the output waveforms of all channels remain sinusoidal, and no waveform distortion or instability is observed. Only the voltage amplitude is affected, while the waveform shape and phase relationship are well preserved.

In addition, no noticeable inter-channel coupling effect is observed under parameter mismatch conditions, indicating that the shared DC-bus architecture effectively suppresses cross-channel interference through the inherent impedance isolation of the power stage and midpoint reference network.

These results indicate that the proposed shared DC-bus architecture exhibits good robustness against parameter mismatches. Even under non-ideal conditions, the system maintains stable operation and consistent waveform characteristics, demonstrating its suitability for practical multi-channel USM drive applications.

4. Experimental Validation and Analysis

To validate the simulation results presented in Section 3 and to demonstrate the practical feasibility of the proposed shared DC-bus multi-channel USM drive architecture, an experimental platform is established in this section, and key electrical characteristics of the system are experimentally evaluated under different operating conditions. The experiments focus on the formation mechanism of the driving waveform, the stability of the midpoint reference network, and the operating behavior under a shared DC-bus configuration. The experimental parameters are kept consistent with those used in the simulations to enable a meaningful comparison.

4.1. Experimental Setup and Test Method

The experimental testing platform is shown in Figure 12. Figure 12a presents the block diagram of the experimental connection configuration, illustrating the relationship among the power supply, drive circuit, control unit, and ultrasonic motor, while Figure 12b shows the corresponding experimental testing platform. The platform is constructed in a modular manner, where the functional circuits are implemented using a perforated prototyping board and external wiring. The experimental system mainly consists of a high-voltage DC power supply, drive circuit modules, and a USM load. This experimental platform is intended for principle verification and feasibility evaluation rather than for a highly integrated engineering prototype. The DC-bus voltage, driving frequency, and matching network parameters adopted in the experiments are kept consistent with those used in the simulations presented in Section 3, thereby ensuring direct comparability between the experimental results and the simulation analysis.

Experimental tests are conducted under different operating conditions, including baseline tests under single-channel operation and comparative tests under multi-channel operation with a shared DC-bus configuration. By measuring the half-bridge output voltage and the motor terminal voltage waveforms, the practical formation of the driving waveforms under different operating conditions is observed and analyzed. Voltage measurements are performed using high-bandwidth differential voltage probes, while the oscilloscope is configured with a bandwidth of 60 MHz and a sampling rate of 1 GS/s. Compared with the driving frequency of approximately 40 kHz, the measurement system provides sufficient bandwidth and temporal resolution to accurately capture voltage amplitude variations and high-frequency transient features, thereby satisfying the experimental measurement requirements.

4.2. Single-Channel Experimental Results and Analysis

To verify the driving effectiveness and operational stability of the proposed shared DC-bus USM drive architecture under practical conditions, experimental tests are conducted under single-channel operation. Key voltage waveforms of the power stage as well as the operating behavior of the USM are experimentally evaluated. The experimental platform and test conditions are identical to those described in Section 4.1, and the USM operates under no additional mechanical load.

Figure 13 shows the measured half-bridge output voltage with respect to the DC-side midpoint reference under single-channel operation. It can be observed that the half-bridge output voltage switches stably around $\pm V_{\mathrm{d}\mathrm{c}}/2$. The magnitudes of the positive and negative voltage levels are slightly lower than the ideal reference values, with a deviation of approximately 2–3%. This deviation is mainly attributed to the conduction voltage drops of the power devices, dead-time effects, and parasitic parameters in the circuit, which are common non-ideal characteristics in practical power electronic systems. During voltage commutation, a certain degree of high-frequency ringing can be observed. However, within the steady-state plateau intervals, the voltage remains stable without noticeable DC offset or midpoint voltage drift, indicating that the adopted midpoint reference network provides a reliable and stable reference potential under single-channel operation.

After the half-bridge output is processed by the series matching network, the two-phase motor terminal voltages are obtained, as shown in Figure 14. Compared with the two-level square-wave output of the half-bridge stage, the motor terminal voltages exhibit a pronounced quasi-sinusoidal shape, and the high-frequency switching harmonics are effectively suppressed. Measurements over multiple consecutive cycles in the steady-state interval indicate that the peak-to-peak value of the single-phase motor terminal voltage is approximately 260–275 V, while the amplitude mismatch between the two phases is maintained within 5%. Compared with the theoretical peak-to-peak voltage obtained from the simulation results in Section 3, the experimental voltage amplitude is reduced by approximately 5–10%. This discrepancy mainly results from deviations in the equivalent parameters of the practical USM, losses in the matching network, and non-ideal characteristics of the power devices, but it does not alter the overall waveform shape or stability of the motor terminal voltages.

Further analysis of the temporal characteristics of the two-phase motor terminal voltages within one electrical period shows that the phase difference between the two driving voltages remains close to 90°. Based on the time intervals between corresponding characteristic points (such as zero-crossings or peak values), the phase error is estimated to be within ±2°, and no noticeable drift is observed over multiple consecutive operating cycles. This result indicates that, under single-channel operation, the drive system can provide the orthogonal excitation conditions required for traveling-wave USM operation.

Regarding the mechanical operating behavior, the startup and steady-state operation of the USM are experimentally observed under single-channel driving conditions. After the driving signals are established, the USM quickly enters a stable operating state and maintains continuous and smooth operation during sustained running. No abnormal stalling, intermittent instability, or significant interruptions are observed. Combined with the measured motor terminal voltage waveforms, it can be confirmed that, under orthogonal excitation with well-defined amplitude and stable phase provided by the drive system, the USM maintains a stable traveling-wave operating state.

In summary, the single-channel experimental results validate the proposed shared DC-bus drive architecture from both electrical output characteristics and mechanical operational stability. The results demonstrate that, under single-channel operation, the proposed drive structure can generate quasi-sinusoidal excitation voltages with well-defined amplitude and stable phase, ensuring stable USM operation. This operating condition therefore serves as the reference case for the subsequent experimental analysis of multi-channel parallel operation.

4.3. Multi-Channel Experimental Results and Analysis

Building on the validation of single-channel operating characteristics, two-channel parallel operation experiments are conducted in this subsection to further evaluate the engineering feasibility of the proposed shared DC-bus multi-channel USM drive architecture under parallel operating conditions. During the experiments, two drive channels are enabled simultaneously, sharing the same DC-bus and midpoint reference network, while all other experimental conditions remain identical to those described in Section 4.2.

Figure 15 shows the measured half-bridge output voltage with respect to the DC-side midpoint reference under two-channel parallel operation. Compared with the midpoint voltage waveform obtained under single-channel operation, the midpoint reference potential exhibits slightly increased dynamic fluctuations during commutation intervals and steady-state plateau regions when two channels operate in parallel. This phenomenon mainly arises from transient current coupling effects introduced through the shared DC-bus and the midpoint reference network during simultaneous switching of multiple channels. Despite the presence of such dynamic disturbances, the midpoint reference voltage remains distributed around $\pm V_{\mathrm{d}\mathrm{c}}/2$ without noticeable DC offset or sustained drift, indicating that the midpoint reference network maintains basic stability under parallel multi-channel operation.

Based on the above midpoint reference stability, the motor terminal driving performance under multi-channel parallel operation is further examined. Figure 16 presents the experimentally measured two-phase motor terminal voltages of each channel under two-channel parallel operation. Both Channel 1 and Channel 2 generate two-phase driving voltages with an approximate phase difference of 90°, thereby forming a four-phase drive configuration. It can be observed that, when both channels operate simultaneously, the motor terminal voltage waveforms of each channel remain continuous and stable, without evident output interruption or severe waveform distortion.

In terms of amplitude characteristics, comparison of multiple steady-state cycles indicates that the peak-to-peak motor terminal voltage under two-channel parallel operation is slightly reduced compared with that obtained under single-channel operation. Based on the measured waveforms, the amplitude reduction is estimated to be approximately 8–10%. Meanwhile, under two-channel operation, the amplitude mismatch between the two phases within each channel is maintained within 8%, indicating that, although a certain degree of energy coupling exists under the shared DC-bus configuration, the output voltage amplitudes of different channels still exhibit good consistency.

Regarding phase characteristics, the phase difference between the two driving voltages within each channel remains close to 90° during two-channel parallel operation. Based on the time intervals between characteristic points within one electrical period, the phase error is estimated to be within ±3°, and no noticeable phase drift or inter-channel mismatch is observed over multiple consecutive operating cycles. This result indicates that the shared DC-bus architecture does not introduce a significant impact on phase consistency.

Further inspection of the motor terminal voltage waveform details reveals that, compared with single-channel operation, the high-frequency disturbances in the motor terminal voltages increase slightly under two-channel parallel operation. Based on the steady-state waveform amplitude variations, the disturbance magnitude is estimated to be approximately 5–7% of the fundamental component. Although a certain increase in high-frequency disturbance is observed, its magnitude remains significantly lower than that of the fundamental component and does not compromise the overall quasi-sinusoidal waveform shape.

In summary, the two-channel parallel experimental results first verify the dynamic stability of the midpoint reference network under shared DC-bus conditions through the measured midpoint voltage waveforms. Combined with the motor terminal driving voltage results, it is further demonstrated that the observed midpoint disturbances do not lead to a substantial degradation in driving performance. The experimental results validate the proposed shared DC-bus multi-channel USM drive architecture from both midpoint reference stability and motor terminal driving effectiveness, indicating good practical feasibility for multi-channel expansion scenarios.

5. Discussion

The proposed shared DC-bus multi-channel USM drive architecture provides structural advantages primarily at the system integration level. Compared with the conventional “one-motor–one-driver” approach, the major difference is that the proposed scheme supplies multiple drive channels from a centralized high-voltage DC-bus, thereby avoiding the repeated configuration of high-voltage power modules and associated magnetic components as the channel count increases. This architectural feature directly targets the main bottleneck of conventional multi-channel USM drive systems, namely the linear growth in hardware redundancy and volume with increasing motor count.

A qualitative comparison between the conventional scheme and the proposed architecture is summarized in

Table 2. Qualitative comparison between the conventional multi-drive scheme and the proposed shared DC-bus architecture.

Comparison Metric	Conventional Scheme	Proposed Scheme
Number of high-voltage modules	Large	Reduced
Magnetic component density	High	Low
System structural complexity	High	Moderate
Hardware redundancy	High	Low
Multi-channel scalability	Limited	Good
System integration level	Low	High
System robustness	High	Moderate
Overall volume impact	Large	Small

. In conventional implementations, each channel is typically powered independently, which requires dedicated high-voltage modules and increases magnetic component usage, leading to higher structural complexity and a lower integration level [23]. In contrast, the proposed shared DC-bus architecture reduces the number of high-voltage modules and magnetic components at the system level while maintaining a parallel, modular output stage. As a result, the overall structure becomes more scalable: adding channels mainly increases only the output-stage duplication rather than the entire high-voltage power conversion chain. This is the key reason why the proposed architecture exhibits advantages in component count, system integration, and scalability, as reflected in Table 2.

Beyond qualitative comparison, the volume benefit can be estimated at the engineering implementation level. For a representative three-motor system with the same power rating and comparable driving requirements, eliminating redundant high-voltage power modules and reducing duplicated magnetic components leads to an approximate 27% reduction in overall drive system volume. This estimate highlights that the proposed architecture offers not only waveform feasibility but also tangible compactness advantages when scaling to multiple actuators. Notably, this reduction is achieved by architectural simplification rather than by aggressive component-level optimization, which makes the result meaningful for practical integration-oriented designs.

In addition to volume reduction, the proposed architecture also shows potential for cost reduction at the system level. This benefit mainly originates from the decreased number of high-voltage power modules, magnetic components, and associated auxiliary circuits, which directly lowers the bill of materials and simplifies system assembly. Although the exact cost reduction depends on component selection and production scale, the reduced hardware redundancy inherent in the shared DC-bus structure provides a clear basis for lowering overall system cost in multi-channel implementations.

It should be noted that this work focuses on validating feasibility and channel consistency rather than on efficiency-oriented optimization. Practical factors such as component losses and thermal behavior may influence efficiency and long-term reliability, but they do not change the fundamental scalability advantage derived from the reduced hardware redundancy. Future studies will therefore extend the present work toward loss modeling, thermal evaluation, and closed-loop coordination to further strengthen the applicability of the proposed architecture in compact multi-degree-of-freedom USM systems.

6. Conclusions

This paper proposed a shared DC-bus multi-channel USM drive architecture to address the problems of large system volume, high structural complexity, and limited scalability in conventional multi-drive systems. By adopting a centralized high-voltage DC power supply and parallel output channels, the proposed architecture avoids the repeated configuration of power conversion units and improves system integration.

The main contributions of this work can be summarized as follows:

• A shared high-voltage DC-bus-based multi-channel USM drive architecture is proposed, which enables independent multi-channel operation under a unified power supply framework and effectively reduces hardware redundancy as the number of drive channels increases;
• Under a unipolar DC supply, a midpoint reference network and series matching inductors are introduced to realize equivalent bipolar excitation at the USM terminals, and a unified electrical model is established to analyze the voltage formation mechanism of the proposed drive system;
• The operating characteristics of the proposed architecture are validated through both simulation and experimental results under single-channel and multi-channel operating conditions. The results demonstrate stable quasi-sinusoidal output waveforms and good channel consistency, confirming the feasibility and effectiveness of the proposed architecture for compact multi-actuator USM drive systems.

Overall, the proposed shared DC-bus architecture provides a practical and scalable solution for multi-channel USM drive applications. Future work will focus on detailed loss modeling, efficiency optimization, thermal behavior analysis, and the extension of the proposed architecture to larger-scale multi-channel systems with closed-loop control.