Nonvolatile Organic Floating-Gate Memory Using N2200 as Charge-Trapping Layer

Abstract

In this work, floating-gate organic field-effect transistor memory using the n-type semiconductor poly-{[N,N′-bis(2-octyldodecyl) naphthalene-1,4,5,8-bis (dicarbo- ximide)-2,6-dili]-alt-5,5′-(2,2′-bithiophene)} (N2200) as a charge-trapping layer is presented. With the assistance of a technology computer-aided design (TCAD) tool (Silvaco-Atlas), the storage characteristics of the device are numerically simulated by using the carrier injection and Fower–Nordheim (FN) tunneling models. The shift in the transfer characteristic curves and the charge-trapping mechanism after programming/erasing (P/E) operations under different P/E voltages and different pulse operation times are discussed. The impacts of different thicknesses of the tunneling layer on storage characteristics are also analyzed. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V under the P/E voltage of ±45 V, 5 s. After 1000 cycle tests, the memory shows good fatigue resistance, and the read current on/off ratio reaches 10³.

1. Introduction

Nonvolatile organic field-effect transistor memories (OFETMs) have attracted considerable attention due to their advantages, including low cost, large area, easy processing, light weight, and good compatibility with flexible substrates, so they have extensive prospects of applications ranging from sensors and flexible displays to wearable electronic devices [1,2,3,4]. With the advent of the post-Moore era, conventional silicon flash memory technologies are facing the quantum limit of the so-called Moore’s law, which states that the charges stored in floating-gate structures are susceptible to leakage in the 10 nm range. Emerging memory technologies are reshaping the data storage space by moving beyond traditional transistor-based architectures. For example, resistive memory (ReRAM) [5] utilizes changes in material resistance to achieve high density, low power, and fast storage. Phase-change memory (PCM) [6] utilizes transitions between amorphous and crystalline states to provide scalability and endurance. Magnetic memories (MRAM and STT-MRAM) [7] rely on magneto-resistive effects for nonvolatile and high-speed operation, and spin–orbit torque MRAM (SOT-MRAM) further improves writing efficiency. Ferroelectric memory (FeRAM) [8] exploits the polarization properties of ferroelectric materials to achieve energy-efficient, fast, and nonvolatile storage. In addition, optical and quantum memories [9,10] explore innovative paradigms for high-performance systems using optical longitudinal and quantum states. Compared to two-terminal memory [11], three-terminal OFETM has many advantages, such as the fact that one does not need to add other circuit components to select the target cell [12], and one can perform accurate charge modulation, non-destructive readout, and multi-bit storage. According to different memory mechanisms, OFETM can be classified into floating-gate OFETM (FG-OFETM), ferroelectric OFETM (Fe-OFETM), and polymer electret OFETM (PE-OFETM) [13,14,15,16]. Fe-OFETM uses a ferroelectric material as the gate dielectric. The polarization state of the ferroelectric insulator is changed by applying an external voltage, thereby accurately adjusting the carrier concentration in the channel. Therefore, the “0” and “1” states can be read out with a lossless drain current. Although Fe-OFETM has many potential advantages, such as fast reading and writing speeds and low power consumption during programming and erasing, ferroelectric materials usually have rough surface morphology [17], and due to the semi-crystalline nature of the material, the programming and erasing time is longer and the retention time is relatively shorter compared to FG-OFETM. PE-OFETM also has potential advantages, such as polymer electret materials having good flexibility, a low cost of raw materials, and a simple manufacturing process. However, the stability of polymer materials is susceptible to environmental factors, which may lead to performance degradation in long-term use. Moreover, the reading and writing speed is slower than that of other types of memory. Compared with Fe-OFETM and PE-OFETM, FG-OFETM has attracted much attention because it is endowed with a more stable data retention capability and excellent fatigue resistance [18,19,20,21,22].

Over the past decade, research on FG-OFETM has mainly focused on manufacturing and optimizing the performance of floating-gate (FG) materials. When nanoparticles (NPs) are used as the FG layer, the memory performance of FG-OFETM can be enhanced by adjusting the size of NPs and the distribution density in the FG layer. Commonly used materials include metal NPs [23], quantum dots [24], inorganic NPs [25], and organic NPs [26]. Xu et al. [27] proposed a flexible FG-OFETM based on an integrated molecular FG/tunneling layer and a pn heterojunction channel layer, which was prepared by configuring a mixed solution of polymer semiconductor poly (9,9-dioctylflfluorene- co-benzothiadiazole) (F8BT) NPs and polystyrene (PS) and then spin-coating on poly (vinylidene flfluoride-triflfluoro-ethy-lene-chloroflfluoroethylene) [P(VDF-TrFE-CFE)] film to obtain an integrated floating-gate/tunneling layer thin-film memory. The device presents a large memory window of 21.6 V at an operating voltage of ±60 V. After 200 cycles of P/E operation, device performance does not degrade significantly, showing excellent erasing endurance and a highly stable charge storage retention capability for up to 10 years. Shu et al. [28] prepared NPs by the mixed solution method and mixed them with poly(methyl methacrylate) (PMMA) to prepare a flexible OFETM with an integrated floating-gate/tunneling layer, which had a memory window of 9.5 V after ±40 V P/E operations. After bending 6000 times with a bending radius of 3 mm, it still exhibited excellent retention characteristics. Wang et al. [29] prepared an organic field-effect transistor memory based on single-walled carbon nanotubes as a nano-FG by the solution method. Under an operating voltage of ±60 V, the device exhibited a large memory window of 26.7 V, and the device memory switch ratio exceeded 10³. After 500 cycles of programming and erasing, it still exhibited excellent erasing endurance and retention characteristics. Yan et al. [30] used polysilicon material as a charge-trapping layer to prepare FG-OFETM. With the assistance of the TCAD tool, simulations were conducted, and it was verified that the device exhibited a large memory window of 57.5 V and a current on/off ratio of more than 10³ after ±70 V_P/E operation. From the above literature, it is clear that a large memory window can be obtained by FG-OFETM. However, it is also found that this approach requires a high operating voltage, and the retention characteristics need to be further improved. In order to improve this situation, it is necessary to find a material with a high charge-trapping capability and low operating voltage to enhance the performance of OFETM.

An n-type semiconductor material is usually used as the active layer in OFET devices and can also be used as an FG layer in FG-OFETM. For example, Liu et al. [31] prepared nano-FG memory, with ZnO nano-crystals being used as a charge-trapping layer. Jin et al. [32] prepared thin-film transistor memory based on ZnO as a charge-trapping layer by utilizing the atomic layer deposition method. Yu et al. [33] reported an OFET with the n-type semiconductor ZnO embedded in pentacene as the active layer. Based on the theory of electrostatic induction, the hole barrier caused by the pentacene defect layer can be adjusted by the thickness of the n-type semiconductor intermediate layer and the carrier density, which can reduce the barrier height of the hole injection into the pentacene, thus reducing the operating voltage of the device. Due to the low-temperature-processing advantages of organic semiconductors, one study chose the n-type polymer semiconductor N2200 to replace ZnO. As an n-type semiconductor material, N2200 is often used as an active layer in organic field-effect transistors. When it was introduced into the OFET with pentacene as the active layer (N2200 is placed between the pentacene and the gate insulator), it was discovered that when N2200 is utilized as an intermediate layer, it not only reduces the barrier for hole injection into the pentacene, but can also efficiently capture holes from the pentacene, thereby enhancing the performance of the OFET. The literature also suggests that N2200 can be used as a charge-trapping layer for OFETM, but its effect on the storage characteristics after changing the single N2200 charge-trapping layer geometry, operating voltage, and related physical parameters has not been studied and discussed in detail. Therefore, this paper will further investigate the interdependence between OFETM performance and the structural and physical parameters of the device when N2200 is used as the charge-trapping layer independently.

In this paper, the n-type semiconductor material N2200 is used as the FG layer. Through the utilization of the hot carrier injection and FN tunneling models, the storage characteristics of the device are numerically simulated with the assistance of the TCAD tool. The impacts of different P/E voltages, different impulse response times, and changes in the geometry (thickness of the tunneling layer) of the FG layer were investigated. The results show that the device exhibits a large memory window of about 16.1 V when the tunneling layer thickness is 8 nm and the operation voltage is ±45 V, 5 s. After 1000 cycles of P/E operations, the device performance does not degrade significantly, showing good fatigue resistance and a high read current on/off ratio.

2. Device Structure and Physical Models

2.1. Device Structure

A bottom-gate top-contact structure is adopted by the device, as shown in Figure 1. Thermally oxidized SiO₂-coated Si/p+ wafer was employed as the substrate. N2200 was spin-coated on the substrate as a floating-gate layer, PMMA was spin-coated on the N2200 surface as a tunneling layer, and pentacene was deposited on PMMA as an active layer. Finally, source–drain electrodes were deposited on pentacene using the thermal evaporation technique, and copper with a high work function was utilized as the source and drain electrodes. Refer to Figure S1 for details of the device fabrication process. Among these, PMMA can also be used as a charge-trapping layer [34]; however, in more reports in the literature, PMMA has been used as a tunneling layer in OFETM [35]. The energy level structure of PMMA makes it more suitable for functioning as a tunneling layer in this device structure. PMMA has a suitable lowest unoccupied molecular orbital energy (LUMO) level and the highest occupied molecular orbital energy (HOMO) level, which form a charge potential well in the PMMA/N2200/SiO₂ structure. This ensures that the charge captured by N2200 remains for a long time. N2200 is a specific material that exhibits distinctive charge-trapping and transport properties. Compared to the materials used in previous studies, N2200 has a more suitable energy level structure, which enables it to achieve higher efficiency and selectivity in the charge-trapping process. The detailed structural and physical parameters of the device are presented in

Table 1. Physical and structural parameters used for device simulation.

Parameter	Symbol	Value
Channel length	L/μm	80
Channel width	W/μm	1000
Thickness of source and drain electrodes	ST, DT/nm	50
Thickness of organic semiconductor	TS/nm	40
Thickness of tunneling insulator	TT/nm	6, 8, 10, 12, 14
Thickness of FG	TF/nm	18
Thickness of gate insulator	TOX/nm	90
Dielectric constant of gate insulator (PMMA)	εS	3.0
Dielectric constant of FG layer (N2200)	εS	3.5
Work function (Cu)	WF/eV	4.65~4.70
Active layer band gap width (pentacene)	Eg/eV	1.8~2.2
Band gap width of FG layer (N2200)	Eg/eV	3.3~3.6

.

2.2. Physical Models

In p-channel OFETM, the carrier transport mechanism is influenced by the temperature, electric field, organic semiconductor channel, hole traps between the electrode and gate dielectric layer, etc. [36]. The carrier transport of N2200 FG-OFETM is simulated by solving the Poisson equation, the carrier continuity equation, and the hole drift diffusion equation [37,38]. The physical models employed in the experiment are as follows:

$$\nabla \left({\epsilon }_0{\epsilon }_{\mathrm{S}}\nabla \phi \right)=q(n-p+N_{\mathrm{t}}-P_{\mathrm{t}})$$

(1)

$$\nabla \cdot J_{\mathrm{p}}=q(G-R)$$

(2)

$$J_{\mathrm{p}}=q{\mu }_{\mathrm{p}}{E}_{\mathrm{P}}-q{D}_{\mathrm{p}}{\nabla }_{\mathrm{P}}$$

(3)

$$D_{\mathrm{p}}={\mu }_{\mathrm{p}}{\displaystyle \frac{K_0{T}_L}{q}}$$

(4)

where φ is the electrostatic potential, N_t and P_t are the density of trapped electrons and holes, respectively, and n and p are the concentrations of electrons and holes. J_p is the hole current density, G indicates the rate of hole production, which is considerably affected by the hole potential barrier, and R is the recombination rate. E_p represents the electric field strength. D_p is the hole diffusion coefficient. According to Einstein Equation (4), J_p is expressed as

$$J_{\mathrm{p}}=q{\mu }_{\mathrm{p}}\cdot \left(E_{\mathrm{P}}-{\displaystyle \frac{K_0{T}_{\mathrm{L}}}{q}}\cdot {\nabla }_{\mathrm{P}}\right)$$

(5)

where K₀ is the Boltzmann constant, T_L represents the lattice temperature (300 K), and μ_p is the Poole–Frenkel mobility [39].

$${\mu }_{\mathrm{p}}={\mu }_{\mathrm{P}0}\exp \left[-{\displaystyle \frac{E_{\mathrm{h}0}}{K_{0}T}}+\left({{\displaystyle \frac{\beta }{k_{0}T}}}_{\mathrm{L}}-\gamma \right)\sqrt{E}\right]$$

(6)

In this model, μ_p0 represents the low-field mobility, E_h0 signifies the activation energy of the hole (E = 0) of 0.018 eV (E = 0), β is the Poole–Frenkel hole factor, and γ is the fitting parameter. In order to obtain good simulation results, the contact between the electrode and the organic semiconductor was defined as the Schottky barrier. Furthermore, the hot carrier injection and Fower–Nordheim (FN) tunneling models were used to simulate the injection of holes from the channel into the FG layer, as well as their release from the FG layer into the channel after P/E operations. The thermal emission current J and the tunneling current J_FN are delineated as follows [40,41]:

$$J=A^{\ast }{T}^2\exp \left(-{\displaystyle \frac{{\phi }_{\mathrm{T}}-\sqrt{q^{3}E}/4\pi {\epsilon }_{0\mathrm{X}}}{K_{0}T}}\right)$$

(7)

$$J_{\mathrm{FN}}=\mathrm{F}.\mathrm{AH}{E}^2\exp \left(-{\displaystyle \frac{\mathrm{F}.\mathrm{BE}}{E}}\right)$$

(8)

where J and J_FN are mainly influenced by E, T, and φ_T; φ_T is defined as the height of the interface barrier between the semiconductor layer and the tunneling layer (during programming) or the tunneling layer and the FG layer (during erasing); F.AH and F.BE are constants, while A* represents the Richardson constant. This research project primarily employed the mentioned physical models for numerical simulations in the investigation and analysis of FG-OFETM performance.

3. Results and Discussion

3.1. Output and Transfer Characteristics

The output and transfer characteristics of N2200 FG-OFETM are numerically simulated. The channel length of the device is 80 μm and the thickness of the tunneling layer is 8 nm, and different gate voltages are applied. The drain–source voltage (V_DS) ranges from 0 V to −40 V and the gate–source voltage (V_GS) from 0 V to −40 V in steps of −10 V, as shown in Figure 2a. The results show that the device exhibits typical p-channel field-effect transistor characteristics [42,43]. Figure 2b shows the initial transfer characteristic curve of the device, and the simulated transfer characteristics are in good agreement with experimental transfer characteristics. The field-effect mobility and threshold voltage (V_TH) of the device are calculated by the following equations.

$$I_{\mathrm{DS}}={\displaystyle \frac{\mu W{C}_{\mathrm{i}}}{2L}}\left(V_{\mathrm{G}}-V_{\mathrm{T}}\right)\cdot V_{\mathrm{DS}}$$

(9)

where C_i is the capacitance per unit area of the device, and the channel length (L) and width (W) of the device are 80 μm and 1000 μm, respectively. The device consists of two insulating layers: the first layer is the gate insulating layer (SiO₂) with a thickness of 90 nm, and the second layer is a tunneling layer (PMMA) with a thickness of 8 nm. C_i can be calculated according to the following formula [44]:

$${\displaystyle \frac{1}{C_{\mathrm{i}}}}={\displaystyle \frac{1}{C_{\mathrm{g}}}}+{\displaystyle \frac{1}{C_{\mathrm{t}}}}={\displaystyle \frac{d_{\mathrm{g}}}{{\epsilon }_0{\epsilon }_{\mathrm{g}}}}+{\displaystyle \frac{d_{\mathrm{t}}}{{\epsilon }_0{\epsilon }_{\mathrm{t}}}},$$

(10)

where d_g and d_t are the thicknesses of the gate insulating (SiO₂) and tunneling (PMMA) layers, and ε_g and ε_t are the dielectric constants of the gate insulating and tunneling layers, respectively. The calculation shows that the capacitance is 3.854 nF/cm² and the mobility is 0.074 cm²·V⁻¹·s⁻¹, and the I_on/I_off ratio exceeds 10⁴.

3.2. Storage Characteristics

Due to the hot charge carrier injection and FN tunneling mechanism, when a negative programming voltage is applied to FG-OFETM, the charge carriers enter the FG layer from the channel through the tunneling layer. On the other hand, when a positive erasing voltage is applied, the charge carriers captured by the FG layer are released into the channel. Both of the above-mentioned processes can lead to a shift in V_TH, which enables the device to exhibit distinguishable physical states for representing the binary 0 and 1. As shown in Figure 3a, the simulated results show that the transfer characteristic of N2200 FG-OFETM has obvious negative and positive shifts under the P/E voltage of ±45 V, 5 s, and the V_DS is constant at −5 V.

Figure 3b shows the energy level of N2200 FG-OFETM without the application of voltage, where E₀ is the vacuum energy level, and the LUMO and HOMO levels of pentacene are 3.1 eV and 5.1 eV, respectively. In Figure 3c, when a negative gate voltage (V_GS) is applied, holes are accumulated at the interface between the pentacene layer and PMMA layer; the energy band of PMMA is greatly bent, which causes holes to be injected into the N2200 FG layer from the channel. The holes captured by the FG layer generate an internal electric field in the opposite direction to the applied negative gate voltage, resulting in a negative shift in the transfer characteristic curve, which is a programming operation. Then, the positive erasing voltage is applied to the device; as shown in Figure 3d, the transfer characteristic curve is returned to the initial position. This is an erasing operation, which indicates that the holes captured by the N2200 FG layer during the programming operation are extracted back to the active layer due to the erasing operation.

The storage characteristics of N2200 FG-OFETM are closely related to factors such as the thickness of the tunneling layer, the magnitude of the operating voltage, and the operation time of P/E voltages. Firstly, the impacts of different tunneling layer thicknesses on the memory window are investigated. There are five samples with tunneling layer thicknesses of 6 nm, 8 nm, 10 nm, 12 nm, and 14 nm. Figure 4a shows that the memory windows that vary with the thickness of the tunneling layer are 24.4 V, 16.1 V, 12.1 V, 7.9 V, and 4.7 V, respectively. It can be observed that the offset of the transfer characteristic curve is the largest when the thickness of the tunneling layer is 6 nm. The memory window decreases with the increase in tunneling layer thickness, because a thinner tunneling layer allows charge carriers to be more easily captured by the FG. However, the tunneling layer should have a suitable thickness. Thicker tunneling layers could make P/E operations difficult, while thinner layers could affect the retention time of storage devices. Therefore, in the subsequent simulation, N2200 FG-OFETM with a tunneling layer thickness of 8 nm is selected as the research object.

Figure 4b,c show the various memory windows under different P/E operations. With the operating voltage changed from ±40 V to ±60 V (the operating time is uniformly 5 s), the corresponding memory windows are 12.4 V, 16.1 V, 25.9 V, 35.9 V, and 45.8 V, respectively. When V_P = −45 V, the transfer characteristic curve returns to the initial position, indicating that all the holes captured by the FG layer are extracted back to the active layer after erasing. When V_P/E > ±45 V, the transfer characteristic curves after erasing are on the right side of the initial position, which suggests that when the erasing voltage is increased, first, all holes in the FG layer are extracted back to the active layer, and then electrons are injected from the active layer to the FG layer and captured by the FG. This phenomenon may be explained by the hot carrier injection mechanism [30]: (1) In certain conditions, the erasing operation is more likely to occur than the programming operation. In Figure 3b, the programming process energy barrier value (1.62 eV) for holes crossing the tunneling layer is slightly higher than the erasing process energy barrier value (0.82 eV). (2) Although the electrons are minority carriers in the p-type pentacene active layer, the energy barrier value (1.54 eV) for electron transport between the LUMO level of pentacene and N2200 is lower than that (1.62 eV) for hole transport between the HOMO level of pentacene and N2200.

Furthermore, the impacts of applying different P/E operation times on the device are studied. As shown in Figure 4d, the V_DS = −5 V, V_P/E = ±45 V, and the P/E operation times are set at 1 s, 5 s, 10 s, and 15 s, respectively. It can be observed that the memory windows of the device rise with the increase in the P/E operation time. The time integration of the FN tunneling current density in Equation (8) shows that the longer the operation time applied is, the more charge carriers are tunneled from the active layer into the FG layer, although the magnitudes of the P/E voltages are the same. However, when the P/E operation time exceeds 5 s, the positive and negative offsets of the transfer characteristic curves do not change significantly. This phenomenon indicates that the ability of the FG to capture charges has a certain limit. The results are also consistent with those previously reported in the literature [30]. As the number of captured charges in the FG layer increases, the built-in electric field generated by the FG layer becomes stronger. The direction of the built-in electric field is opposite to the P/E electric field, which leads to a tunneling electric field decrease during P/E operation. When the actual electric field of the tunneling layer is less than the minimum electric field required for FN tunneling to occur, the charge carried in the active layer will not be further injected into the FG layer. Although the P/E operation time is increasing, the charge in the FG layer will not continue to increase. Therefore, the memory window no longer increases significantly when the P/E operation time exceeds 5 s.

Table 2. Comparison of FG-OFETM performance of different FG layer materials.

FG Layer	Tunneling Layer	VP/VE (V)	Memory Window (V)	Reference
Gold nanoparticles	PMMA	+80/−150	43	[45]
Single-walled carbon nanotubes	PMMA	+60/−60	26.7	[29]
Polysilicon	PMMA	+60/−60	9.28	[46]
F8BT	PMMA	+40/−40	9.28	[28]
C60	TTC	+40/−40	8.0	[47]
N2200	PMMA	+45/−45	16.1	This work

summarizes the memory windows and P/E voltages of FG-OFETM with different FG layer and tunneling layer materials in the recent literature. The comparison results show that the N2200 FG-OFETM presented in this work has a relatively low P/E voltage and large memory window (V_P/E = ±45 V, 5 s; memory window is 16.1 V).

Finally, the effect of temperature on the device’s performance was investigated. A series of temperature-controlled experiments were designed to test the device in different temperature ranges (40 °C, 60 °C, 80 °C, 100 °C, and 120 °C) to study the effect of temperature changes on key performance parameters such as the memory window, as shown in Figure 5. It can be seen from Figure 5a,b that temperature significantly impacts the programming characteristics of the device and has almost no effect on the erasure characteristics. When the temperature is 40 °C, the memory window of the device is largest, reaching 32.7 V. With the increase in temperature, the memory window of the device gradually decreases, and when the temperature is ≥80 °C, the transfer characteristic curve of the device no longer changes. Through these temperature stability tests, the memory performance of the device in different temperature environments can be better understood, and some references for subsequent temperature effects on device performance can be provided. Table 2 summarizes the memory windows and P/E voltages of FG-OFETM with different FG layer and tunneling layer materials in the recent literature. The comparison results show that the N2200 FG-OFETM presented in this work has a relatively low P/E voltage and large memory window (V_P/E = ±45 V, 5 s; memory window is 16.1 V).

For P-type OFETM, under a certain V_DS, when V_GS is less than V_TH, I_DS is almost zero and the transistor is in the off state (I_OFF). When the negative V_GS exceeds V_TH, a conductive channel is induced in the active layer, I_DS increases rapidly, and the device is in the on state (I_ON). P/E operation causes V_TH drift, and at the same V_GS and V_DS, the I_DS may exhibit differences in order of magnitude. Based on the above-mentioned characteristics, the I_DS of N2200 FG-OFETM with programming–read–erasing–read (PRER) cycles is investigated. The corresponding voltages are V_P = −45 V, read voltage (V_R) = −20 V, V_E = 45 V, and V_R = −20 V at a time step of 5 s. After 200 PRER cycles, the memory characteristics of the device did not change significantly, indicating that N2200 FG-OFETM exhibits exceptional erasing endurance, as shown in Figure 6a. Figure 6b displays the retention characteristics of N2200 FG-OFETM. After a P/E voltage of ±45 V, 5 s, is applied to the device, the read current on/off ratio reaches 10³.

4. Conclusions

In this paper, FG-OFETM with a bottom-gate top-contact structure was designed by using the n-type semiconductor N2200 as the FG layer. Through the utilization of the carrier injection and FN tunneling models with the assistance of the TCAD simulation tool, the variations in FG-OFETM memory performance under different tunneling thicknesses, operating voltages, and pulse operation times were investigated. The results show that the memory window with a tunneling layer thickness of 8 nm is 16.1 V, and the current on/off ratio is about 10⁴ under the P/E voltage of ±45 V, 5 s. In comparison to the FG-OFETM results reported in previous research (in Table 2), N2200 FG-OFETM can obtain a relatively larger memory window at a small operating voltage. After 200 cycles of PRER testing, the device shows good endurance to erasing and writing, and its read current on/off ratio reaches 10³.