A Method for Grading Failure Rates Within the Dynamic Effective Space of Integrated Circuits After Testing

Abstract

Integrated circuits that pass testing still have quality differences, thus making grading necessary. Traditional grading methods rely on static testing and electrical measurements, which are challenging to achieve precise grading, time-consuming, and costly. A new grading method based on the failure rate within a dynamically effective space is proposed. This method dynamically adjusts the evaluation space and uses an exponential decay function to calculate the influence weight of each neighboring chip on the evaluated chip, thereby computing the weighted failure rate of the evaluated chip and quantitatively grading the chips after wafer testing based on the scores. Experiments show that this method not only accurately captures quality differences and ensures grading accuracy but also significantly improves grading efficiency.

1. Introduction

In the semiconductor manufacturing industry, chip testing directly affects the quality and reliability of final products [1]. Each chip must pass through rigorous electrical characteristics tests, including probe testing and functional testing [2], in order to ensure the chip meets the predetermined performance standards before entering the market. In addition to traditional testing methods, the semiconductor testing field has begun to adopt cutting-edge technologies such as quantum dot testing and electromagnetic characteristic analysis [3]. These technologies aim to explore the micro-level electrical characteristics and failure modes of chips. The development of Automatic Test Equipment (ATE) [4] has significantly facilitated the implementation of large-scale chip testing, which continues to expand its operation spheres to include higher speeds, larger ranges, and lower costs. This implementation has moved at superhigh speeds, increasing testing efficiency and coverage, and decreasing the false negatives and false positives. At the same time, the application of artificial intelligence and machine learning has enhanced the optimization of testing processes and the precision of defect detection [5]. The establishment and implementation of international standards such as IEEE 1149.1 (JTAG) [6] have provided a uniform and standardized framework for global chip testing practices. With the emergence of technologies like IoT, 5G communications, and AI, chip testing has welcomed new opportunities and challenges, leading to innovative developments in testing technologies that improve and ensure quality assurance in chip design and manufacturing [7].

Chip testing not only helps to identify and eliminate defective chips but also provides the basis for chip grading [8]. Although chips that have passed basic quality control still pose a failure risk, this risk is often related to the chip’s performance stability under different working conditions [9,10]. Through refined grading, manufacturers can optimize resource allocation by using high-performance chips for applications with stringent requirements and assigning lower-performance chips to other applications which are sensitive to cost [11]. This strategy not only optimizes resource use and enhances the market competitiveness of product lines [12], but it also reduces potential safety issues caused by chip failures. Chip grading serves not only advancing technology but also controlling costs [13,14], thereby impacting competitiveness.

With the pace of development within the industry, it has become overwhelmed with chip design and manufacturing, with rising demands for grading and quality control. Traditional chip grading methods rely on static testing and electrical measurements [15], which are increasingly inefficient in rapidly changing production lines, often resulting in the inaccurate characterization of minute performance differences. This ultimately leads to incorrect grading, raising the cost of high-density integrated circuits and high-performance chips [16]. Additionally, traditional testing equipment is physically limited in sensitivity and accuracy, so it cannot catch the very subtle instances of incorrect grading, which in turn negatively influences the accuracy and trustworthiness of the grading [17]. As a result, unified testing standards can no longer meet the needs of modern high-performance, high-reliability integrated circuits [18,19].

To accommodate the increasingly complex designs and production demands of integrated circuits, manufacturers and research institutions are adopting a variety of cutting-edge technologies and methods to improve the accuracy and efficiency with which chips can be graded [20]. Dynamic testing technologies enable more comprehensive performance evaluations under simulated real-world conditions [21], examining basic electrical characteristics, analyzing long-term variability, and investigating failure modes. Alongside such advanced techniques, artificial intelligence and machine learning are extensively used for testing data analysis, where training from historical data allows for the automatic identification of performance issues or potential derivatives. These innovations not only advance the sophistication of chip grading but also improve its practicality [22], helping manufacturers meet market demands for high-performance and highly reliable chips.

Domestic companies, such as SMIC and Huahong Semiconductor [23], are developing more advanced grading technologies using machine learning and artificial intelligence algorithms, increasing grading accuracy and data processing capabilities. This system has increased automation and processing, which has consequently raised operating and maintenance costs owing to its complexity and skill requirements [24]. Hai Guang Integrated Circuit Design Company [12] proposed a dynamic adjustment grading method where the final test result of packaged chips can be used as a grading scale. The method thus developed gives a good accuracy as well as consistency in grading by packaging and testing bare dies, but this also leads to increased complexity and testing time in the systems [25].

In the US, Europe, and Japan, companies such as Intel, Samsung, and TSMC use highly automated and integrated testing systems [11]. These include 3D X-ray microscopy, automated defect detection, high-speed electrical testing, and advanced image processing technologies that thoroughly characterize and classify chips [26]. Winbond uses sample classification methods to significantly reduce testing time, at the cost of compromising comprehensiveness. TSMC employs PCA-based methods that aim to optimize yield analysis and improve data-processing efficiency [27], although this requires complex data support. While grading precision and efficiency have indeed been very much improved via these techniques, their general uptake has been hampered because of high costs and technical complexity.

Against this backdrop, researchers have introduced artificial intelligence algorithms, combined with traditional testing methods, for efficient chip grading [28]. The Parameter Parts Average Testing (PPAT) combined with Statistical Yield Analysis (SYA) allowed the real-time analysis of the defects present and dynamic adjustments to made to the allocation of resources in tests to optimize testing [29,30]. By combining PPAT and SYA with artificial intelligence algorithms, it can optimize the allocation of testing resources, ensuring product quality and reliability.

Additionally, regional PAT improves the stringency of product quality control by evaluating the proximity weights of bare dies and eliminating good bare dies around failed ones [31,32]. However, these methods still have deficiencies in dynamic adjustments and real-time environmental adaptation, thus making it difficult to cope with inherent process variations and outlier occurrences during production.

Traditional grading systems are riddled with excessive rigidity and poor accuracy. Existing machine learning and artificial intelligence algorithms show great dependence on extensive historical data that are not often available for real-time environments [33,34,35]. To tackle these setbacks, this paper proposes an innovative method for grading chips where grading is based on failure rates within a dynamically effective space and the effect of nearby chips is assessed through weighted failure rate, which autonomously modifies the grading span and precludes grading errors that had previously resulted from using the traditional method.

It also uses an exponential decay function to avoid the interference of extreme values, as well as having the ability to dynamically adjust the failure rates of neighboring areas, which can more accurately handle the dies at the wafer edges. Compared with existing machine learning-based chip grading methods, the proposed method does not rely on complicated data processing and training data steps, reflecting the characteristics of high accuracy and low resource consumption.

Although chips after wafer-level testing may still have failure risks, this grading method can effectively distinguish chip grades, reducing potential risks in subsequent applications. This method is suitable for high performance chip production and can reduce resource waste caused by inaccurate grading.

To clarify the terminology, we use “die” to specifically refer to individual, unpackaged chips on the wafer, while “chip” is used as a general term that can refer to both packaged and unpackaged semiconductor components. For simplicity and readability, the term “chip” is retained throughout the text, but in the context of wafer-level testing, it refers to dies. The abbreviations used in the algorithms are listed in

Table A1. Abbreviations and Their Explanations.

Abbreviation	Full Name	Meaning
PPAT	Parameter Parts Average Testing	A chip quality evaluation method based on parameter average.
SYA	Statistical Yield Analysis	A statistically based method for analyzing chip yield.
ATE	Automatic Test Equipment
PCA	Principal Components Analysis	Dimensionality reduction to transform multiple indicators into a few comprehensive ones.
I-PAT	Inline Part Average Testing
CNN	Convolutional Neural Network

in Appendix A, while those used in the experiments and introduction are listed in

Table A2. Abbreviations and their full names in algorithm and experiments.

Abbreviation	Full Name	Meaning
Average	The average score
SD	standard deviation
afr	Average failure rate	Used to measure the average failure rate of neighboring chips.
W_score(${\text{wfr}}_i$)	Weighted failure rate	The weighted failure rate of the evaluated die (i).
${\text{p\_score}}_k$	Parameter score of test item k
T_score	${\text{test\_total\_score}}_i$	Total score of test items for the evaluated chip (i).
${\text{p\_weight}}_k$	Weight of parameter item k
F_score	${\text{final\_score}}_i$	The final score of the evaluated chip (i).
OSN_TCK(V)	Open Short Net Test Clock Voltage

in Appendix A.

2. Algorithm Description

This paper uses the fault rate around the evaluated die (chip) as the main evaluation criterion and utilizes other test parameters’ proximity to their specified standards during the testing phase as auxiliary criteria. By calculating the weighted normalized values of both, the evaluated die is given a comprehensive score for subsequent grading. The specific process is shown in Figure 1.

2.1. Calculate the Failure Rate of the Evaluated Die

Calculating the failure rate of a die first requires determining its evaluation range. The evaluation of each die begins by defining its evaluation space, which is dynamically adjusted based on the failure rates of neighboring dies.

2.1.1. Determination of Effective Space

• Processing of evaluated dies with sufficient number of surrounding dies
  • Set a minimum radius (r = 3) as the initial radius and calculate the failure rate within the current radius:

    $$\mathrm{Fault}\mathrm{Rate}={\displaystyle \frac{\mathrm{Number}\mathrm{of}\mathrm{Faulty}\mathrm{Dies}\mathrm{within}r}{\mathrm{Total}\mathrm{Number}\mathrm{of}\mathrm{Dies}\mathrm{within}r}},$$

    (1)

    where the “Number of Faulty Dies within r” is the number of faulty dies within the current radius, and the “Total Number of Dies within r” is the total number of dies within the current radius.
  • Set a maximum threshold R and dynamically adjust the evaluation radius until the final radius is obtained:
    Within the range of $r=3$, if the Fault Rate is less than ${\displaystyle \frac{1}{3}}$, expand the radius to $r+1$. If the Fault Rate is still less than ${\displaystyle \frac{1}{3}}$ when the evaluation radius is 4, then extend it to $r+3$, choosing $r=7$ as the final radius (if the maximum range of the evaluated die is less than 7, choose the current r as the final r).
    In the range where $r=3$, if the Fault Rate is less than ${\displaystyle \frac{1}{3}}$, expand the radius to $r+1$, meaning that the evaluated radius is 4; if it exceeds ${\displaystyle \frac{1}{3}}$, expand r outward three times, while each time the Fault Rate is less than ${\displaystyle \frac{1}{3}}$, select this time r for subsequent calculation. If the Fault Rate is greater than ${\displaystyle \frac{1}{3}}$, expand r outward three times, and each time, if the Fault Rate is greater than ${\displaystyle \frac{1}{3}}$ total, select $r+3$ for subsequent calculation.
    Otherwise, extend to $r=R$.
• Processing of edge parts
  During the expansion of the radius, it is necessary to evaluate whether the number of dies within the current radius is sufficient to determine if there are missing dies in certain directions or if the evaluated die is located at the edge of the wafer. For dies located at the edge of the wafer and missing dies in certain directions, the average failure rate of neighboring points is used as virtual data to estimate the average failure rate of a missing part.
  • Starting from radius 1, gradually check the actual number of neighboring dies within each radius range. If the data in a certain direction of the edge die are insufficient, calculate the average failure rate (afr) of the currently available neighboring die radius range:

    $$\mathrm{afr}={\displaystyle \frac{\mathrm{\Sigma }\mathrm{failure}\mathrm{state}\mathrm{of}\mathrm{actual}\mathrm{adjacent}\mathrm{die}}{\mathrm{the}\mathrm{number}\mathrm{of}\mathrm{actual}\mathrm{adjacent}\mathrm{dies}}},$$

    (2)
  • Dynamically adjust the radius and fill in data. Dynamically calculate and update the average failure rate of neighboring dies according to the evaluation radius at each step. Each time the evaluation radius is expanded, recalculate the average failure rate of all actual neighboring dies within that radius and use these data to fill in the virtual neighboring dies.
  • If sufficient neighboring die data are already included within a certain radius range, or further expansion of the radius does not add new actual neighboring dies, expand and judge according to the above steps, determine the final evaluation space, and fill in the missing die data for different radius.

2.1.2. Calculate Impact Weight

On a wafer, regional failures may affect the reliability of surrounding chips. The degree of impact varies according to the different distances between the failed chip and the evaluated chip, The closer a faulty die is to the die under evaluation, the greater its impact. Calculate the influence weight of each chip within the final evaluation space on the evaluated chip using the following exponential decay function:

$${\mathrm{Weight}}_{ij}=e^{-\lambda d_{ij}},$$

(3)

where the $d_{ij}$ is the distance from ${\text{die}}_i$ be evaluated to the neighborhood ${\text{die}}_j$, and $\lambda$ is the attenuation coefficient for controlling the decay rate of the influence.

The exponential decay function provides a smooth and continuous way to reduce the influence of other dies they are farther from the evaluation center die. When the value of $\lambda$ increases, the ${\text{Weight}}_{ij}$ decreases. Figure 2 shows how different $\lambda$ values (e.g., $\lambda$ = 0.2, 0.5, 1, 2) affect ${\text{Weight}}_{ij}$, where the horizontal axis represents the distance between ${\text{die}}_j$ and ${\text{die}}_i$, and the vertical axis represents the ${\text{Weight}}_{ij}$. According to Figure 2, smaller $\lambda$ values result in slower weight decay, making the impact of farther dies on the evaluated die more significant and applicable to a larger evaluation range. However, this may also introduce some irrelevant interference; larger $\lambda$ values cause rapid weight decay, and the influence of nearby dies is more significant, which can avoid interference from distant dies and is suitable for the accurate classification of local ranges.

2.1.3. Calculation of Final Weighted Failure Rate

Each die has two states: normal (marked as 1) and failed (marked as 0). After determining the evaluation range, perform a weighted calculation of the failure rates of all dies within its range to obtain the weighted failure rate (wfr) of the evaluated die:

$${\mathrm{wfr}}_i={\displaystyle \frac{{\sum }_{j\in \mathrm{neighbors}}({\mathrm{Weight}}_{ij}\times {\mathrm{state}}_j)}{{\sum }_{j\in \mathrm{neighbors}}{\mathrm{Weight}}_{ij}}},$$

(4)

where the ${\mathrm{state}}_j$ is the state of ${\text{die}}_j$, with 0 for failure and 1 otherwise. The denominator is the sum of the weights, ensuring that the score is calculated based on relative rather than absolute failure impact. This makes it possible to more fairly assess the influence of neighboring die failures on the central die, while taking distance into account.

2.2. Performance Evaluation by Parameters

During the wafer testing phase, there are a lot of test data for each evaluated die. The score for each test item needs to be calculated based on the test results of these test parameters and their proximity to the upper and lower limits of the test items. The closer the test value is to the specified range, the higher the score.

2.2.1. Calculation of the Score of Each Parameter Item

Calculate the score for each test item k:

$${\mathrm{P\_score}}_k=1-{\displaystyle \frac{min\left(\right|{\mathrm{test\_value}}_k-{\mathrm{uplimit}}_k|,|{\mathrm{test\_value}}_k-{\mathrm{downlimit}}_k\left|\right)}{{\mathrm{uplimit}}_k-{\mathrm{downlimit}}_k}},$$

(5)

where the ${\mathrm{P\_score}}_k$ is the score of k, ${\mathrm{test\_value}}_k$ is the test result of a certain k test item of the evaluated die, and ${\mathrm{uplimit}}_k$ and ${\mathrm{downlimit}}_k$ are the specified ranges of this test item, respectively.

2.2.2. Calculation of the Test Total Score of the Test Item

After obtaining the scores of each parameter item, perform weighting and normalization to ensure that all scores reasonably reflect the test total score:

$${\mathrm{test\_total\_score}}_i=\sum _{\mathrm{all}k}{\displaystyle \frac{{\mathrm{P\_weight}}_k\times {\mathrm{P\_score}}_k}{{\sum }_{\mathrm{all}k}{\mathrm{P\_weight}}_k\times {\mathrm{P\_score}}_k}},$$

(6)

where ${\mathrm{P\_weight}}_k$ highlights the relative importance of different test items.

2.3. Rank Division

2.3.1. Calculation of the Total Score

Combine the weighted failure rates derived from the influence of all neighboring die failures with the test total scores, and multiply each by its corresponding weighting factor to calculate a comprehensive score as follows:

$${\mathrm{Score}}_i=w_1\times {\mathrm{wfr}}_i+w_2\times {\mathrm{test\_total\_score}}_i.$$

(7)

where $w_1$ and $w_2$ are the weights. In practice, $w_2$ is less than $w_1$. $w_1$ and $w_2$ are used to adjust the influence of the weighted failure rate and test phase score on the total score.

2.3.2. Result Optimization

To achieve consistency in the magnitude and improve the generality of the model to make it more robust to input data of different magnitudes or units and to allow the scoring system to be more widely applicable to different evaluation environments and standards, perform normalization on the results as follows:

$${\mathrm{final\_score}}_i={\displaystyle \frac{{\mathrm{Score}}_i-min\left(\mathrm{Score}\right)}{max\left(\mathrm{Score}\right)-min\left(\mathrm{Score}\right)}}.$$

(8)

2.3.3. Grade Definition

Based on the final normalized total score and using the standard deviation method, the deviation of each die from the average level of the entire batch is assessed to ensure quality consistency.

• Calculate the average score of all dies.
• Calculate the standard deviation of the scores.
• Set multiple quality levels as shown in

  Table 1. Quality grading levels.

  Grade	Score Range	Description
  A	>$\mathrm{Average}+1\mathrm{SD}$	Excellent
  B	$\mathrm{Average}\mathrm{to}\mathrm{Average}+1\mathrm{SD}$	Good
  C	$\mathrm{Average}-1\mathrm{SD}\mathrm{to}\mathrm{Average}$	Fair
  D	<$\mathrm{Average}-1\mathrm{SD}$	Poor

  :

Where Average refers to the average score, and “SD” denotes the standard deviation. Apply the above criteria to each die and classify it into the corresponding quality grade.

3. Experimental Procedure

This experiment was based on a real production dataset containing the test results and status information of thousands of chips.

3.1. Description of the Data Set

In this experiment, the data are divided into three parts: metadata, headers, and data.

The metadata part mainly includes the following information: test program path (Test_Program), the specific batch being tested (Lot_ID), operator identifier (Operator), specific test identifier (Test_ID), and the date and time of the test (Date).

The headers section includes the upper limit for each measurement item (UpLimit), the lower limit for each measurement item (DownLimit), and the unit for each measurement parameter (Unit).

The measurement data mainly include the following information: the serial number of the test item (Serial), the test site number (Site), the X coordinate of the probe (ProbeX), the Y coordinate of the probe (ProbeY), and other columns representing specific measurement parameters (such as OSN_TCK(V), IDD(A), LDO(V), etc.) along with their respective units and recorded values.

3.2. Data Cleaning

In this experiment, in order to ensure the accuracy of the data used, the raw data were obtained from a CSV file, the chip test data were read using the Python’s Pandas library for reading the CSV file, and the data were loaded into a DataFrame, detect, filter, and mark missing values, outliers, and format inconsistencies. The preliminary cleaning of data by using python scripts was undertaken to remove any outliers or missing data. The data format was standardized to ensure that all data items met the analysis requirements.

The table structure was defined using the DB Browser for SQLite and the cleaned data were imported into the table using Pandas. During the experiment, to simplify operations and ensure data relevance, specific columns were selected from the raw data. These columns include the unique identifier of the chip (Serial), the coordinates of the chip on the wafer (ProbeX, ProbeY), and the test results of certain parameters and their upper and lower limits, which are stored in the table.

At the same time, based on the raw data, the table structure was defined with the addition of four extra fields: state for storing the chip status, failure_rate_score for the weighted failure rate score, test_data_score for the test item score, total_score for the total score, and grade for the final grade.

3.3. Specific Experimental Procedure

Before the experiment, the status of each chip was determined from the database based on its test results and upper and lower limits, and chips were marked as normal (STATE = 1) or failed (STATE = 0). The experiment created three scripts to calculate the weighted failure rate score (${\text{wfr}}_i$), parameter item score (${\text{test\_total\_score}}_i$), total score (${\text{final\_score}}_i$), and grade evaluation, respectively. For the weighted failure rate score, the evaluation space was dynamically adjusted, the evaluation range was determined, the influence weights were calculated to obtain the weighted failure rate, and the average failure rate of neighboring chips was used as virtual data to supplement chips with insufficient data in the evaluation space. The parameter item scores were combined to obtain the total score, grade classification was performed, the database data were updated, and the csv file was exported.

3.4. Experiment for Comparison

To verify the effectiveness of the proposed chip grading method based on failure rates within a dynamically effective space, we compared it with the traditional electrical testing grading method. The specific steps are as follows:

• Use other parameter items in the wafer test for calculation to obtain the test item scores for each chip (the parameter item OSN_DCIN was selected for this experiment).
• Calculate the total score for each chip and perform grade classification, and save the results to the database (Grade_Test).
• A comparative analysis of the results was made: compare the grading results of this method (Grade) with the traditional method (Grade_Test), and calculate the accuracy and confusion matrix to evaluate the performance of both methods.
  • Obtain Grade and Grade_Test column data from the database.
  • Accuracy calculation: Use the accuracy_score function in sklearn.metrics to calculate the accuracy of Grade and Grade_Test, evaluating the grading accuracy of this method compared to the traditional method.
  • Calculation of confusion matrix: Use the confusion_matrix function in sklearn. metrics to calculate the confusion matrix of Grade and Grade_Test, analyzing the classification performance for each category (A, B, C, D).
  • Analyze and interpret the results: Calculate precision, recall, and F1 scores to show the model’s performance in each category.

Through the above experimental steps and results analysis, the feasibility and effectiveness of the grading method proposed in this paper were systematically evaluated in practical applications, and the results were compared compare it with traditional method for verification.

3.5. Experimental Result

3.5.1. Partial Experimental Results

Some experimental results are shown in

Table 2. Partial experimental results.

Id	W_Score	T_Score	F_Score	Grade
139	0.994552	0.595353	0.994552	B
140	0.986764	0.597397	0.986764	C
141	0.966017	0.596029	0.966017	C
142	0.913740	0.597999	0.913740	D
143	0.991467	0.595927	0.991467	B
145	0.991294	0.595037	0.991294	C
146	0.992589	0.596689	0.992589	B
147	0.976132	0.588751	0.976132	C
148	0.914109	0.595905	0.914109	D
149	0.966588	0.595990	0.966588	C
150	0.987443	0.596877	0.987443	C
151	0.995343	0.594699	0.995343	B
152	0.986764	0.597397	0.986764	C

, where the W_score is the weighted failure rate of the evaluated chip, the T_score is the parameter item score of the evaluated chip, and the F_score is the total score.

3.5.2. Comparative Experimental Results

The confusion matrix generated by the comparison experiment is shown in

Table 3. Confusion matrix.

Actual\Predicted	Grade A	Grade B	Grade C	Grade D
Grade A	0	0	0	0
Grade B	0	2679	184	14
Grade C	0	82	27	1
Grade D	0	23	2	25

, and its heatmap is shown in Figure 3, illustrating the performance of the proposed chip grading method based on failure rates within a dynamically effective space across various categories. The specific analysis is as follows:

• Accuracy: 0.899, indicating that 89.9% of the samples in all test samples were correctly classified by this method.
• Each piece of data of the confusion matrix represents the classification between different categories, which is explained as follows:
  • First row (samples with actual category A): No actual category A samples were correctly or incorrectly classified (all values are 0).
  • Second row (samples with actual category B): 2679 actual category B samples were correctly classified as B. A total of 184 actual category B samples were incorrectly classified as C. A total of 14 actual category B samples were incorrectly classified as D.
  • Third row (samples with actual category C): 82 actual category C samples were correctly classified as B. One actual category C sample was incorrectly classified as D.
  • Fourth row (samples with actual category D): 23 actual category D samples were correctly classified as B. Two actual category D samples were incorrectly classified as C.

Performance metrics by category are shown in Figure 4, demonstrating the performance of the classification model in four categories (A, B, C, D). The blue line represents precision, showing the proportion of samples predicted as the category by the model that are actually in that category; the green line represents recall, showing the proportion of all samples actually in that category that are correctly predicted by the model; the red line represents the F1 score, which is the harmonic mean of precision and recall, used to measure the overall performance of the model.

The comparison experiment shows that the proposed grading method achieves an accuracy of 89.9%, indicating that it can correctly classify chips in most cases with high accuracy.

3.5.3. Algorithm Comparison

Memory and time consumption tests and robustness tests were conducted for the grading method using failure rates within a dynamically effective space and the grading method relying on traditional electrical testing. The memory and time usage of the two algorithms are shown in

Table 4. Time and memory consumption.

Method\Test Content	Time	Memory
Proposed Method	0.69 s	62.88 MiB
Traditional Method [15]	1.52 s	63.90 MiB

, and the robustness test results are shown in Figure 5.

In actual production environments, the chip testing process may be affected by various random disturbances, such as instrument measurement errors, environmental interference, and noise during signal transmission. To validate the robustness of the proposed method under different noise levels, Gaussian noise was artificially introduced to simulate potential random disturbances. The level of noise is represented by the standard deviation $\sigma$, ranging from 0 to 8, simulating different noise environments. By adding random noise to the measured values of chip testing items, the instability of testing equipment and environmental interference can be simulated.

Figure 5 shows the grading results of the proposed method and traditional method at different noise levels. The proposed method (blue curve) shows almost no change with increasing noise levels, while the traditional method (orange curve) exhibits sensitivity to noise, indicating its susceptibility to random interference.

In terms of time and memory consumption, the average processing time of the proposed method is 0.69 s, while the traditional method is 1.52 s, which reduces time consumption by 54.6%. The proposed method uses 62.88 MiB of memory, which is 1.6% less than traditional method. Moreover, the proposed method has good robustness, which can provide more reliable results under complex production conditions.

In conclusion, the proposed algorithm can optimize memory usage, reduce computation and resource consumption while ensuring grading accuracy, and its good stability is suitable for production environments that require efficient processing of large-scale chip data.

4. Conclusions

This paper proposes a chip grading method based on weighted failure rates within an effective space, which improves the accuracy in chip grading, reduces testing time and costs, and provides a suitable, economical way to grade chips in the semiconductor industry. By introducing failure rates within a dynamically effective space and combining weighted failure rates with the exponential decay functions, the proposed method enhances the accuracy of evaluating chip performance and reliability, making it a novel solution for the semiconductor domain. Dynamically adjusting the evaluation space and filling in missing data parts could enhance grading accuracy, especially for chips on the edge. The proposed method is characterized by its capability to adapt to varying testing ambient conditions and diverse performance criteria for chips, thus making it suitable for the production of high-density and high-performance chips.

Future research can introduce more environmental variables, chip characteristics, and multidimensional data to increase the accuracy and applicability of the evaluation. Furthermore, adding advanced machine learning and artificial intelligence algorithms can increase the degree of intelligence and automation in chip grading, increasing grading accuracy and efficiency.