Prospects for the Use of Quasi-Mersen Numbers in the Design of Parallel-Serial Processors
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsТhe topic is of interest and can be applied in various applications. This article shows that a serial-parallel processor comparable in bit depth to a 16-bit binary processor can be implemented based on an algorithm built on the residue number system, the distinctive feature of which is the use of the first four quasi-Mersenne numbers. The specificity of these numbers allows to implement a fairly simple circuit of a modulo adder. The simplicity of its design (in comparison with existing analogues) is ensured by the transition to a trigger circuit, when for certain values ​​of the summed numbers the circuit can be in two different stable states.
It is necessary to format the text and caption in Fig.2.
Author Response
The authors sincerely thank the reviewer for his positive feedback and report that, in accordance with his comments, the formatting of the text and figure captions has been brought into line with the journal's requirements.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe primary research question investigates the potential for using quasi-Mersenne numbers to design a processor built on the residue number system (RNS) capable of serial-parallel computing. The focus is on developing a trigger adder modulo quasi-Mersenne numbers, which would allow for simpler and more efficient processing circuits, potentially enhancing computational performance for specific applications, such as convolutional neural networks.
The topic is original and relevant to the fields of computer architecture and computational mathematics. The study addresses a gap in designing efficient hardware that can handle partial convolutions more effectively, which is a growing need given the increasing use of convolutional neural networks (CNNs). The uniqueness of this work lies in employing quasi-Mersenne numbers in RNS-based processing and demonstrating the feasibility of constructing a serial-parallel processor capable of operating within this framework.
The research adds significant value by:
1) Demonstrating the construction and operation of an adder modulo quasi-Mersenne numbers.
2) Providing a practical scheme that could streamline specific computational processes, especially for tasks requiring efficient addition and multiplication.
3) Highlighting potential advancements in implementing digital logarithms for reducing multiplication operations to additions in Galois fields, adding a unique angle for practical processor design.
1) The methodology appears technically sound, with comprehensive RNS formation and adder circuit design descriptions. However, more in-depth comparative analysis with existing methods or implementations could strengthen the discussion.
2) To ensure robustness, the authors should include:
a) Comparative performance analysis with existing processor designs.
b) Extensive simulation under various operational conditions to validate stability and efficiency.
c) An assessment of potential errors or limitations, particularly in boundary cases involving Galois field operations.
The conclusions align well with the evidence and arguments presented. The logical progression from mathematical foundations to circuit implementation substantiates the proposed processor design's practicality and potential for further development. However, the conclusions could be enhanced by discussing any identified limitations or challenges encountered.
The references cited are appropriate, covering key topics related to RNS, Galois fields, and processor design. The inclusion of seminal and recent studies strengthens the credibility of the research. However, adding references directly compared to similar processor designs or highlighting real-world applications could enrich the background.
The provided circuit diagrams effectively illustrate the design of the trigger adder and its operation states. However, adding captions or explanations detailing each part's step-by-step function would improve clarity.
The table outlining the quasi-Mersenne numbers is clear and informative. Additional data, such as comparative performance metrics or other potential numbers, could benefit readers interested in exploring variations.
Consider elaborating on the practical implications of this design in contemporary and future hardware applications.
A prototype or practical simulation using FPGA or similar technology could provide tangible evidence of the proposed benefits. This could be easily verified by using VHDL representation of the design, with a Testbench in Modelsim.
This paper is a noteworthy contribution, particularly for specialists exploring efficient computational frameworks for digital signal processing and neural network operations. The improvements and controls outlined could further substantiate the findings and broaden the impact of the research.
Author Response
The authors sincerely thank the reviewer for the positive feedback and valuable comments. In accordance with each of the comments made, the following corrections have been made to the text of the article.
1. Comparative performance analysis with existing processor designs.
The text of the article includes a comparison with other types of devices that perform calculations modulo an integer, including references to patent literature (additions are made at the very beginning of section 2.3., highlighted in red).
2. Extensive simulation under various operational conditions to validate stability and efficiency.
Additional testing of the proposed adder circuit was carried out using the Testbench (VHDL language) and Verilog software products (additions are made to the end of section 2.4., highlighted in red).
3. An assessment of potential errors or limitations, particularly in boundary cases involving Galois field operations.
The software tools specified above were used to test the proposed electronic circuits in the entire range of values, and the adequacy of their functioning was verified. Additionally, the text of the article includes a detailed description of one of the most important (for the type of fields under consideration) limiting cases, formulas (17) and (18). The additions are highlighted in red.
4. The conclusions align well with the evidence and arguments presented. The logical progression from mathematical foundations to circuit implementation substantiates the proposed processor design's practicality and potential for further development. However, the conclusions could be enhanced by discussing any identified limitations or challenges encountered.
A discussion of the issues raised by the reviewer in this comment is included in the text of the conclusion (highlighted in red, last paragraphs)
5. The references cited are appropriate, covering key topics related to RNS, Galois fields, and processor design. The inclusion of seminal and recent studies strengthens the credibility of the research. However, adding references directly compared to similar processor designs or highlighting real-world applications could enrich the background.
The text of the article includes a comparison with existing technologies for performing calculations modulo an integer. In particular, references to patent literature are included (additions are made at the very beginning of section 2.3., highlighted in red).
6. The provided circuit diagrams effectively illustrate the design of the trigger adder and its operation states. However, adding captions or explanations detailing each part's step-by-step function would improve clarity.
The text of section 2.3 includes the necessary additional information (highlighted in red).
7. The table outlining the quasi-Mersenne numbers is clear and informative. Additional data, such as comparative performance metrics or other potential numbers, could benefit readers interested in exploring variations.
In response to this reviewer's comment, additional information (highlighted in red) has been added to the Discussions section. Section 2.3 also includes paragraphs at the end showing how the proposed approach can be extended to use RNSs formed by other primes.
8. Consider elaborating on the practical implications of this design in contemporary and future hardware applications.
In accordance with this comment, additional paragraphs have been included in the text of the Discussions section, which reflect the possibilities of using the proposed approach, including for the development of computing equipment on a non-trivial element base (highlighted in red font on a yellow background).
9. A prototype or practical simulation using FPGA or similar technology could provide tangible evidence of the proposed benefits. This could be easily verified by using VHDL representation of the design, with a Testbench in Modelsim.
Additional testing of the proposed adder circuit was carried out using the Testbench (VHDL language) and Verilog software products (additions are made to the end of section 2.4., highlighted in red).
Reviewer 3 Report
Comments and Suggestions for AuthorsThe paper presents an innovative approach to designing a processor that leverages the residue number system (RNS) and utilizes the first four quasi-Mersenne primes.The paper introduces a novel method for implementing a serial-parallel processor using RNS, which is a distinctive and interesting approach.The paper could benefit from improved clarity and organization, particularly in the sections describing the circuit diagram and operation of the adder. But there are some Weaknesses:
1.Limited Scope: The paper primarily focuses on a specific set of quasi-Mersenne primes and does not explore the broader applicability of the proposed approach to other sets of primes or different types of problems.
2.Lack of Comparative Analysis: There is no comparative analysis with existing processors or adder circuits to demonstrate the superiority or practical advantages of the proposed solution.
3.Clarity and Presentation: The paper could benefit from improved clarity and organization, particularly in the sections describing the circuit diagram and operation of the adder.
The authors should consider exploring the applicability of the proposed approach to other sets of primes and different types of computational problems，and provide a comparative analysis with existing processors and adder circuits to highlight the advantages and potential benefits of the proposed solution. The author should also improve the clarity and organization of the paper, particularly in the sections describing the circuit diagram and the operation of the adder.
I believe the paper has potential but requires significant revisions before it can be accepted for publication. I encourage the authors to address the weaknesses and suggestions outlined above to strengthen their work.
Author Response
The authors sincerely thank the reviewer for the positive feedback and valuable comments. In accordance with each of the comments made, the following corrections have been made to the text of the article.
1. Limited Scope: The paper primarily focuses on a specific set of quasi-Mersenne primes and does not explore the broader applicability of the proposed approach to other sets of primes or different types of problems.
The authors focused on the use of quasi-Mersenne primes, since they have quite definite advantages from the point of view of the prospects for developing calculators designed to perform digital convolution operations. The corresponding arguments are included in the text of the paper (highlighted in purple at the end of Section 2.1). The proposed approach, however, does allow generalization to the use of other sets of primes. Proofs of this, in accordance with the wishes of the reviewer, are also included in the text of the paper (highlighted in purple at the end of Section 2.3). The transition to other sets of primes is not associated with fundamental changes in the adder circuits proposed by us, but does not exclude the question of using specific Galois fields to solve specific problems.
2.Lack of Comparative Analysis: There is no comparative analysis with existing processors or adder circuits to demonstrate the superiority or practical advantages of the proposed solution.
The corresponding analysis is included in the text of the article, including references to patent literature (additions are made at the very beginning of section 2.3., highlighted in red).
3.Clarity and Presentation: The paper could benefit from improved clarity and organization, particularly in the sections describing the circuit diagram and operation of the adder. The authors should consider exploring the applicability of the proposed approach to other sets of primes and different types of computational problems，and provide a comparative analysis with existing processors and adder circuits to highlight the advantages and potential benefits of the proposed solution. The author should also improve the clarity and organization of the paper, particularly in the sections describing the circuit diagram and the operation of the adder.
The text of section 2.3, which describes the operation of the proposed scheme, has been reworked in accordance with the reviewer's comments (highlighted in red). Also presented are detailed proofs of the advantages of using RNSs built on the first quasi-Mersenne numbers compared to other RNSs (highlighted in purple).
Reviewer 4 Report
Comments and Suggestions for AuthorsThis is an article on the prospects of applying quasi-Mersenne numbers in computing, which involves a certain amount of work. There is still a need to further enhance the research and innovation within the article. Specific suggestions are as follows:
- The title "Prospects for the use of quasi-Mersen numbers in computing" may require a more specific description to reflect the specific content and contributions of the article. For example, it could more explicitly indicate the application of these numbers in the design of parallel-serial processors.
- The keywords section can be further refined to include more specific terms, such as "parallel-serial computing," "Residue Number System (RNS)," and "trigger adder," to more accurately describe the content of the article.
- The introduction section can be further expanded to provide more background information, including the historical application of quasi-Mersenne numbers in computing and the current research gaps, as well as why these specific numbers were chosen for study.
- When introducing the algorithm based on the Residue Number System (RNS), a more detailed description of the steps and theoretical foundations of the algorithm can be provided so that readers can better understand its working principle.
- The results section can include more charts and visual elements to help explain and demonstrate the performance and effects of the proposed adder circuit.
- It is recommended to pay attention to the size of the text characters in the figures of the paper, which should not exceed the size of the text characters in the main body by too much.
Minor editing of English language required.
Author Response
The authors sincerely thank the reviewer for the comments made. They have been taken into account in full. The responses to each of them are presented below.
1. The title "Prospects for the use of quasi-Mersen numbers in computing" may require a more specific description to reflect the specific content and contributions of the article. For example, it could more explicitly indicate the application of these numbers in the design of parallel-serial processors.
The title has been corrected in accordance with the reviewer's comments (highlighted in blue)
2. The keywords section can be further refined to include more specific terms, such as "parallel-serial computing," "Residue Number System (RNS)," and "trigger adder," to more accurately describe the content of the article.
Key words have been adjusted according to the reviewer's comments (highlighted in blue)
3. The introduction section can be further expanded to provide more background information, including the historical application of quasi-Mersenne numbers in computing and the current research gaps, as well as why these specific numbers were chosen for study.
The Introduction section has been significantly expanded in accordance with the reviewer's recommendations, in particular, it reflects a comparison of the specifics of Galois fields corresponding to Mersenne primes and quasi-Mersenne numbers (highlighted in blue).
4. When introducing the algorithm based on the Residue Number System (RNS), a more detailed description of the steps and theoretical foundations of the algorithm can be provided so that readers can better understand its working principle.
In accordance with the reviewer's comments, an additional section has been included in the text of the article ("Basic scheme of operation of the proposed type of calculators"), which describes in detail the theoretical foundations of the algorithm used (highlighted in blue).
5. The results section can include more charts and visual elements to help explain and demonstrate the performance and effects of the proposed adder circuit.
Additional testing of the proposed adder circuit was carried out using the Testbench (VHDL language) and Verilog software products (additions are made to the end of section 2.4., highlighted in red).
6. It is recommended to pay attention to the size of the text characters in the figures of the paper, which should not exceed the size of the text characters in the main body by too much.
The font sizes in the figures are given in accordance with the font size in the main text of the article.
Round 2
Reviewer 3 Report
Comments and Suggestions for AuthorsThe authors have made revisions based on the reviewers' comments. Although the revisions are not yet satisfactory, it is acceptable in this current state.
It is worth pointing out that there are more or less problems with the references, and the authors are requested to check and correct them article by article in accordance with the requirements of the journal.
Author Response
The authors sincerely thank the reviewer for the work done, the comments have been taken into account, the list of references has been brought into compliance with the requirements of the journal
Reviewer 4 Report
Comments and Suggestions for AuthorsMany problems in the thesis have been revised and improved, meeting the requirements for publication.
Author Response
The authors sincerely thank the reviewer for the work done. Due to the lack of explicit comments, but notes on the possibility of improving the background, the authors made additions to the discussion section (highlighted in red), which allow us to further demonstrate the significance of the work done.
