Design of Dual-Notch-Filter-Based Controllers for Enhancing the Dynamic Response of Universal Single-Phase Grid-Connected Power Converters

Abstract

Trade-off between transient response and grid-side current quality is a well-known issue of single-phase mains-connected power converters. A dual-loop control structure (usually based on PI or type-II controllers) is typically employed in such systems to regulate the DC link voltage to a constant reference (in order to maintain power balance) while forcing the grid-side current to have a specific shape (in order to comply with power quality requirements). Introducing notch term/s (tuned to certain multiple/s of the mains base frequency) into one of the loops allows either for the improvement of the dynamic performance without worsening the total harmonic distortion of grid-side current or for the enhancement of the current quality without impairing the dynamic response. Since the maximum tolerable value of total harmonic distortion is typically imposed by a certain power quality standard, it is desirable to enhance the transient response of the power converter system as much as possible while keeping the total harmonic distortion at the maximum allowed value. However, universal off-grid operating power conversion systems must support both 50 Hz and 60 Hz mains; consequently, tuning the notch term/s to 50 Hz multiple/s would not be sufficient for a 60 Hz mains operation and vice-versa. Consequently, this work examines the possibility of introducing a dual-notch term into the control loop in order to cover both above-mentioned base frequencies. It is demonstrated that under typical base frequency uncertainty values, the performances of dual-notch terms are nearly decoupled so that the term tuned to a 50 Hz frequency (and optionally to its multiples) has nearly no influence at a 60 Hz mains operation and vice-versa. Consequently, the methodology allows for the improvement of the dynamics of universal grid-connected power converters without total harmonic distortion (THD) deterioration. A stability analysis of the proposed control structure is carried out and quantitative design guidelines, allowing for the attainment of an optimized dynamic response for a given maximum tolerable total harmonic distortion, minimum allowed phase margin and a certain base frequency uncertainty, are established. It is shown that a DC link voltage loop bandwidth of 52 Hz may be attained while keeping the grid-side current THD below 5%. Simulations and experimental results support well the proposed design methodology.

1. Introduction

Mains-interfacing power conversion systems are typically obliged by power quality standards to interchange sinusoidal-shaped current with the utility grid [1,2,3]. As a result, alternating instantaneous power is exchanged between the two entities, formed by a DC component and a power component pulsating at twice the mains base frequency [4,5,6]. While the DC component is transferred to/from the load/source in order to carry the energy, the pulsating power constituent should not be allowed to reach the load/source to avoid lifetime reduction and excessive losses [7,8,9]. Consequently, DC link capacitors are typically employed to compensate instantaneous power mismatch between grid-side and load/source-side both in steady state and during transients [10,11,12]. This is accomplished by regulating the average DC link capacitor voltage (reflecting the stored energy) to a constant reference value employing a PI or type-2 compensator [13,14,15,16] without counteracting the pulsating power component. As a result, pulsating current flows through the DC link capacitor, giving rise to an uncontrolled DC link voltage ripple [17,18], which is proportional to the total power processed and inversely proportional to the DC link capacitance value and DC link voltage reference value [19,20]. Upon sensing the DC link voltage and feeding it back to the regulation loop, the ripple distorts the grid-side current magnitude reference signal (created by the loop compensator), leading to an increased total harmonic distortion (THD) of utility-side current [21,22]. In order to limit the THD, the gain of DC link voltage loop compensator should be restricted in the vicinity of double the base utility frequency [23], implying a trade-off between AC-side current THD and DC link voltage dynamics in case compensators with monotonically decreasing frequency response characteristics (e.g., PI or type-2) are employed [24,25,26]. Typically, around 10 Hz DC link voltage loop bandwidth is attained under 5% grid-side current THD restriction. Such a relatively low bandwidth imposes a high value of the required DC link capacitance in order to cope with sharp load-side power variations, since the DC link voltage value should always remain above the maximum of grid-side voltage to retain converter controllability [22,24].

Many solutions aiming to improve the trade-off have been suggested. Utilizing line voltage and/or load current feedforward to compensate against parameter variations does not increase the DC voltage loop bandwidth, yet it requires additional sensors [27,28,29,30]. The ripple estimation and cancellation techniques proposed in [31,32,33,34,35,36] indicated an improved performance, yet requiring a relatively complex circuitry and a significantly increased computational burden. The implementation of approaches based on nonlinear and/or time-varying control proposed in [37,38,39,40] call for a high-performance microcontroller. On the other hand, linear filtering-based methods proposed in [41,42,43,44,45,46,47] seem to be much simpler in terms of analysis and implementation. In particular, compensators combining a PI or type-II term with a notch filter may be easily realized either digitally or by a simple analog network. As mentioned above, the value of DC link voltage loop gain should be restricted in the vicinity of double the base utility frequency in order to limit the THD. A notch filter was combined with the current loop controller in [48] to enhance transient responses at both the DC bus voltage and the output current. Introducing a notch filter tuned to double the mains base frequency allows for local DC-link voltage loop gain minimization without restricting the corresponding PI or type-II controller gain, thus attaining an increased crossover frequency. Disturbance observer-based approaches, employing notch terms, were shown to yield a similar effect [49,50]. Design guidelines for obtaining PI + Notch controller coefficients based on the maximum tolerable grid-side current THD and transient DC link voltage deviation were established in [51].

Nevertheless, neither of the above-mentioned notch-filter-based solutions took into account the fact that a universal grid-connected converter must be capable of supporting both 50 Hz and 60 Hz grid frequencies. Moreover, utilizing transient DC link voltage deviation may yield non-optimal performance in terms of phase margin “overkill”. Recently, a disturbance observer-based approach [50] was extended to employ dual-notch-based action in [52], yet the methodology may only be applied to existing systems with slow PI or type-II controllers and cannot be employed in from-scratch designs. In addition, the control structures of disturbance observer-based methods are quite complex and not easy to implement.

Consequently, the main contributions of this work are as follows:

1.

It is suggested to combine a PI term with two notch filters, tuned to 50 Hz and 60 Hz, respectively, in order to support universal grid interfacing without the need for controller redesign.

2.

The minimum allowed phase margin is used as the second performance merit (along with the maximum tolerable grid-side current THD) rather than the maximum tolerable transient DC link voltage deviation. Such an approach allows the optimization of the latter rather than setting a desired value a priori (which may lead to a non-existing solution, requiring further iterations).

An explicit process of deriving coefficients of the proposed PI + N² controller employed for regulating the DC-link voltage of single-phase converters interfacing either 50 Hz or 60 Hz mains is proposed in this work. The proposed methodology allows for the optimization of the DC-link voltage transient caused by step-like load changes while attaining prescribed values of grid-side current THD and DC-link voltage loop phase margin under the prescribed mains frequency uncertainty range.

The rest of the paper is organized as follows. The essentials of single-phase grid-connected power conversion system operation are brought forward in Section 2. The steady-state performance of the system in terms of total harmonic distortion and its dynamic response in terms of DC-link voltage deviation upon step-like load variation are revealed analytically in Section 3 and Section 4, respectively. Guidelines for the proposed controller coefficient derivation are established in Section 5. The simulations and experiments of the proposed methodology applied to a 500 W grid-connected converter are demonstrated in Section 6. The paper is then concluded in Section 7.

2. Single-Phase Grid-Connected Power Conversion System

Consider a typical dual-stage off-grid operating power conversion system depicted in Figure 1a, formed by a mains-interfacing AC/DC converter and a downstream DC-DC converter, interconnected via a DC link capacitance C_DC. The grid is assumed to act as energy source in the subsequent discussion, yet the methodology remains valid in case the energy flows from the DC side to the AC side. Moreover, all the variables below are switching-cycle-average, i.e., free from switching components. Considering harmonic-free mains and unity power factor operation for brevity (yet without loss of generality), the grid-side voltage and current are given by [52]

$$\begin{array}{cc}{v}_G(t)=v_M(t)\sin \left({\displaystyle \int \omega (t)d}t\right),& i_G(t)=i_M(t)\sin \left({\displaystyle \int \omega (t)d}t\right)\end{array}$$

(1)

with ω denoting the instantaneous base frequency of the grid and v_M, i_M representing the corresponding magnitudes. In steady state, the above quantities are constant so that

$$\begin{array}{ccc}{v}_M(t)=V_M,& i_M(t)=I_M,& \omega (t)={\omega }_G.\end{array}$$

(2)

In steady state, the base frequency of the mains may attain the following values,

$${\omega }_G=\alpha \cdot \left\{\begin{array}{cc}100\mathsf{\pi },& 50\mathrm{Hz}\hspace{0.17em}mains\\ 120\mathsf{\pi },& 60\mathrm{Hz} mains\end{array}\right.$$

(3)

with α $\in$ [α_min < 1, α_max > 1] representing the corresponding deviation from nominal values (i.e., |1 − α| indicates the corresponding uncertainty). On the other hand, DC-side variables are also constant in steady state so that

$$\begin{array}{cc}{v}_L(t)=V_L,& i_L(t)=I_L.\end{array}$$

(4)

Assuming lossless conversion, a functional diagram of the power conversion system is shown in Figure 1b with

$$\begin{array}{ccc}{p}_L(t)=v_L(t)i_L(t),& p_G(t)=v_G(t)i_G(t),& v_{DC}(t)i_{DC}(t)=p_G(t)-p_L(t)\end{array},$$

(5)

where v_DC(t) and i_DC(t) represent the voltage across the DC link capacitance C_DC and the corresponding current, respectively. Combining (1) with (5) yields [10]

$$v_{DC}(t)i_{DC}(t)=v_{DC}(t)\underset{i_{DC}(t)}{\underbrace{C_{DC}\frac{d{v}_{DC}(t)}{dt}}}=0.5v_M(t)i_M(t)-0.5v_M(t)i_M(t)\cos \left(2{\displaystyle \int \omega (t)d}t\right)-v_L(t)i_L(t),$$

(6)

reducing in steady state to

$$C_{DC}{v}_{DC}^{ss}(t)\frac{d{v}_{DC}^{ss}(t)}{dt}=0.5V_M{I}_M-0.5V_M{I}_M\cos \left(2{\omega }_{G}t\right)-V_L{I}_L,$$

(7)

which may be split into

$$0.5V_M{I}_M=V_L{I}_L$$

(8)

and

$$C_{DC}{v}_{DC}^{ss}(t)\frac{d{v}_{DC}^{ss}(t)}{dt}=-0.5V_M{I}_M\cos \left(2{\omega }_{G}t\right),$$

(9)

respectively. Consequently, the steady-state expressions of grid-side current and DC link voltage are given by

$$\begin{array}{cc}{I}_M=\frac{2P_L}{V_M},& P_L=V_L{I}_L\end{array}$$

(10)

and

$$v_{DC}^{ss}(t)=V_{DC}^{*}\sqrt{1-\frac{P_L}{{\omega }_G{\left(V_{DC}^{*}\right)}^2{C}_{DC}}\sin \left(2{\omega }_{G}t\right)},$$

(11)

respectively, with $V_{DC}^{*}$ denoting the DC link voltage set point value. In practice,

$$\frac{P_L}{{\omega }_G{\left(V_{DC}^{*}\right)}^2{C}_{DC}}<<1$$

(12)

typically holds; hence, (11) may be further reduced to [11]

$$\begin{array}{ccc}{v}_{DC}^{ss}(t)\cong V_{DC}^{*}-\Delta v_{DC}(t),& \Delta v_{DC}(t)=\Delta V_{DC}\sin \left(2{\omega }_{G}t\right),& \Delta V_{DC}=\frac{P_L}{2{\omega }_G{V}_{DC}^{*}{C}_{DC}}\end{array}.$$

(13)

Consequently, steady-state DC link voltage would always be formed by the dominating DC component and the significantly smaller double-base-frequency pulsating ripple component, proportional to the load power and inversely proportional to the DC link capacitance, DC link voltage set point, and base frequency of the mains.

It must be emphasized that two typical realizations of the grid-interfacing AC/DC converter exist in practice. In case of unidirectional AC-to-DC power conversion, a grid-interfacing converter is often realized by a diode bridge rectifier followed by a boost DC-DC converter, as shown in Figure 1c. In case of DC-to-AC energy flow, the grid-interfacing converter operates as an inverter and should be realized in a bridgeless manner, e.g., as shown in Figure 1d. It should be mentioned, however, that unidirectional rectifiers may also be realized by bridgeless topology circuits. The corresponding control structures are depicted in Figure 2. In case a bridge-rectifier-based topology is utilized, all the measurements are taken at the DC side of the converter. The outer (voltage) loop regulates the DC link voltage by feeding the difference between the corresponding set point $V_{DC}^{*}$ and the measured value v_DC into the voltage controller C_V, which calculates the mains current magnitude value $I_M^{*}$ required to maintain the power balance (cf. (10)). On the other hand, the rectified mains voltage $\left|v_G\right|$ is sensed and the corresponding unity magnitude template $\left|sin\int \omega \left(t\right)dt\right|$ is extracted and multiplied by $I_M^{*}$ in order to generate the reference signal for the rectified grid-side current ${\left|i_G\right|}^{*}$. The inner (current) loop regulates the rectified grid-side current by feeding the difference between the corresponding reference ${\left|i_G\right|}^{*}$ and the measured value $\left|i_G\right|$ into the current controller C_I, which calculates the required modulating signal. The output of the PWM modulator is then fed to the switch of the boost DC-DC converter (cf. Figure 1c).

In case a bridgeless topology is utilized, grid-side measurements are required. While the outer (voltage) loop is similar to that of the bridge-rectifier-based topology, here the mains voltage v_G is sensed and the corresponding unity magnitude template $sin\int \omega \left(t\right)dt$ is extracted and multiplied by $I_M^{*}$ in order to generate the reference signal for the grid-side current $i_G^{*}$. The inner (current) loop regulates the grid-side current by feeding the difference between the corresponding reference $i_G^{*}$ and the measured value i_G into the current controller C_I, which calculates the required modulating signal. The outputs of the PWM modulator are then fed to the switches of the AC/DC converter (cf. Figure 1d).

It was shown in [53] that the attainable bandwidth ω_CI of a typical current loop is given by

$${\omega }_{CI}\cong \frac{0.5\mathsf{\pi }-P{M}_I^{*}}{T_d},$$

(14)

where ${PM}_I^{*}$ is the desired phase margin of the current loop and T_d is the total switching and sampling delay, the worst case of which equals 1.5 times the sampling period. Considering the typical values of ${PM}_I^{*}=\frac{\mathsf{\pi }}{4}$ and switching frequency of 50 kHz, the attainable current loop bandwidth would be $2\mathsf{\pi }·$4167 rad/s, which is about two decades higher than the attainable voltage loop bandwidth. Consequently, it may be assumed that

$$\begin{array}{cc}{i}_G(t)=i_G^{*}(t),& \left|i_G(t)\right|={\left|i_G(t)\right|}^{*}\end{array}$$

(15)

with a high degree of accuracy. Noticing that

$$v_G(t)i_G(t)=\left|v_G(t)\right|\left|i_G(t)\right|=p_G(t).$$

(16)

holds for (1) and combining (15) with (6) while taking Figure 1b and Figure 2 into account, the corresponding simplified closed-loop system representations are depicted in Figure 3 [51].

In this paper, the controller C_V is realized by a cascaded proportional-integral–dual-notch (PI + N²) structure

$$C_V(s)=\underset{PI(s)}{\underbrace{K\frac{\tau s+1}{s}}}\cdot \underset{N^2(s)}{\underbrace{\underset{N{F}_1(s)}{\underbrace{\frac{s^2+{\left(200\mathsf{\pi }\right)}^2}{s^2+2{\xi }_f\left(200\mathsf{\pi }\right)s+{\left(200\mathsf{\pi }\right)}^2}}}\cdot \underset{N{F}_2(s)}{\underbrace{\frac{s^2+{\left(240\mathsf{\pi }\right)}^2}{s^2+2{\xi }_f\left(240\mathsf{\pi }\right)s+{\left(240\mathsf{\pi }\right)}^2}}}}}$$

(17)

with 0 ≤ ξ_f ≤ 1, proposed by the authors in [54]. There are three parameters to be determined (namely K, τ and ξ_f) according to the desired phase margin of the voltage loop ${PM}_V^{*}$, the maximum tolerable total harmonic distortion value THD* and the expected deviation of base frequencies from their nominal values α.

3. Total Harmonic Distortion

According to (10), (13) and Figure 3, there is

$$I_M^{*}=\frac{2P_L}{V_M}-\Delta V_{DC}\left|C_V\left(2{\omega }_G\right)\right|\sin \left(2{\omega }_{G}t+\arg C_V\left(2{\omega }_G\right)\right)$$

(18)

in steady state. Consequently (cf. (15)), there is

$$\left|i_G(t)\right|=I_M^{*}\left|\sin {\omega }_{G}t\right|=\frac{2P_L}{V_M}\left(1-\frac{V_M\Delta V_{DC}}{2P_L}\left|C_V\left(2{\omega }_G\right)\right|\sin \left(2{\omega }_{G}t+\arg C_V\left(2{\omega }_G\right)\right)\right)\left|\sin {\omega }_{G}t\right|$$

(19)

in case of a diode bridge-based rectifier. If

$$\frac{V_M\Delta V_{DC}}{2P_L}\left|C_V\left(2{\omega }_G\right)\right|<<1$$

(20)

then (19) implies grid current [51]

$$\begin{array}{l}{i}_G(t)=\frac{2P_L}{V_M}\left(1-\frac{V_M\Delta V_{DC}}{2P_L}\left|C_V\left(2{\omega }_G\right)\right|\sin \left(2{\omega }_{G}t+\arg C_V\left(2{\omega }_G\right)\right)\right)\sin {\omega }_{G}t\\ =\frac{2P_L}{V_M}\left(\begin{array}{l}\sin {\omega }_{G}t+\frac{V_M\Delta V_{DC}}{4P_L}\left|C_V\left(2{\omega }_G\right)\right|\cos \left({\omega }_{G}t+\arg C_V\left(2{\omega }_G\right)\right)-\\ -\frac{V_M\Delta V_{DC}}{4P_L}\left|C_V\left(2{\omega }_G\right)\right|\sin \left(3{\omega }_{G}t+\arg C_V\left(2{\omega }_G\right)\right)\end{array}\right),\end{array}$$

(21)

formed by the first and the third harmonic components only. Note that (21) also holds in the case of bridgeless grid-interfacing converter implementation. Consequently, the grid-side current THD is given by (cf. (20))

$$THD\cong \frac{V_M\Delta V_{DC}}{4P_L}\left|C_V\left(2{\omega }_G\right)\right|.$$

(22)

Furthermore, (20) may be reformulated as

$$2\cdot THD<<1,$$

(23)

which is typically true since THD values of 5% and below are typically considered. Hence, (20) is justified and (21) is a valid approximation.

It may be concluded from (21) that the pulsating ripple component of the DC link voltage (13) imposes a non-zero grid-side current THD. Denoting the maximum tolerable THD value as THD*, the combination of (13) and (21) yields the following constraint

$$\frac{V_M}{8{\omega }_G{V}_{DC}^{*}{C}_{DC}}\left|C_V\left(2{\omega }_G\right)\right|=TH{D}^{*}\Rightarrow \left|C_V\left(2{\omega }_G\right)\right|=\frac{4\left(2{\omega }_G\right)V_{DC}^{*}{C}_{DC}}{V_M}TH{D}^{*},$$

(24)

which must be satisfied within the region given by the following union (cf. (3))

$$\left(2{\alpha }_{\min }\cdot 100\mathsf{\pi }\le 2{\omega }_G\le 2{\alpha }_{\max }\cdot 100\mathsf{\pi }\right)\cup \left(2{\alpha }_{\min }\cdot 120\mathsf{\pi }\le 2{\omega }_G\le 2{\alpha }_{\max }\cdot 120\mathsf{\pi }\right).$$

(25)

Considering (23) with (17) yields

$$\begin{array}{l}K\frac{\sqrt{{\left(2{\omega }_G\tau \right)}^2+1}}{2{\omega }_G}\times \\ \frac{{\left(200\mathsf{\pi }\right)}^2-{\left(2{\omega }_G\right)}^2}{\sqrt{{\left({\left(200\mathsf{\pi }\right)}^2-{\left(2{\omega }_G\right)}^2\right)}^2+{\left(4{\omega }_G{\xi }_f\left(200\mathsf{\pi }\right)\right)}^2}}\frac{{\left(240\mathsf{\pi }\right)}^2-{\left(2{\omega }_G\right)}^2}{\sqrt{{\left({\left(240\mathsf{\pi }\right)}^2-{\left(2{\omega }_G\right)}^2\right)}^2+{\left(4{\omega }_G{\xi }_f\left(240\mathsf{\pi }\right)\right)}^2}}\\ =\frac{4\left(2{\omega }_G\right)V_{DC}^{*}{C}_{DC}}{V_M}TH{D}^{*}.\end{array}$$

(26)

Combining (26) with (3) leads to

$$\begin{array}{l}\begin{array}{cc}\begin{array}{l}K\frac{\sqrt{{\left(2{\omega }_G\tau \right)}^2+1}}{2{\omega }_G}\times \\ \frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\alpha }^2}{{\left(1-{\alpha }^2\right)}^2}}}\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\left(\frac{5}{6}\alpha \right)}^2}{{\left(1-{\left(\frac{5}{6}\alpha \right)}^2\right)}^2}}}=\frac{4\left(2{\omega }_G\right)V_{DC}^{*}{C}_{DC}}{V_M}TH{D}^{*},\end{array}& {\omega }_G=\alpha 100\mathsf{\pi }\end{array}\\ \begin{array}{cc}\begin{array}{l}K\frac{\sqrt{{\left(2{\omega }_G\tau \right)}^2+1}}{2{\omega }_G}\times \\ \frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\alpha }^2}{{\left(1-{\alpha }^2\right)}^2}}}\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\left(\frac{6}{5}\alpha \right)}^2}{{\left(1-{\left(\frac{6}{5}\alpha \right)}^2\right)}^2}}}=\frac{4\left(2{\omega }_G\right)V_{DC}^{*}{C}_{DC}}{V_M}TH{D}^{*},\end{array}& {\omega }_G=\alpha 120\mathsf{\pi }\end{array}\end{array}$$

(27)

unified as

$$K\frac{\sqrt{{\left(2{\omega }_G\tau \right)}^2+1}}{2{\omega }_G}f\left(\alpha \right)=\frac{4\left(2{\omega }_G\right)V_{DC}^{*}{C}_{DC}}{V_M}TH{D}^{*}$$

(28)

with

$$f\left(\alpha \right)=\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\alpha }^2}{{\left(1-{\alpha }^2\right)}^2}}}\cdot \left\{\begin{array}{cc}\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\left(\frac{5}{6}\alpha \right)}^2}{{\left(1-{\left(\frac{5}{6}\alpha \right)}^2\right)}^2}}},& {\omega }_G=\alpha 100\mathsf{\pi }\\ \frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\left(\frac{6}{5}\alpha \right)}^2}{{\left(1-{\left(\frac{6}{5}\alpha \right)}^2\right)}^2}}},& {\omega }_G=\alpha 120\mathsf{\pi }\end{array}\right.$$

(29)

denoting the multiplication of tuned and un-tuned notch term gains, respectively. Plots of f(α) versus 0.99 ≤ α ≤ 1.01 (signifying 1% mains frequency uncertainty) are depicted in Figure 4 for different values of ξ_f. As expected, the gain of the notch term is zero at nominal frequency (theoretically implying THD = 0), increasing with detuning. Moreover, the highest total f(α) is attained at α_min for 50 Hz mains and at α_max for 60 Hz mains. Nevertheless, since the magnitude response of the PI term in (17) monotonically decreases until the effect zero begins to kick in, the gain at ω_G = α_min∙100π may be expected as the worst case one. In addition, it is well-evident that increasing ξ_f improves robustness to frequency variations. It should be emphasized that if ξ_f = 0 is selected, the control structure in (17) reduces to the typical PI regulator.

4. Dynamic Response

Reformulating (6) as

$$C_{DC}{v}_{DC}(t)\frac{d{v}_{DC}(t)}{dt}=0.5v_M(t)i_M(t)-p_L(t)-\underset{p_2(t)}{\underbrace{0.5v_M(t)i_M(t)\cos \left(2{\displaystyle \int \omega (t)d}t\right)}}$$

(30)

and linearizing around the operating point by substituting

$$\begin{array}{c}\begin{array}{ccc}{v}_{DC}(t)=V_{DC}^{*}+{\tilde{v}}_{DC}(t),& i_M(t)=\frac{2P_L}{V_M}+{\tilde{i}}_M(t),& v_M(t)=V_M+{\tilde{v}}_M(t),\end{array}\\ \begin{array}{cc}{p}_L(t)=P_L+{\tilde{p}}_L(t),& p_2(t)=P_L\cos \left(2{\omega }_{G}t\right)+{\tilde{p}}_2(t),\end{array}\end{array}$$

(31)

into (31) and neglecting high-order small-signal terms yields

$$C_{DC}{V}_{DC}^{*}\frac{d{\tilde{v}}_{DC}(t)}{dt}=0.5V_M{\tilde{i}}_M(t)+\frac{P_L}{V_M}{\tilde{v}}_M(t)-{\tilde{p}}_L(t)-{\tilde{p}}_2(t).$$

(32)

The resultant control structure is depicted in Figure 5 [22].

The corresponding loop gain is obtained as

$$\begin{array}{l}L(s)=\frac{0.5V_M}{C_{DC}{V}_{DC}^{*}s}{C}_V(s)=\\ \frac{0.5V_{M}K}{C_{DC}{V}_{DC}^{*}}\frac{\tau s+1}{s^2}\frac{s^2+{\left(200\mathsf{\pi }\right)}^2}{s^2+2{\xi }_f\left(200\mathsf{\pi }\right)s+{\left(200\mathsf{\pi }\right)}^2}\frac{s^2+{\left(240\mathsf{\pi }\right)}^2}{s^2+2{\xi }_f\left(240\mathsf{\pi }\right)s+{\left(240\mathsf{\pi }\right)}^2}=\\ {\omega }_n^2\frac{2\frac{{\xi }_n}{{\omega }_n}s+1}{s^2}N{F}_1(s)N{F}_2(s), {\omega }_n=\sqrt{\frac{0.5K{V}_M}{C_{DC}{V}_{DC}^{*}}}, {\xi }_n={\omega }_n\frac{\tau }{2}.\end{array}$$

(33)

Denoting the crossover frequency of the voltage loop as ω_CV, the corresponding phase and gain contributions of the notch terms are given by

$$\begin{array}{c}\begin{array}{cc}\arg N{F}_1({\omega }_{CV})=-{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}}\right),& \arg N{F}_2({\omega }_{CV})=-{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{240\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{240\mathsf{\pi }}}\right),\end{array}\\ \begin{array}{cc}\left|N{F}_1({\omega }_{CV})\right|=\sqrt{\frac{1}{1+\frac{4{\xi }_f^2}{{\left(\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}\right)}^2}}},& \left|N{F}_2({\omega }_{CV})\right|=\sqrt{\frac{1}{1+\frac{4{\xi }_f^2}{{\left(\frac{240\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{240\mathsf{\pi }}\right)}^2}}},\end{array}\end{array}$$

(34)

respectively. The Bode diagram of dual-notch term NF₁(s)∙NF₂(s) is depicted in Figure 6 for different values of ξ_f and ω < 200π (since ω_CV < 200π in practice). It is well-evident that increasing the value of ξ_f escalates both the phase and gain contributions of the dual-notch term.

It is well-evident that the gain contribution may be neglected within the whole frequency range considered, thus

$$\left|L({\omega }_{CV})\right|\cong \frac{{\omega }_n^2}{{\omega }_{CV}^2}\sqrt{\left(2{\xi }_n\frac{{\omega }_{CV}}{{\omega }_n}\right)+1}=1$$

(35)

should be satisfied at the crossover frequency ω_CV, yielding the crossover frequency

$${\omega }_{CV}=\underset{{\theta }_n}{\underbrace{{\xi }_n\sqrt{2+2\sqrt{1+\frac{1}{4{\xi }_n^4}}}}}{\omega }_n={\theta }_n{\omega }_n.$$

(36)

On the other hand, the phase contribution in (34) must be taken into account, imposing

$$\begin{array}{l}\arg \left(L({\omega }_{CV})\right)=\\ t{g}^{-1}\left(2{\xi }_n\frac{{\omega }_{CV}}{{\omega }_n}\right)-{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}}\right)-{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{240\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{240\mathsf{\pi }}}\right)-\mathsf{\pi }=-\mathsf{\pi }+P{M}_V^{*}\end{array}$$

(37)

at the crossover frequency with ${PM}_V^{*}$ indicating the desired voltage loop phase margin. Solving (37) with (36), there is

$$\begin{array}{cc}{\xi }_n={\left(\frac{{\left(\frac{tg\left(P{M}_V^{*}+\beta \right)}{2\sqrt{2}}\right)}^4}{2{\left(\frac{tg\left(P{M}_V^{*}+\beta \right)}{2\sqrt{2}}\right)}^2+\frac{1}{4}}\right)}^{\frac{1}{4}},& \beta ={\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}}\right)+{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{240\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{240\mathsf{\pi }}}\right)\end{array}.$$

(38)

Note that β in (38) may be approximated for simplicity (with some safety margin) as

$$\beta \cong 2{\tan }^{-1}\left(\frac{2{\xi }_f}{\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}}\right),$$

(39)

hence, in order to minimize it, ${\xi }_f$ should satisfy

$${\xi }_f<<\frac{1}{2}\left(\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}\right).$$

(40)

Setting ${\xi }_f$ to

$${\xi }_f=\frac{1}{2}\lambda \left(\frac{200\mathsf{\pi }}{{\omega }_{CV}}-\frac{{\omega }_{CV}}{200\mathsf{\pi }}\right),$$

(41)

and substituting into (39), there is

$$\begin{array}{cc}\beta \cong 2{\tan }^{-1}\left(\lambda \right)\approx 2\lambda ,& \lambda <<1.\end{array}$$

(42)

In order to bound β by β_max degrees, λ should be set to

$$\lambda =\frac{1}{2}\tan \left({\beta }_{\max }\right)$$

(43)

and ${PM}_V^{*}$ increased by β_max degrees to compensate for β. For the value of β_max = 5° recommended in [51], λ = 0.0437 should be selected. In case ${\xi }_f$ is bounded according to (40), ${\xi }_n$ and ${\theta }_n$ are presented graphically versus the typical range of the desired voltage loop phase margin values in Figure 7 and Figure 8, respectively. It may be concluded that both parameters increase with the rise in ${PM}_V^{*}$. In addition, the crossover frequency ω_CV is always higher than ω_n for the practical values of the desired voltage loop phase margin.

In practice, the variations of grid voltage magnitude and frequency are slower with respect to the voltage loop time constant. Consequently, a critical transient response is the one caused by load power variations. The corresponding transfer function of interest may be derived from Figure 5 (neglecting the influence of the dual notch term) as

$$\begin{array}{cc}{\left.\frac{{\tilde{v}}_{DC}(s)}{{\tilde{p}}_L(s)}\right|}_{p_2(t)=0}\approx -G_n\frac{s}{s^2+2{\xi }_n{\omega }_{n}s+{\omega }_n^2},& G_n=\frac{1}{C_{DC}{V}_{DC}^{*}}\end{array}.$$

(44)

Therefore, the load power step of ΔP_L imposes a DC link voltage perturbation expressed as

$${\left.{\tilde{v}}_{DC}(s)\right|}_{p_2(s)=0}=-\frac{G_n\Delta P_L}{s^2+2{\xi }_n{\omega }_{n}s+{\omega }_n^2}\Rightarrow {\left.{\tilde{v}}_{DC}(t)\right|}_{p_2(t)=0}=-\frac{G_n\Delta P_L}{{\omega }_n\sqrt{1-{\xi }_n^2}}{e}^{-{\xi }_n{\omega }_{n}t}\sin \left({\omega }_n\sqrt{1-{\xi }_n^2}t\right).$$

(45)

On the other hand, the contribution of p₂(t) is given by Δv_DC(t) in (13). Consequently, the total DC link voltage deviation may be approximated by

$$\begin{array}{l}{\tilde{v}}_{DC}(t)={\left.{\tilde{v}}_{DC}(t)\right|}_{p_2(t)=0}+\Delta v_{DC}(t)=\\ -\frac{G_n\Delta P_L}{{\omega }_n\sqrt{1-{\xi }_n^2}}{e}^{-{\xi }_n{\omega }_{n}t}\sin \left({\omega }_n\sqrt{1-{\xi }_n^2}t\right)-\frac{\Delta P_L}{2{\omega }_G{V}_{DC}^{*}{C}_{DC}}\sin \left(2{\omega }_{G}t\right),\end{array}$$

(46)

bounded by

$$\begin{array}{l}{\tilde{v}}_{DC}(t)=v_{DC}(t)-V_{DC}^{*}\ge \\ \max \left({\left.{\tilde{v}}_{DC}(t)\right|}_{p_2(t)=0}\right)+\max \left(\Delta v_{DC}(t)\right)=-\frac{\Delta P_L}{V_{DC}^{*}{C}_{DC}}\left(\frac{1}{{\omega }_n}{e}^{-\frac{{\xi }_n{\cos }^{-1}{\xi }_n}{\sqrt{1-{\xi }_n^2}}}+\frac{1}{2{\omega }_G}\right).\end{array}$$

(47)

Since the value of ${\xi }_n$ is dictated solely by ${PM}_V^{*}+\beta$_max (cf. (38)), the total DC link voltage deviation is reduced when ${\omega }_n$ is increased. Since ${\omega }_n$ is proportional to ω_CV (cf. (37)) for a given ${PM}_V^{*}$, increasing ${\omega }_n$ is equivalent to increasing the voltage loop bandwidth. Moreover, the right-hand side within the brackets of (46) implies that ω_G = α_min∙100π would also be the worst case in terms of contribution to the DC link voltage deviation. It should be recalled that in an earlier work [51], the desired undershoot value rather than the minimal tolerable phase margin was used as a performance merit, yielding excessive stability at the expense of a larger DC link voltage overshoot. Here, a minimal tolerable phase margin is imposed, yielding an improved DC link voltage undershoot, as shown next.

5. Controller Parameters Selection

Combining (28) with (33) and solving while considering the worst-case grid frequency ω_G = α_min∙100π yields

$${\omega }_n=\sqrt{8}{\xi }_n{\alpha }_{\min }100\mathsf{\pi }\sqrt{\sqrt{1+\frac{{\left(TH{D}^{*}\right)}^2}{{\xi }_n^4{f}^2\left({\alpha }_{\min }\right)}}-1}.$$

(48)

with

$$f\left({\alpha }_{\min }\right)=\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\alpha }_{\min }^2}{{\left(1-{\alpha }_{\min }^2\right)}^2}}}\frac{1}{\sqrt{1+4{\xi }_f^2\frac{{\left(\frac{5}{6}{\alpha }_{\min }\right)}^2}{{\left(1-{\left(\frac{5}{6}{\alpha }_{\min }\right)}^2\right)}^2}}}.$$

(49)

As mentioned at the end of the preceding section, ${\omega }_n$ should be maximized in order to optimize the transient response (i.e., minimize the DC link voltage deviation). According to (43), this implies minimizing the value of f(α) since ${\xi }_n$ is dictated solely by ${PM}_V^{*}$+ β_max. However, this conclusion contradicts the one drawn in Section 3, where the opposite was required in order to improve the steady-state performance. Consequently, the trade-off between steady-state and dynamic performances remains and the proposed methodology aims to improve it but not eliminate it. According to (36) and (48), the crossover frequency is then given by

$${\omega }_{CV}={\theta }_n\sqrt{8}{\xi }_n{\alpha }_{\min }100\mathsf{\pi }\sqrt{\sqrt{1+\frac{{\left(TH{D}^{*}\right)}^2}{{\xi }_n^4{f}^2\left({\alpha }_{\min }\right)}}-1}.$$

(50)

Substituting (50) into (41) and rearranging, there is

$$\begin{array}{l}{\xi }_f=\\ \frac{1}{2}\lambda \left(\frac{1}{{\theta }_n\sqrt{2}{\xi }_n{\alpha }_{\min }\sqrt{\sqrt{1+\frac{{\left(TH{D}^{*}\right)}^2}{{\xi }_n^4{f}^2\left({\alpha }_{\min }\right)}}-1}}-{\theta }_n\sqrt{2}{\xi }_n{\alpha }_{\min }\sqrt{\sqrt{1+\frac{{\left(TH{D}^{*}\right)}^2}{{\xi }_n^4{f}^2\left({\alpha }_{\min }\right)}}-1}\right).\end{array}$$

(51)

Since ${\theta }_n$ and ${\xi }_n$ are known from (36) and (38), solving (51) with (49) yields the value of ${\xi }_f$. Then, ${\omega }_n$ is obtained from (48) and the coefficients of the PI controller term in (17) are obtained as (cf. (33))

$$\begin{array}{cc}K=\frac{2C_{DC}{V}_{DC}^{*}}{V_M}{\omega }_n^2,& \tau =2\frac{{\xi }_n}{{\omega }_n}.\end{array}$$

(52)

The proposed process of controller coefficient tuning is then summarized as follows:

1.

Initialize β_max and${PM}_V^{*}$.

2.

Obtain ${\theta }_n$ using (36), ξ_n using (38) and λ using (43).

3.

Initialize THD* and α_min.

4.

Obtain ξ_f using (51) and ω_n using (48).

5.

Initialize V_M, C_DC and $V_{DC}^{*}$.

6.

Determine K and τ using (52).

7.

Verify the design by Bode diagram.

8.

Release requirement/s and iterate if necessary.

6. Example and Validation

Consider a bidirectional 500 W single-phase grid-connected converter shown in Figure 9 (the downstream DC-DC converter is represented by the power load element p_L [55]) operating at a switching frequency of 30 kHz with L = 3.5 mH. The value of the DC link capacitance was set to $C_{DC}=385 \mathsf{\mu }\mathrm{F}$ [22] and the DC link voltage set point was selected as $V_{DC}^{*}=400 \mathrm{V}$ [51]. The desired performance merit pair was selected as THD* = 0.05, ${PM}_V^{*}$ = 40°. The grid frequency uncertainty was assumed to be 1%, i.e., α $\in$ [α_min = 0.99, α_max = 1.01] were considered for both 50 Hz and 60 Hz mains and the corresponding magnitude was set to V_M = 325 V. According to the process of controller coefficient tuning proposed in the previous section:

1.

β = 7.5° and ${PM}_V^{*}$ = 40° + 7.5°.

2.

${\theta }_n$ = 1.2, ξ_n = 0.45 and λ = 0.066.

3.

THD* = 0.05 and α_min = 0.99.

4.

ξ_f = 0.047 and ω_n = 2π∙45 rad/s.

5.

V_M = 325 V, C_DC = $385 \mathsf{\mu }\mathrm{F}$ and $V_{DC}^{*}$ = 400 V.

6.

K = 76 and τ = 0.0032.

Figure 9. Grid-interfacing converter under study.

Figure 9. Grid-interfacing converter under study.

The resulting Bode diagram of the DC link voltage loop gain (cf. (33)) is depicted in Figure 10, indicating a crossover frequency of ω_CV = 2π∙52 rad/s and a phase margin of 39.2° in accurate agreement with ${PM}_V^{*}$ = 40°.

It is interesting to compare the expected performance to the one demonstrated in [51]. Here, voltage deviation of ~10 V is expected (cf. (47)) under a 40° phase margin. On the other hand, a DC link deviation of 20 V was attained in [51] under a 58° phase margin. It may be then concluded that imposing a minimal tolerable phase margin yields an optimized DC link voltage deviation, as stated at the end of Section 4.

6.1. Simulations

During simulations (PSIM 2022 software), the transient responses of the DC link voltage and grid-side current to a zero-to-rated power step-like load variation, and the corresponding steady-state performance under the proposed control methodology were evaluated. The results are depicted in Figure 11 and Figure 12 for 50 Hz and 60 Hz mains, respectively.

It may be concluded that the system operates as expected under the proposed methodology in terms of dynamic response (a ~10 V DC link voltage deviation is evident irrespectively of mains frequency). As to the grid-side current quality,

Table 1. PSIM-measured THD in simulations.

ωG/2π	49.5 Hz	50 Hz	50.5 Hz	59.4 Hz	60 Hz	60.6 Hz
THD%	5	0.1	4.52	3.98	0.067	3.68

summarizes the corresponding steady-state THD values. It is evident that the system designed according to the proposed approach complies well with THD* at ω_G = α_min∙100π. Moreover, the THD attains near-zero values at the nominal values of the mains frequency, as predicted above.

6.2. Experiments

In order to validate the proposed methodology experimentally, a modified Texas Instruments High Voltage Single Phase Inverter Kit [56] (Figure 13) was utilized.

The control algorithm was realized adopting first-order hold digitization [57] by a TMS320F28335 DSP-based control card under an average-current-controlled inner loop. The utility was emulated by an APS-7100 Gw Instek programmable AC power source operating as 50 Hz/60 Hz $\pm 1\%$, 230V_rms sinusoidal voltage source. The M9715B Maynuo DC electronic load functioning in constant power mode was employed to emulate the power load p_L (cf. Figure 9).

During the simulation framework, it was shown that frequency variations have a negligible influence on the shape of transient responses; hence, the latter were recorded for nominal mains frequency values only. The corresponding results are depicted in Figure 14, matching well the corresponding simulation results demonstrating ~10 V DC link deviations upon a step-like load variation.

The steady-state performance under a rated load around 50 Hz and 60 Hz mains is demonstrated in Figure 15 and Figure 16, respectively. Prior to the experimental framework, the AC power source voltage THD was measured and found to be 0.5%, as shown in Figure 9 in [22]. This value should be taken into account in order to correctly interpret the measured values of THD_i.

Table 2. Scope-measured THD in experiments.

ωG/2π	49.5 Hz	50 Hz	50.5 Hz	59.4 Hz	60 Hz	60.6 Hz
THD	0.0535	0.0261	0.053	0.0528	0.0212	0.046

summarizes the corresponding steady-state THD values. It is evident that the system designed according to the proposed approach complies well with THD*.

7. Conclusions

A method for deriving the coefficients of a proportional-integral and dual-notch controller employed for regulating the DC link voltage of single-phase converters interfacing either 50 Hz or 60 Hz mains was proposed in this work. The suggested approach allows for the optimization of the DC link voltage transient caused by step-like load changes while attaining the prescribed values of the grid-side current total harmonic distortion and the DC link voltage loop phase margin under a certain uncertainty range of mains frequency. An explicit process of controller coefficient tuning was established and successfully validated both by simulations and experimentally. It was shown that the 50 Hz and 60 Hz notch terms are nearly decoupled in frequency domain, allowing the proposed methodology to attain an approximate 5-fold increase in the DC link voltage loop crossover frequency compared to the classical PI control under a 5% grid-side current THD restriction, a 45° phase margin and a 1% grid frequency uncertainty. Future work on the subject will focus on distorted grid interfacing (calling for multi-dual-notch-based control structure) and examining the advantages of replacing the PI term of the controller with a type-II regulator. It is expected that the additional degree of freedom inherent in the type-II regulator may further improve the trade-off between steady-state and transient converter behavior. Moreover, multi-dual-notch-based control structures may give rise to stability issues which must be identified and appropriately resolved.