# Bit Streaming Processing Algorithms for Intelligent Hardware Converters

^{*}

## Abstract

**:**

## 1. Introduction

- Pulses in the bit stream are of equivalent weight; therefore, the bit stream conversion is highly reliable. Loss of one pulse in the stream is equivalent to loss of the least significant bit of the binary code, while loss of one bit in the code can lead to loss of value equal to 2
^{i}, where i stands for the lost bit position. - The usage of single wire instead of multi-bit buses simplifies data transmission between the endpoints and the computational cores of the systems.
- Measurement and calculation processes can be easily parallelized.
- The presence of pauses between pulses in the stream reduces the average power consumption that implies high energy efficiency.

## 2. Materials and Methods

- Pulse frequency sweep (PFS);
- Pulse-width sweep (PWS).

#### 2.1. Bit-Stream Multiplication Process

_{1}, with the stream PWM generated from N

_{2}(block 5). This interrupt provides streams multiplication and allows us to implement the following operation: ${\mathrm{N}}_{\mathrm{out}2}={\mathrm{N}}_{1}{\mathrm{N}}_{2}$ (block 8). The P3 stream is the result of interrupting the stream based on the N

_{1}code by a stream of inverted PWM pulses. Such an interrupt implements the multiplication by inverted code $\overline{{\mathrm{N}}_{2}}$:${\mathrm{N}}_{\mathrm{out}3}={\mathrm{N}}_{1}\overline{{\mathrm{N}}_{2}}$ (block 9).

#### 2.2. Process of Calculating of the Bit-Stream Multiplication-Division Function

## 3. Results

#### 3.1. Bit-Stream Algorithms

_{i}is incremented by 1, and ${\mathrm{N}}_{\mathrm{binc}}$ code is formed.

_{i}.

^{n}t

_{i}, where t

_{i}is the time interval determined frequency of the process quantization. The description of the computational process is based on the time interval t

_{i}, chosen as the unit time, and then in relative units T = 2

^{n}. The number of time samples t

_{i}per period T is denoted as ${\mathrm{X}}_{\mathrm{t}}$.

_{i}per period can be any number. By taking ${\mathrm{X}}_{{\mathrm{t}}_{1}}={2}^{\mathrm{n}}$, this simplifies the mathematical description of the process but does not change its essence. Formula (2) can be written as follows:

^{n}cycles of the work of multiplication-division algorithm, the output code is defined as follows:

#### 3.2. Algorithm Implementation

_{clk}as well as the changing input code Nk. The function $urandom_range is used to generate the input code in a bit grid i; the frequency of code Nk changing during the test is f

_{clk}/(3 × 2

^{i}).

- two code-to-PWM converters performing the conversion of ${\mathrm{N}}_{2}$ and ${\mathrm{N}}_{3}$ codes into a stream of PWM signals; they implement the operations of blocks 2 and 6 of the Figure 3 algorithm and can be implemented by known methods, for example, using counters;
- two «&» elements performing multiplication of bit stream by PWM signal (blocks 3 and 7 of the Figure 3 algorithm);
- increment/decrement counter, which counts the pulses generated in the positive and negative branches of the unit (blocks 4 and 8 of the Figure 3 algorithm).

_{1}, N

_{2}and N

_{3}were formed using the function $urandom_range. The frequency of change of input codes was chosen so that on the time diagram we could observe the transient process when the device tends to an equilibrium state, as well as the process of holding the stable state.

_{1}is converted into a pulse stream (line MDU_tst/i1/F_plus). The codes N

_{2}and N

_{3}are converted into PWM signal streams (line MDU_tst/i1/PWM_Active2 and MDU_tst/i1/PWM_Active3). Figure 6a shows the transient where the resulting signal (MDU_tst/i1/r_count) increases on each cycle, coming closer to the result. The corresponding pulse stream becomes more intense on each cycle (MDU_tst/i1/F_minus). At the digital output (MDU_tst/i1/N_out), the data is fixed at the end of each period; this allows for a stable output code value during the period.

_{1}= 120, N

_{2}= 60, and N

_{3}= 30, the result Nout = 240.

#### 3.3. Application of the Developed Modules

_{max}for the bit-parallel method was 35.94 MHz. For the bit-stream method, the maximum frequency was 111.73 MHz, but the processing period was related to the bit rate, and for the 10-bit device version the frequency was defined as f

_{max}/2

^{10}, or 109 kHz.

## 4. Discussion

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Conflicts of Interest

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**Figure 1.**The scheme of the parallel bit-stream process: (

**a**) multiplication process; (

**b**) multiplication-division process.

**Figure 6.**Result of multiplication-division algorithm simulation: (

**a**) transition process and (

**b**) the process of tracking the result in a state of equilibrium.

**Figure 7.**The cholinesterase activity analyzer: (

**a**) exterior view of analyzer; (

**b**) sensor installation; (

**c**) temperature control using the proposed implementation and using mercury thermometers.

N_{b} | N_{binc} | P_{ν}_{0} | P_{ν}_{1} | P_{ν}_{2} | P_{ν}_{3} |
---|---|---|---|---|---|

0000 | 0001 | 0 | 0 | 0 | 1 |

0001 | 0010 | 0 | 0 | 1 | 0 |

0010 | 0011 | 0 | 0 | 0 | 1 |

0011 | 0100 | 0 | 1 | 0 | 0 |

0100 | 0101 | 0 | 0 | 0 | 1 |

0101 | 0110 | 0 | 0 | 1 | 0 |

0110 | 0111 | 0 | 0 | 0 | 1 |

0111 | 1000 | 1 | 0 | 0 | 0 |

1000 | 1001 | 0 | 0 | 0 | 1 |

1001 | 1010 | 0 | 0 | 1 | 0 |

1010 | 1011 | 0 | 0 | 0 | 1 |

1011 | 1100 | 0 | 1 | 0 | 0 |

1100 | 1101 | 0 | 0 | 0 | 1 |

1101 | 1110 | 0 | 0 | 1 | 0 |

1110 | 1111 | 0 | 0 | 0 | 1 |

1111 | 0000 | 0 | 0 | 0 | 0 |

Family/Device/Fitter Summary | Bit-Parallel Method | Bit-Stream Method |
---|---|---|

MAX3000A/EPM3512AFC256-7 | Not synthesized | Total macrocells 171/512 (33%) |

Cyclone II/EP2C5AF256A7/ | ||

Total logic elements | 157/4608 (3%) | 70/4608 (2%) |

Total combinational functions | 152/4608 (3%) | 49/4608 (1%) |

Dedicated logic registers | 32/4608 (<1%) | 62/4608 (1%) |

Total registers | 32 | 62 |

Total pins | 13/158 (8%) | 13/158 (8%) |

Embedded Multiplier 9-bit elements | 2/26 (8%) | 0/26 (0%) |

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**MDPI and ACS Style**

Bureneva, O.; Kupriyanov, M.; Safyannikov, N. Bit Streaming Processing Algorithms for Intelligent Hardware Converters. *Appl. Sci.* **2021**, *11*, 4899.
https://doi.org/10.3390/app11114899

**AMA Style**

Bureneva O, Kupriyanov M, Safyannikov N. Bit Streaming Processing Algorithms for Intelligent Hardware Converters. *Applied Sciences*. 2021; 11(11):4899.
https://doi.org/10.3390/app11114899

**Chicago/Turabian Style**

Bureneva, Olga, Mikhail Kupriyanov, and Nikolay Safyannikov. 2021. "Bit Streaming Processing Algorithms for Intelligent Hardware Converters" *Applied Sciences* 11, no. 11: 4899.
https://doi.org/10.3390/app11114899