An Improved Investigation into the Effects of the Temperature-Dependent Parasitic Elements on the Losses of SiC MOSFETs

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The conclusion of this paper could serve as an important basis for the design guidelines of fast switching power converters.

Abstract

This paper presents an improved investigation into the effects of temperature-dependent parasitic elements on the silicon carbide (SiC) MOSFET power losses. Based on the physical knowledge of MOSFET, a circuit-level loss analytical model is proposed, which takes the parasitic elements of the power devices and the stray inductances of the Printed Circuit Board (PCB) traces into consideration. The state equations derived from the equivalent circuit of each stage is solved by iteration to calculate the loss in the switching transients. In order to study the temperature characteristic completely, the key parameters needed in the calculation are extracted from power device test platform based on Agilent B1505A. The loss assessment of the proposed analytical model with varied elements has been successfully substantiated by the experimental results of a 400-V, 15-A double-pulse-test bench. Finally, some practical knowledge about loss mechanisms is given to help estimate the power losses and optimize the efficiency of power converters.

1. Introduction

In recent years, silicon carbide (SiC) has attracted extensive attention and has been gradually applied to power semiconductor devices due to its higher breakdown electric field, electron saturation velocity and thermal conductivity than conventional silicon (Si) materials [1,2,3,4,5]. In addition, increasing switching frequency has always been a common method to push up the power density and facilitate the miniaturization of switching converters by reducing the size of the passive components [6,7]. With a significant increase in switching speed, the effect of parasitic elements that mainly result from power semiconductor devices and PCB traces on switching performance can no longer be ignored and the losses become a crucial factor that determines the converter efficiency. Therefore, it is necessary to accurately calculate the loss of power devices and analyze the effects of the parasitic elements on it, helping designers to acquire in-depth knowledge of the switching loss mechanisms. There is considerable research in this filed. As discussed in [8], basically, investigation into loss can be classified into three categories. They are physical model, behavioral model, and analytical model (also called mathematical model).

Based on the knowledge of semiconductor physics and microelectronics, the physical model solves the characteristic expression of power devices by conducting the finite element analysis (FEA) [9,10,11,12]. The simulation results of physical model match the experimental results very well. However, this kind of model needs comprehensive parameters of the power device, such as gate oxide thickness, doping concentration in the channel, electron mobility, etc., which are difficult to obtain and the modeling process is rather complex and time-consuming, which is not suitable for circuit-level simulation.

The behavior model is widely used in the loss analysis because it has a good trade-off between the accuracy and simulation time. Based on the values obtained from parameter extraction (normally, device manufacturer provides these data or models on their website), the effect of parasitic elements including the junction capacitances of power devices and the stray inductances of the PCB traces on switching loss can be analyzed by circuit simulation software, e.g., PSpice or Saber, in which behavioral model of the MOSFET is used [13,14,15]. In [14], with specific modifications of the conventional Si power MOSFET model based on PSpice, an improved behavioral model is proposed for 10-kV SiC MOSFETs to validly predict switching loss. However, it cannot suffice to explain the switching loss mechanisms of the power device behind the simulation results.

The last method is the analytical model [16,17,18,19,20,21,22,23,24]. Generally, the switching loss expressions are derived from different equivalent circuits according to different stages on switching transients. The simplest and classical analytical model is the piecewise linear model, which is easier to obtain and solve than the aforementioned two model. However, there are many limitations in such a model; for example, ([16]) the analytical model only considers the gate resistance and the junction capacitances (the switching process is equivalent to the charging and discharging process of the RC circuit). In practice, especially in high-frequency operation, the effect of parasitic inductances cannot be totally ignored. Other analytical models that consider both junction capacitances and parasitic inductances have also been proposed. The effect of the parasitic elements on switching performance in low-voltage operation (the voltage lower than 40 V) has been extensively discussed in [17,18,19,20]. In low-voltage operation, the drain-source voltage may reach zero before the drain current reaches the steady-state value during the turn-on transients and the drain current may drop to zero before the drain-source voltage reaches bus voltage during the turn-off transients [19]. However, these particular cases will hardly happen to high-voltage MOSFETs. The analytical model of [21] considers the MOSFET–Snubber–Diode (MSD) configuration, whereas it treats the trans-conductance and the threshold voltage as a constant. In [23,24], the parasitic elements of the analytical model are extracted from the datasheet of the device vendor, but these models cannot reflect the temperature characteristics of the parasitic elements of the power devices. As a result, there are a lot of limitations in these analytical models.

For the sake of accuracy and computational efficiency, an improved analytical model that considers temperature-dependent parasitic elements of SiC MOSFET and the interaction between exterior parasitic inductances of PCB traces will be proposed. The paper is organized as follows: in Section 2, the basis of modeling is given. In Section 3, the turn-on and turn-off transients of the SiC MOSFET are divided into five stages, respectively, and then the state equations are derived from the equivalent circuits of each stages. In Section 4, a power device analysis platform is built to obtain the detailed temperature characteristics of the parasitic elements. In Section 5, the calculation results of this proposed analytical model will be verified by comparison with the experimental results of a 400-V, 15-A double-pulse test bench, then, the effects of the parasitic elements on loss will be comprehensive explained. Finally, a conclusion that can help engineer to design high-frequency power converters and minimize switching loss will be given in the Section 6.

2. The Basis of the Analytical Model

Figure 1 shows a simplified physical structure of Vertical Double-diffused MOSFET (VDMOSFET) considering the discrete package. There is an internal resistance due to the gate contact. The pad parasitic inductances and the internal bonding between the carbon silicon die and the package pads, which are relevant to the package technology, contribute to the total parasitic inductance in the power device. The only viable alternative to further lower the parasitic inductances is to concurrently address the underlying package problem, using clip lead or sandwich package assembly methods to eliminate bond wires while maximizing the ratio of die area to package footprint [25]. As a unipolar device, the dynamic characteristics of SiC MOSFET are mainly determined by the charging and discharging process of the junction capacitances which are composed of oxide capacitances and depletion edge capacitances [26]. The width of depletion edge is related to the applied voltage between drain terminal and source terminal, so that the value of the junction capacitances is nonlinear. When a positive voltage applied between the gate terminal and source terminal, the depletion region gets wider towards the body, and it begins to drag the free electrons to the interface. As the density of the free holes of the body and the density of the free electrons of the interface becomes equal, the free electron layer is called the inversion layer (N channel).

Based on the above knowledge, the equivalent circuit of the MOSFET is obtained, as shown in Figure 2. The junction capacitances are represented by three nonlinear capacitances connected in parallel with each internal node. The parasitic inductances in series in each terminal of the device (the gate terminal also includes the internal resistance). The channel is the key element of modeling, which determines the accuracy of the model and should be carefully considered. The equivalent of the channel in the switching transients will be thoroughly discussed in the next section.

3. Analysis of the Switching Transients

The switching process of the MOSFET will be studied stage by stage in this section. A double-pulse test circuit is adopted for the modeling of MOSFET switching transients, as shown in Figure 3. The input is a constant voltage source V_DD and the load is a clamped-inductive load which can provide a constant current I_DD. The gate signal V_pulse is assumed to flip between V_SS and V_GG with zero rise time and fall time in the analysis. In order to investigate the switching process better, two different external gate resistances R_{g_on} and R_{g_off} are used in the turn-on transients and turn-off transients, respectively. Similar to the MOSFET, the freewheeling diode is modeled by two parasitic inductances L_{c_1} and L_{a_1} and a parasitic resistance R_f in series with an ideal diode D_f, and then in parallel with a nonlinear junction capacitance Cf. In addition to these power devices, there also are a lot of stray inductances result from the PCB traces of the power loop, which are represented by L_bus1, L_bus2, L_{c_2}, L_{a_2}, L_{d_2}, L_{g_2} and L_{s_2}. In order to simplify the model and the equations, some parameters are merged in the equivalent circuit. L_d1 = L_{d_ext} + L_{d_int}, L_g1 = L_{g_ext} + L_{g_int} and L_s1 = L_{s_ext} + L_{s_int} are denoted as the total parasitic inductances at each terminal of the MOSFET, respectively. It should be noted that the stray inductance of the ground lead of a measuring loop is hard to quantitatively analyze and its influence on the loss assessment can be ignored. Therefore, it was not considered in this model.

3.1. Turn-On Switching Transients

Stage 1 [t0–t1] turn-on delay time: Before the gate source voltage v_gs reaches the threshold voltage V_th, the SiC MOSFET power device is still in the cut-off region. At this stage, the value of the drain current id is assumed to be zero. According to Figure 4a and Kirchhoff’s law, the following equations are obtained:

$$V_{GG}=R_{GG}{i}_g+L_g\frac{d{i}_g}{dt}+v_{gs}+L_s\frac{d{i}_s}{dt}$$

(1)

$$i_g=C_{gs}\frac{d{v}_{gs}}{dt}+C_{gd}\frac{d{v}_{gd}}{dt}$$

(2)

$$i_s=C_{gs}\frac{d{v}_{gs}}{dt}+C_{ds}\frac{d{v}_{ds}}{dt}$$

(3)

$$v_{gs}=v_{gd}+v_{ds}$$

(4)

$$i_g+i_d=i_s$$

(5)

where R_GG = R_{g_on} + R_{g_int}, L_g = L_g1 + L_g2.

There are three independent state variables: the drain current i_g, the gate-source voltage v_gs and the drain-source voltage v_ds. The state equations derived from above equations are shown in Appendix A Equation (A1). As the power device is not activated, there is no switching loss P_sw during this period.

Stage 2 [t1–t2] current rise time: When the gate source voltage v_gs goes beyond the threshold voltage V_th, the conductive pass (channel) enabling the current flow begins to form. Due to the fast speed of the SiC MOSFET power device, the drain current i_d surges, which generates the induced voltage across the parasitic inductances. This induced voltage deservers special attention, as it determines whether the drain current (id) will rise to its full value I_DD before or after the drain-source voltage v_ds drops to v_gs − V_th (the boundary condition between the saturation region and the ohmic region of MOSFET). If the power device works in the saturation region, the channel of the SiC MOSFET can be equivalent to a voltage-controlled current source (the relationship between the channel current i_ch and gate-source voltage v_gs is governed by (6)), otherwise it can be equivalent to a nonlinear resistance which is related to the junction temperature T_j and the drain current i_d. Both of them are discussed as follows.

$$i_{ch}=g_f(v_{gs}-V_{th})$$

(6)

where g_f is trans-conductance of the SiC MOSFET, which is also nonlinear.

Case I: The MOSFET works in the saturation region. In this situation, as shown in Figure 4b, the drain current i_d consists of three parts: the channel current i_ch and the current flowing through the junction capacitor C_gd and C_ds. The circuit equations can be expressed as:

$$V_{GG}=R_{GG}{i}_g+L_g\frac{d{i}_g}{dt}+v_{gs}+L_s(\frac{d{i}_d}{dt}+\frac{d{i}_g}{dt})$$

(7)

$$i_g=(C_{gs}+C_{gd})\frac{d{v}_{gs}}{dt}-C_{gd}\frac{d{v}_{ds}}{dt}$$

(8)

$$v_{ds}=V_{DD}-v_f-L_p\frac{d{i}_d}{dt}-L_s\frac{d{i}_g}{dt}$$

(9)

$$i_d=g_f(v_{gs}-V_{th})+C_{ds}\frac{d{v}_{ds}}{dt}-C_{gd}\frac{d(v_{gs}-v_{ds})}{dt}$$

(10)

$$v_f=R_f(i_d-I_{DD})-V_f$$

(11)

where L_p = L_bus1 + L_bus2 + L_c + L_a + L_d + L_s, L_c = L_c1 + L_c2, L_a = L_a1 + L_a2, L_d = L_d1 + L_d2, L_s = L_s1 + L_s2.

Case II: The MOSFET works in ohmic region directly. As discussed above, the channel of MOSFET can be represented by a nonlinear resistance in this scenario. Therefore, (10) is changed to (12), and the rest remains unchanged.

$$i_d=\frac{v_{ds}}{R_{on}}+C_{ds}\frac{d{v}_{ds}}{dt}-C_{gd}\frac{d(v_{gs}-v_{ds})}{dt}$$

(12)

A new independent state variable i_d appears in this stage compared to the previous one, and the state equations derived from the above equations are shown in Appendix A Equation (A3). This stage ends when the drain current id reaches the bus current I_DD. The switching loss E_sw expression in this period is as follows.

$$E{(\mathsf{{\rm I}})}_{sw\_s2}={\displaystyle {\int }_{t_1}^{t_2}{i}_d{v}_{ds}dt}$$

(13)

However, a more appropriate switching loss analysis is to replace (13) with (14), taking into account the assumption that the junction capacitances of MOSFET are only lossless energy buffers. The discrepancy between the two types of calculation methods will be further elucidated in Section 5 with the experimental verification.

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s2}={\displaystyle {\int }_{t_1}^{t_2}{i}_{ch}{v}_{ds}dt}$$

(14)

Stage 3 [t2–t3] voltage falling time I: As the current is transferred to the SiC MOSFET, the SiC Schottky Diode (SBD) becomes capable of blocking the voltage; Figure 4c shows the equivalent circuit of this stage, and the drain-source voltage v_ds drops dramatically at the same time, if the case I occurs in the previous stage. The gate-source voltage v_gs is maintained at the Miller Plateau, because the gate current i_g is completely absorbed by the drain-source capacitance C_ds without flowing to the gate-source capacitance C_gs. Although SBD features zero reverse recovery current, the drain current id continues to increase since the charging current of junction capacitance C_f of the SiC SBD. Therefore, (11) is replaced by (15), and the rest remains unchanged. A resonant period begins in this moment, which induced by the oscillations between L_p and C_f. This stage ends when drain-source voltage v_ds decreases to v_gs − V_th.

$$\frac{d{v}_f}{dt}=\frac{i_d-I_{DD}}{C_f}$$

(15)

There are five independent state variables: the drain current i_g, the drain current i_d, the gate-source voltage v_gs, the drain-source voltage v_ds and the free freewheeling diode voltage v_f. The state equations at this stage are shown in Appendix A Equation (A4).

During this period, the two type of switching loss calculation as following:

$$E{(\mathsf{{\rm I}})}_{sw\_s3}={\displaystyle {\int }_{t_2}^{t_3}{i}_d{v}_{ds}dt}$$

(16)

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s3}={\displaystyle {\int }_{t_2}^{t_3}{i}_{ch}{v}_{ds}dt}$$

(17)

Stage 4 [t3–t4] voltage falling time II: When the drain-source voltage v_ds decreases to v_gs − V_th, the SiC MOSFET will come out of the saturation region and get into the ohmic region. As shown in Figure 4d, the channel is equivalent to a nonlinear resistance (also called on-state resistance) in this stage. Therefore, (10) is replaced by (18). The gate-source voltage v_gs breaks out of the Miller Plateau and begins to increase again. The drain-source voltage v_ds drops slightly in this period, and the drain current id drops back to I_DD simultaneously. The oscillations in the power loop will be damped by the stray resistance resulting from the PCB traces. In order to specify this point, a lumped resistance R_stray is added in the equivalent circuit, as same as the stray inductances, to compensate for the active power consumption and (9) should be replaced by (19). Once the drain-source voltage v_ds decreases to i_d·R_on, this stage ends and the channel can be seen as completely conductive.

$$i_d=\frac{v_{ds}}{R_{on}}+C_{ds}\frac{d{v}_{ds}}{dt}-C_{gd}\frac{d(v_{gs}-v_{ds})}{dt}$$

(18)

$$v_{ds}=V_{DD}-v_f-R_{stray}{i}_d-L_p\frac{d{i}_d}{dt}-L_s\frac{d{i}_g}{dt}$$

(19)

The independent state variables at this stage remain unchanged and the state equations are shown in Appendix A Equation (A5). The switching loss in this period can be calculated as:

$$E{(\mathsf{{\rm I}})}_{sw\_s4}={\displaystyle {\int }_{t_3}^{t_4}{i}_d{v}_{ds}dt}$$

(20)

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s4}={\displaystyle {\int }_{t_3}^{t_4}{i}_{ch}{v}_{ds}dt}$$

(21)

Stage 5 [t4–t5] On-State Operation: The gate current i_g still continues to charge the gate-source capacitance C_gs until the gate-source voltage v_gs reaches the positive drive voltage V_GG. The state equations and the equivalent circuit are the same as the previous stage, while the loss at this stage is considered as conduction loss E_cond and can be calculated as:

$$E_{cond1}={\displaystyle {\int }_{t_4}^{t_5}{i}_d^2{R}_{on}dt}$$

(22)

3.2. Turn-Off Switching Transients

It is known that the turn-off switching transients are a reversely symmetrical process of the turn-on switching transients, in which the channel can also be equivalent to a nonlinear resistance, voltage-controlled current source, or an open circuit. Therefore, some repeated equations are omitted in the derivation of the stage equations for the turn-off switching transients.

Stage 6 [t6–t7] Turn-Off Delay Time: Before the gate source voltage v_gs reduces to the Miller Voltage V_miller, which is governed by (23), the SiC MOSFET power device operates in the ohmic region. It is assumed that the drain current i_d remains unchanged (i_d = I_DD) at this stage. As shown in Figure 5a, the gate-source capacitance and the gate-drain capacitance are being discharged through R_g and L_s. The circuit equations are shown from (24) to (26):

$$V_{mil}=\frac{I_o}{g_f}+V_{th}$$

(23)

$$V_{SS}=R_{SS}{i}_g+L_g\frac{d{i}_g}{dt}+v_{gs}+L_s(\frac{d{i}_d}{dt}+\frac{d{i}_g}{dt})$$

(24)

$$i_g=(C_{gs}+C_{gd})\frac{d{v}_{gs}}{dt}-C_{gd}\frac{d{v}_{ds}}{dt}$$

(25)

$$i_s=\frac{v_{ds}}{R_{on}}+C_{gs}\frac{d{v}_{gs}}{dt}+C_{ds}\frac{d{v}_{ds}}{dt}$$

(26)

where R_SS = R_{g_off} + R_{g_int}.

As with the stage 1, there are three independent state variables: the drain current i_g, the gate-source voltage v_gs and the drain-source voltage v_ds, and the state equations derived from the above equations are shown in Appendix A Equation (A6). Since the device is still activated, the loss during this period is conduction loss E_cond, which can be calculated as:

$$E_{cond2}={\displaystyle {\int }_{t_5}^{t_6}{i}_d^2{R}_{on}dt}$$

(27)

Stage 7 [t7–t8] Voltage Rising Time I: During this stage, the power device still works in the ohmic region until the drain-source voltage v_ds reaches v_gs − V_th. Therefore, the drain current i_d stays constant at I_DD and the gate-source voltage v_gs (almost) remains at the Miller voltage. The equivalent circuit and equations during this period are the same as the previous one, while the loss during this period is regarded as the switching loss E_sw and can be calculated as:

$$E{(\mathsf{{\rm I}})}_{sw\_s7}={\displaystyle {\int }_{t_6}^{t_7}{i}_d{v}_{ds}dt}$$

(28)

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s7}={\displaystyle {\int }_{t_6}^{t_7}{i}_{ch}{v}_{ds}dt}$$

(29)

Stage 8 [t8–t9] Voltage Rising Time II: When the drain-source voltage v_ds reaches v_gs − V_th, the device begins to operate in saturation region. Therefore, the channel is equivalent to a voltage-controlled current source, as shown in Figure 5b. The drain-source voltage v_ds continues to increase until the forward voltage v_f of the SBD decreases to the forward voltage −V_f. The voltage slew rate will be faster than in the previous stage, since the value of junction capacitance significantly decreases with the increase in drain-source voltage v_ds. A part of I_DD will be flowing through the freewheeling diode to discharge the C_f, which will be causing the drain current id drop. During this period, the channel current i_ch is also governed by (6). Hence the drain current id expression is changed to (10) and the rest of the circuit equations are the same as the stage 4 and the state equations are shown in Appendix A Equation (A8). During this period, the switching loss E_sw is given by (30) and (31).

$$E{(\mathsf{{\rm I}})}_{sw\_s8}={\displaystyle {\int }_{t_7}^{t_8}{i}_d{v}_{ds}dt}$$

(30)

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s8}={\displaystyle {\int }_{t_7}^{t_8}{i}_{ch}{v}_{ds}dt}$$

(31)

Stage 9 [t9–t10] Current Falling Time: When the freewheeling diode ceases to block the voltage, the current begins to divert from the MOSFET to the freewheeling diode rapidly, which will induce a voltage drop across the parasitic inductances and simultaneously incur a voltage overshoot on the drain-source voltage v_ds. Compare to the previous stage, the expression of the freewheeling diode voltage is replaced by (11) and the rest of circuit equations remain unchanged. This stage ends when the gate-source voltage v_gs decreases to V_th. The equivalent circuit is shown in Figure 5c.

$$E{(\mathsf{{\rm I}})}_{sw\_s9}={\displaystyle {\int }_{t_8}^{t_9}{i}_d{v}_{ds}dt}$$

(32)

$$E{(\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_s9}={\displaystyle {\int }_{t_8}^{t_9}{i}_{ch}{v}_{ds}dt}$$

(33)

Stage 10 [t10–t11] Off-State Operation: After the gate-source voltage v_gs decreases to V_th, the device works in the cut-off region. For a similar reason, a lumped resistance is added in the circuit (shown in Figure 5d). This stage ends, when the gate-source voltage v_gs decreases to the negative drive voltage V_SS. The state equations are shown in Appendix A Equation (A9) Since the channel is inactive, there is no power loss during this period. As discussed above, the power loss during the switching transient can be categorized and summarized as (34) to (37).

$$E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_on}={\displaystyle \sum _{i=2}^{4}E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_si}}$$

(34)

$$E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_off}={\displaystyle \sum _{i=7}^{9}E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_si}}$$

(35)

$$E_{cond}=E_{cond1}+E_{cond2}$$

(36)

$$E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{total}=E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_on}+E{(\mathsf{{\rm I}}/\mathsf{{\rm I}}\mathsf{{\rm I}})}_{sw\_off}+E_{cond}$$

(37)

4. Experimental Setup

Based on the proposed analytical model, except for the operating condition V_DD, I_DD, V_GG, and V_SS, the parameters needed in the calculation are the junction capacitances C_gs, C_gd, C_gs and C_f, the stray inductances of the PCB traces L_bus, L_line, the parasitic inductances of the terminal L_g, L_d, L_s, L_a and L_c, and the static characteristic of power devices: the trans-conductance g_f, the internal resistance R_{g_int} and R_f, the threshold voltage V_th, the forward voltage V_f, and on-state resistance R_on. Apart from the junction capacitances and the parasitic, stray inductances, all the other parameters are temperature dependent. Therefore, it is necessary to build a test platform for the measurement. The approaches to obtain these parameters can be divided into three categories.

4.1. Static Characteristic Test Platform

According to the standards of IEC 60747-8 [27] and datasheet of the device vendor [28,29], the static characteristic test platform based on Power Device Analyzer Curve Tracer (PDACT) Agilent B1505A with the heating plate was established to measure the static characteristic of SiC MOSFET C2M0025120D (Cree, 1200 V, 90 A) and SiC SBD C4D20120A (Cree, 1200 V, 90 A), as shown in Figure 6. Considering the materials and components that make up the package are not compatible with high temperature (usually lower than 175 °C) [30], the testing temperature ranges from 25 to 150 °C. It should be noted that the case temperature T_c obtained by infrared thermal camera is used to approximate the junction temperature T_j, since the latter is difficult to measure by conventional methods. The specific settings of each module are shown in

Table 1. Preliminary setting of the state characteristic testing.

Static Characteristic	Part Number	Parameter	Gate-Source Voltage/Step	Applied Voltage/Step	Temperature/Step
Transfer characteristic	B1510A and B1512A	gf	0 to 12 V/0.25 V	20 V (fixed)	25 to 150 °C/25 °C
Output characteristic		Ron	10 to 20 V/2 V	0 to 10 V/2 V
Threshold voltage		Vth, Vf	0 to 5 V/0.1 V	10 V, Id = 15 mA (fixed)	25 to 145 °C/10 °C
Junction capacitance	B1520A	Ciss, Coss, Ciss, Cf	Sweep signal	Applied voltage	Temperature/step
			VAC = 25 mV, f = 1 MHz	0 to 1000 V	25 to 150 °C/25 °C

.

4.2. ANSYS Q3D Extractor

A common approach to measure the value of the stray inductance is computational electromagnetics [31], which relies on finite-element analysis (FEA) simulation (e.g., ANSYS Q3D Extractor) to solve Maxwell’s equations through the PCB layout and component material information. The stray resistance and stray inductance, including both self-inductance and mutual-inductance, can be accurately extracted through this approach. However, in order to simplify the calculation, the mutual inductances are neglected in this analytical model.

4.3. Vector Network Analyzer

The parasitic inductance is mainly determined by the devices package. However, the above approach suffers from being time-consuming and having poor convergence, since the physical structure of a package is complex. There is a more practical approach which is based on Impedance Analyzer or Vector Network Analyzer (VNA) [32]. By calibrating the test system using a mathematical technique called vector error correction, VNA provides high measurement accuracy [33]. The power device is performed over a frequency range of 100 kHz to 200 MHz by Keysight VNA (E5061B). Since the MOSFET under zero applied voltage is equivalent to a second-order RLC circuit, as shown in Figure 7, it has a self-resonant frequency (SRF). The parasitic inductances and internal resistances can be calculated through its SRF [34]. The testing temperature also ranges from 25 to 150 °C.

5. Results

5.1. Experimental Results

The static characteristic parameters obtained from the above methods are shown in Figure 8e (the black scatter plot). All of these measured scatters require nonlinear fitting before they can be used for calculation. The extraction results of the stray inductances of PCB traces and the parasitic inductances of power device terminals are shown in

Table 2. Extraction results of the stray and parasitic inductances.

Q3D	Parameter	Lbus1	Lbus2		Lc2	La2		Lg2	Ld2	Ls2	Rstray
	Value(nH)	51.24	72.85		4.25	4.12		6.39	12.08	1.71	1.85 Ω
VNA	Package	TO-247-3							TO-220-2
	Parameter	Lg1 (nH)		Ld1 (nH)			Ls1 (nH)		La1 + Lc1 (nH)
	Maximum	9.57 (@ 50 °C)		4.71 (@ 25 °C)			8.39 (@ 50 °C)		10.12 (@ 25 °C)
	Minimum	9.13 (@ 75 °C)		4.54 (@ 125 °C)			8.06 (@ 150 °C)		9.79 (@ 100 °C)
	Difference	4.77%		3.79%			4.21%		3.34%
	Average	9.218		4.623			8.176		9.889

, respectively. Due to the maximum difference of less than 5%, the parasitic inductances are treated as a constant (the average) in the later calculation. The internal resistance R_{g_int} and R_f obtained through VNA measuring are shown in Figure 8f while the others, such as R_{s_int} and R_{d_int}, are ignored in the proposed model since their values are very small.

5.2. Fitting to the Key Parameters

For the sake of a trade-off between the precision and simplicity, the polynomial fitting is adopted to fit the static characteristic curve of the SiC MOSFET C2M0025120D. An appropriate polynomial order is chosen to ensure the R-squared (coefficient of determination, a goodness of fit) higher than 0.995. The trans-conductance gf and on-state resistance R_on can be regarded as a two-variable function of V_gs and T_j and function of id and T_j, respectively. The fitting equations are given in (38) and (39), the fitted curves are shown in the Figure 8a,b.

$$\begin{array}{l}{g}_f(v_{gs},T_j)=p_{00}+p_{10}{v}_{gs}+p_{01}{T}_j+p_{20}{v}_{gs}^2+p_{11}{v}_{gs}{T}_j+p_{02}{T}_j^2+p_{30}{v}_{gs}^3+p_{21}{v}_{gs}^2{T}_j+p_{12}{i}_d{T}_j^2+p_{03}{T}_d^3\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}+p_{40}{v}_{gs}^4+p_{31}{v}_{gs}^3{T}_j+p_{22}{v}_{gs}^2{T}_j^2+p_{13}{v}_{gs}{T}_j^3+p_{04}{T}_j^4\end{array}$$

(38)

where p₀₀ = −1.313, p₁₀ = 2.74, p₀₁ = 2.292 × 10⁻⁴, p₂₀ = −1.287, p₁₁ = −3.362 × 10⁻², p₀₂ = −9.872 × 10⁻⁵, p₃₀ = −0.2086, p₂₁ = 9.167 × 10⁻³, p₁₂ = 9.789 × 10⁻⁵, p₀₃ = 6.437 × 10⁻⁸, p₄₀ = −8.4 × 10⁻³, p₃₁ = −5.352 × 10⁻⁴, p₂₂ = −1.034 × 10⁻⁵, p₁₃ = −8.058 × 10⁻⁸, p₀₄ = 2.109 × 10⁻¹⁰.

$$\begin{array}{l}{R}_{on}(i_d,T_j)=p_{00}+p_{10}{i}_d+p_{01}{T}_j+p_{20}{i}_d^2+p_{11}{i}_d{T}_j+p_{02}{T}_j^2+p_{30}{i}_d^3+p_{21}{i}_d^2{T}_j+p_{12}{i}_d{T}_j^2+p_{03}{T}_d^3\\ \hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}+p_{40}{i}_d^4+p_{31}{i}_d^3{T}_j+p_{22}{i}_d^2{T}_j^2+p_{13}{i}_d{T}_j^3+p_{04}{T}_j^4\end{array}$$

(39)

where p₀₀ = 30.71, p₁₀ = 0.03, p₀₁ = −0.1388, p₂₀ = 3.705 × 10⁻⁴, p₁₁ = −2.019 × 10⁻⁴, p₀₂ = 4.309 × 10⁻³, p₃₀ = −1.091 × 10⁻⁸, p₂₁ = −1.725 × 10⁻⁶, p₁₂ = 2.894 × 10⁻⁶, p₀₃ = −2.642 × 10⁻⁵, p₄₀ = 6.933 × 10⁻⁹, p₃₁ = −2.448 × 10⁻⁹, p₂₂ = 2.817 × 10⁻⁹, p₁₃ = −6.658 × 10⁻⁹, p₀₄ = 6.943 × 10⁻⁸.

The threshold voltage V_th, the forward voltage V_f, the gate internal resistance R_{g_int} and the freewheeling resistance R_f can be regarded as a single-variable function of the junction temperature T_j. The fitting equations are given from (40) to (43) and the fitted curves are shown from Figure 8c–f.

$$V_{th}(T_j)=1.064\times {10}^{-5}{T}_j^2-0.006629T_j+2.779$$

(40)

$$V_f(T_j)=-0.001509T_j+1.012$$

(41)

$$R_{g\_\mathrm{int}}(T_j)=p_1{T}_j^3+p_2{T}_j^2+p_3{T}_j+p_4$$

(42)

where p₁ = 6.104 × 10⁻⁸, p₂ = 7.835 × 10⁻⁶, p₃ = −4.974 × 10⁻³, p₄ = 1.524.

$$R_f(T_j)=0.271T_j+22.52$$

(43)

Nevertheless, polynomial does not perform well in the junction capacitance versus the applied voltage curve fitting. According to [35,36], the input capacitance C_iss was treated as two discrete values and (44) is adopted to characterize the nonlinearity of the output capacitance C_oss and the reverse transfer capacitance C_rss (see

Table 3. Specification of nonlinear junction capacitances.

	$\mathbf{0}\mathit{V}\mathbf{<}\mathit{v}\mathbf{\le }\mathbf{10}\mathit{V}$	$\mathbf{10}\mathit{V}\mathbf{<}\mathit{v}\mathbf{\le }\mathbf{400}\mathit{V}$
Cf (pF)	$\frac{1500}{{(1+\frac{v_{ca}}{1.412})}^{0.5047}}$	$\frac{1500}{{(1+\frac{v_{ca}}{1.387})}^{0.5007}}$
Ciss (pF)	4000	3300
Coss (pF)	$\frac{3850}{{(1+\frac{v_{ds}}{2.394})}^{0.5895}}$	$\frac{3850}{{(1+\frac{v_{ds}}{1.154})}^{0.4654}}$
Crss (pF)	$\frac{1430}{{(1+\frac{v_{ds}}{1.041})}^{0.774}}$	$\frac{1430}{{(1+\frac{v_{ds}}{0.03})}^{0.4964}}$

). The transform relationship between C_iss, C_rss, C_oss and C_gs, C_gd, C_ds is shown in (45).

$$C=\frac{C_0}{{(1+\frac{v}{a})}^b}$$

(44)

where v is the applied voltage, C₀ is the capacitance value under v = 0 V, a and b are two adjustment parameters extracted from the capacitance versus voltage curve.

$$\left\{\begin{array}{l}{C}_{iss}=C_{gs}+C_{gd}\hfill \\ C_{rss}=C_{gd}\hfill \\ C_{oss}=C_{gd}+C_{ds}\hfill \end{array}\right.$$

(45)

5.3. Loss Assessment

Based on the discussion above, the flowchart in Figure 9 presents the calculation routine for applying the model. Compared with traditional method, the iterative method is adopted to solve the state equations, from which the numerical solution can be derived without simplification [37]. Therefore, the calculation accuracy is improved. As mentioned in the previous section, there are two switching loss calculation methods in this model. In turn-on transients, the calculation I will be less than calculation II, since the discharging current of C_ds and C_gd, which opposes the trend of the drain current is included in i_d. However, the turn-off loss of calculation I will be greater than calculation I due to the charging current of C_ds and C_gd. As a result, the two types of calculation would not vary the E_total but would instead vary the distribution of power losses between E_{sw_on} and E_{sw_off}.

The experimental prototype of a 400-V, 15-A double-pulse-test setup is shown in Figure 10, in which the chip inductors are added to simulate the varied stray inductances.

As stated in [38], the measurement system bandwidth should be higher than ten times the highest equivalent frequency of the measured signal, which can be approximated by

$$f=\frac{0.25}{\min (t_r,t_f)}$$

(46)

where t_r is the rise time, t_f is the fall time.

The typical rise/fall time of C2M0025120D is 32/28 ns. According to (46), the equivalent frequency is 8.9 MHz. The measurement system specified in

Table 4. Specification of the measurement system.

Part No.	Description	Bandwidth	Measured Signal
RTH1004	Oscilloscope	500 MHz
RT-ZI10	Passive probe	500 MHz	vds
TPP0201	Passive probe	200 MHz	vgs
TCP0030A	Current probe	120 MHz	id

can meet the bandwidth requirement. It must be pointed out that for the sake of emulating the switching waveforms taken in the experiment, the induced voltage drops across the parasitic inductances of the package terminal; L_s1 and L_d1 have to be included in the analytical waveforms for v_ds, as they are intrinsic and inside the package.

As shown in Figure 11, the switching waveforms of the proposed analytical model match the experiment well. Voltage and current overshoot are also important factors in the application of the power device, which should be considered together with the power losses. The quantitative comparison of loss and voltage and current overshoot is listed in

Table 5. Quantitative comparison of loss, voltage and current overshoot.

	Experiment	Calculation I	Error
Esw-on(μJ)	119.06	121.05	1.67%
Esw-off(μJ)	66.27	67.51	1.87%
Econd(μJ)	3.71	3.45	7.01%
Vos(V)	111.65	119.61	7.13%
Ios(A)	6.22	6.45	3.70%

. The maximum error is 7.13%, which proves the good accuracy of the model. The variation patterns of power losses with each parameter element can be worked out by the calculation, as shown in Figure 8, to present a further investigation into the loss mechanism and they will be demonstrated experimentally. The ±10% error bars of the experimental results are added to illustrate the accuracy. It can be seen that the calculation results are in good accordance with the experiment.

$$\ast \mathrm{Error}=\left|\frac{\mathrm{Calculated}\mathrm{value}-\mathrm{Experimental}\mathrm{value}}{\mathrm{Experimental}\mathrm{value}}\right|\times 100\%$$

Junction Temperature: In Figure 8, it can be seen that most of the key parameters are temperature-dependent. As a result, the temperature will affect the switching performances of SiC MOSFET obviously. The comparison of power losses between experiment and calculation with varied junction temperature T_j are illustrated in Figure 12a. It is easy to see that the increase in T_j reduces the turn-on loss and increases the turn-off loss contrarily. The conduction loss increases slightly, since the on-state resistance R_on is positively correlated with T_j. As a result, the total loss does not exhibit great variation at different T_j. In the turn-off transients, with the increased trans-conductance g_f affected by the rising junction temperature T_j, the Miller voltage will decrease consequently, which leads to a reduction in the current slew rate. Hence, the voltage overshoot decreases with the increase in T_j, as shown in Figure 12b.

Gate Driver Resistance:Figure 13a presents the power losses with varied R_g. It shows that the switching loss (both turn-on and turn-off) exhibit distinctive increases with the increase in R_g, which is due to the slower switching speed resulting from larger R_g. For the same reason, the voltage and current overshoot will all decrease (see Figure 13b). It is necessary for designers to make a trade-off between switching speed and switching loss. The double-gate-resistances is a useful solution; a proper turn-on resistance to ensure the switching speed and a low turn-off resistance to discharge the C_gs fast.

Loop Parasitic Inductance: L_p denotes all the stray inductances along the power loop and the parasitic inductances of the terminal of the power devices. Figure 14a illustrates the power losses with varied L_p. It can be seen that the turn-on loss decreases obviously with the increase in L_p, because the greater L_p will induce a larger voltage drop in stage 2, so that the voltage falling time will be shorter. However, as shown in Figure 14b, the larger L_p will generate a larger voltage overshoot and current voltage.

Common Source Stray Inductance: L_s2 differ from other stray inductances of PCB traces since it co-exists in both the power stage and the gate drive stage. When the MOSFET works in the saturation region (the channel equivalent to a voltage-controlled current source), the fast-changing drain current will induce a voltage drop across L_s2, which provides a negative feedback to the gate drive stage. Hence, the effect of L_s2 on switching loss is similar to R_g, as shown in Figure 15. In common engineering practice, the gate driver is normally placed next to the power device as close as possible to reduce this inductance.

External Gate Stray Inductance: The comparison of power losses, voltage overshoot and current overshoot between experiment and calculation with varied external gate stray inductance L_g2 is illustrated in Figure 16a,b, respectively. There is no recognizable difference with varied L_g2. In fact, according to the circuit design guidelines, L_g2 should be kept small to avoid the oscillations between L_g and C_gs.

According to the aforementioned experimental and analytical investigation, the effects of the varied elements including the T_j, R_g, L_p, L_s2 and L_g2 on the power losses and voltage and current overshoot in the switching transients are summarized in

Table 6. Quantitative comparison of loss, voltage and current overshoot.

Elements	T	Rg	Lp	Ls2	Lg2
Esw-on	↓	↑	↓	↑	→
Esw-off	↑	↑	→	↑	→
Etotal	→	↑	↓	↑	→
Vos	↓	↓	↑	↓	→
Ios	→	↓	↑	↓	→

↑/↓, denotes increase/decrease with the increase in the varied element; → denotes no obvious change the with the increase in the varied element.

.

6. Conclusions

This paper has presented an improved analytical loss model which takes the parasitic elements of the power devices and the stray inductances of the PCB traces into consideration. A comprehensive power device test platform is built to extract the key temperature-dependent parameters in the calculation. The measurement results show that the trans-conductance g_f, on-state resistance R_on, threshold voltage v_th and internal resistance R_g-int are sensitive to junction temperature. The switching waveforms of the proposed analytical model successfully match the experiment results of a 400-V, 15-A double-pulse-test bench. In addition, the variation patterns of power losses both in calculation and experiments can be summarized as follows.

(1) The increase in the gate driver resistance R_g or the common stray inductance L_s2 will increase the total loss while decreasing the voltage overshoot and the current overshoot at the same time. In common practical applications, the gate driver resistance R_g is the only component that can be changed. Therefore, it should be chosen to compromise the conflicts between power loss and device stresses.

(2) The increase in the loop parasitic inductances L_p will decrease the total loss while increasing the voltage overshot and the current overshoot in the meantime.

(3) The total loss does not change obviously with the varied junction temperature T_j and the varied external gate stray inductance L_g2.

The summarized conclusions above are expected to assist PCB layout design in practical applications of the SiC MOSFET, which is aimed at achieving a low power loss with proper device stresses. Future studies will be dedicated to varied circuits based on this study.