Symmetry and Extended Duality in Resonant DC-AC Inverters: Open-Input and Closed-Input Operation Below and Above Resonance

Abstract

This paper develops a symmetry-oriented regime-level framework for resonant DC-AC inverters that extends classical source duality toward a multidimensional representation of inverter operation. The proposed formulation introduces a compact inverter signature vector and associated symmetry operators to organize source-domain, detuning side, commutation, switch-path, and modal correspondences within a unified hierarchy. On this basis, a symmetry-guided workflow is defined using compact screening metrics for stress/circulation balance, phase displacement, and commutation feasibility, enabling early-stage comparison of operating regimes before topology-specific detailed design closure. The framework is demonstrated through an extended-duality pairing of two resonant DC-AC inverter regimes: an open-input super-resonant ZVS-like corridor and a closed-input sub-resonant ZCS-like corridor. The case studies show how the proposed regime signatures and screening metrics support structured reasoning about soft-switching corridors, stress redistribution, and device-class-dependent implications, including wide-bandgap (WBG) design tendencies. The proposed metrics are intended as low-order screening indicators and regime-selection tools rather than substitutes for detailed circuit, thermal, EMI, and device-level validation. Within this scope, the paper contributes an operational symmetry formalism that links duality-based interpretation to practical early-stage design organization and robustness-oriented comparison.

1. Introduction

DC-AC conversion is a cornerstone of modern power electronic systems, enabling grid integration of renewables, motor drives, traction systems, and high-frequency power supplies [1,2]. Resonant and quasi-resonant inverter families are particularly important when efficiency, electromagnetic performance, and switching stress must be managed under high switching frequency or harsh operating conditions [3,4,5].

A symmetry-oriented viewpoint offers an alternative lens to conventional topology-centered classification. Inverters are inherently periodic dynamical systems in which switching actions and reactive energy exchange shape the waveform structure. From this perspective, operating regimes are structured manifestations of symmetry in time, frequency, and energy flow. The classical duality between voltage-source and current-source inverters reflects an important source-domain symmetry [2,4]; however, restricting inverter duality to source type captures only a projection of a broader symmetry space.

In resonant inverters, inverter behavior is strongly governed by frequency-domain symmetry [4,5]. Operation below, at, and above resonance forms a natural symmetry axis, with resonance acting as a symmetry-centered operating point. Crossing resonance changes the sign of the effective reactance, exchanges leading/lagging phase relations between voltage and current and reshapes the commutation environment. These changes often create ZVS-favorable or ZCS-favorable switching tendencies as consequences of regime selection, rather than as independently imposed design goals [5].

Motivated by these observations, this paper develops a generalized symmetry framework for inverter operation in which duality extends beyond source type. The contributions are: (i) an explicit multidimensional symmetry description of inverter regimes; (ii) an extended-duality formulation integrating source, frequency-domain, commutation, and modal symmetries; and (iii) symmetry-guided design implications emphasizing robustness and the cost of symmetry in stress and losses.

Related Work and Positioning

Resonant DC-AC inverters have been developed along two partially overlapping lines. Classical treatments and comparative topology studies describe the main resonant inverter families and their above-resonance design and stress implications [3,6,7,8]. One line treats the inverter as a tuned power amplifier, where the resonant tank enforces waveform symmetry (e.g., Class-E operation and its variants) and the operating point is chosen by frequency-domain balance between device capacitances and tank reactance [9,10,11]. A second line adds resonant transitions to PWM inverters via resonant DC links, resonant poles, and auxiliary commutation networks, achieving soft switching while retaining PWM control degrees of freedom [12,13,14]. Survey treatments emphasize that these families must be analyzed in a joint state-space of operating point, commutation boundary, and auxiliary-network timing rather than by topology alone [15].

Induction heating and cooking have been a key application driver for high-frequency resonant inverters, motivating systematic comparisons of current-source and voltage-source realizations, phase-shift and fixed-frequency control, and load-adaptive tuning strategies [16,17,18]. Comprehensive reviews highlight the broad design space of single- and multiple-output resonant inverters and the central role of detuning relative to resonance for maintaining ZVS/ZCS under load drift [19,20,21,22]. The “multi-load/single-converter” viewpoint further illustrates how modal structure (multiple excitation paths and operating states) becomes a practical symmetry variable in zone-controlled systems [23,24,25].

Recent work has extended classical series-resonant half-bridge inverters using controlled reactive elements (e.g., variable transformers/inductors) and energy-recovery switches to enlarge the ZVS-feasible region at fixed switching frequency [26,27,28]. In parallel, current-fed resonant inverter platforms remain attractive in wireless power-transfer systems, where the input constraint is naturally current-like and where switching safety depends critically on detuning and commutation phase relations [29,30,31]. These application-driven studies consistently return to the same structural question: how do input constraints, detuning sign, switch-path reversibility, and mode structure co-determine commutation symmetry and stress redistribution?

Most existing analyses organize results along one dominant axis—topology families, control methods, or application constraints—while duality is often treated narrowly as VSI versus CSI [32,33]. Recent modeling contributions make this duality explicit in averaged and state-space form, highlighting the deeper structural correspondence between current- and voltage-excitation domains [34,35]. The present paper builds on this foundation by proposing a multidimensional symmetry hierarchy and a compact signature map that (i) unifies these axes and (ii) converts them into a design-oriented workflow.

Specific novelty relative to the author’s prior work. The present manuscript extends the author’s earlier symmetry/duality studies [4,5,6,36] in several non-redundant directions. First, it introduces an explicit multidimensional symmetry hierarchy operationalized through a compact inverter signature vector s = (σS, σF, σC, σP, σM) and corresponding symmetry operators (Section 2.5), which provide a reusable regime-level language beyond source duality alone. Second, it adds a symmetry-guided design workflow with compact screening metrics (e.g., k_V(AC), k_I(AC), k_RMS(AC), |φ|, m_ZVS, m_ZCS) that connect regime selection to commutation feasibility and stress/circulation trade-offs (Section 4.1 and Section 5). Third, it demonstrates the framework using an explicit extended-duality pairing of two application-oriented case studies (open-input super-resonant ZVS-like corridor and closed-input sub-resonant ZCS-like corridor), including device-class-aware screening implications for WBG platforms (Section 5.5, Section 5.6 and Section 5.7). Thus, while the paper builds on earlier duality/symmetry concepts, its contribution here is a regime-organizing and screening-oriented methodology that integrates signature formalization, operator-based pairing, and design interpretation in a single framework.

To make the novelty of the present manuscript more explicit relative to the author’s earlier studies on duality and symmetry in resonant converters,

Table 1. Positioning of the present manuscript relative to the author’s prior symmetry/duality studies.

Prior Work	Main Focus	What Was Established	Main Limitation	What Is Added in the Present Manuscript
Earlier duality-oriented study on resonant DC-AC inversion [5]	Basic dual interpretation between selected resonant inverter operating conditions	Introduced the idea that below-resonance and above-resonance operation may admit structured dual interpretation under changed source and commutation context	Duality remained primarily conceptual and was not expressed through an explicit regime signature formalism	Formal signature vector, explicit operator-based mapping, and structured regime-level comparison between open-input and closed-input operation
Earlier symmetry-oriented study on resonant inverter operation [36]	Qualitative symmetry/asymmetry interpretation of resonant operating intervals	Highlighted that operating behavior can be interpreted through mirrored or inverted regime patterns	Symmetry remained descriptive and was not extended into a broader transformation framework with screening metrics and dual-pair interpretation	Extended symmetry logic through source-side, frequency-side, and commutation-side operators, together with circulation/stress/margin descriptors
Present manuscript	Symmetry and extended duality in resonant DC-AC inverters below and above resonance	Unifies regime description through the signature vector (s = (σS, σF, σC, σP, σM)), introduces structured transformation operators, and evaluates dual regime pairs through screening-oriented stress and commutation metrics	Not intended as a full topology-isomorphism theory or complete experimental validation framework	Provides a regime-level formalism that combines symmetry interpretation, extended-duality mapping, screening indicators, and comparative analysis for both open-input and closed-input resonant inverter operation

summarizes the conceptual progression from prior work to the present contribution. The purpose of this comparison is not to restate previous results, but to clarify what was already established, what remained unresolved, and what is added here in terms of regime classification, formal operator structure, stress-oriented screening, and applicability to both open-input and closed-input operating conditions.

As shown in Table 1, the present manuscript goes beyond the earlier descriptive use of duality and symmetry by introducing a more explicit regime-level structure. In particular, the contribution of the paper lies in combining a formal signature representation, a bounded but useful transformation logic, and practical screening metrics for comparing paired operating regimes under source-condition and frequency-side inversion. This progression clarifies that the present work is not a simple restatement of earlier ideas, but a more structured extension of them. Accordingly, the manuscript does not attempt to replace converter-specific switched analysis; instead, it proposes a structured pre-synthesis and regime-screening framework intended to reduce ambiguity during the early comparison of resonant inverter operating classes.

It is also important to clarify the intended scope of this work. The paper does not propose a new circuit model of resonant inverters. The analytical relations used in the manuscript rely on well-established resonant-tank descriptions commonly employed in power electronics analysis (for example, series RLC representations and normalized detuning coordinates). The novelty of the present contribution lies instead in the regime-level organization of inverter operation through a symmetry-oriented framework that integrates source-domain interpretation, detuning side symmetry, commutation tendencies, and path feasibility into a unified signature representation.

In this sense, the proposed framework complements existing analytical models rather than replacing them, providing a structured language for organizing and comparing resonant inverter operating regimes.

The remainder of the paper is organized as follows. The Related Work and Positioning section positions the contribution relative to representative resonant inverter families and common analysis approaches. Section 2 introduces the symmetry framework and corresponding normalized regime coordinates. Section 3 formalizes extended inverter duality beyond source type. Section 4 interprets soft switching and stress distribution as global symmetry consequences. Section 5 develops a symmetry-guided design methodology and practical implications, and Section 6 concludes.

2. Symmetry Framework for Inverters

Inverters can be viewed as periodic cyber-physical dynamical systems in which switching actions and reactive energy exchange shape waveform structure and commutation boundary conditions. In the proposed framework, inverter operation is described through a hierarchy of symmetry domains: source-domain symmetry (input constraint), frequency-domain symmetry (detuning relative to resonance), commutation symmetry (soft-switching boundary alignment), switch-path symmetry (reverse-conduction capability), and modal symmetry (single- versus multi-mode operation). This hierarchy extends the commutation-centered symmetry viewpoint commonly used in quasi-resonant PWM converters—where local resonant transients are introduced to restore ZVS or ZCS—toward a broader regime-level interpretation in which the commutation environment emerges as a consequence of the selected resonant operating condition [1,2,3,4,5].

To visualize this hierarchy in a compact form, Figure 1 summarizes the principal symmetry axes used throughout the paper to classify resonant inverter operation. The figure is intended as a conceptual map rather than a strict mathematical diagram: it shows how source-side condition, detuning relative to resonance, commutation tendency, switch-path feasibility, and modal structure together define the multidimensional symmetry space within which the subsequent regime analysis is developed. This representation also clarifies that the proposed framework does not reduce inverter symmetry to a single soft-switching criterion but organizes it across several coupled operating dimensions.

2.1. Source-Domain Symmetry: Open-Input Versus Closed-Input Excitation

Resonant inverters are commonly classified by their input nature as open-input (voltage-fed) and closed-input (current-fed) structures [2,4]. Open-input inverters are driven by a voltage-dominated DC link (typically supported by a large capacitor), whereas closed-input inverters are driven by a current-dominated DC link (typically supported by a large inductor). In the proposed framework, this open-/closed-input distinction represents the source-domain duality axis, which coexists with frequency-domain, commutation, and modal dualities rather than defining inverter behavior on its own.

To make this source-domain distinction more explicit,

Table 2. Source-domain duality of resonant inverters: open-input versus closed-input structures.

Aspect	Open-Input (Voltage-Fed)	Closed-Input (Current-Fed)
DC-side excitation	Voltage-dominated source	Current-dominated source
Typical DC-link element	Large capacitor	Large inductor
Input characteristic	Input voltage approximately constant	Input current approximately constant
Energy flow constraint	Voltage constrained, current adapts	Current constrained, voltage adapts
Stress sensitivity (conceptual)	Load variation tends to appear as current stress	Load variation tends to appear as voltage stress
Relation to frequency regimes	Can operate sub-/near-/super-resonant	Can operate sub-/near-/super-resonant

summarizes the principal structural and interpretive differences between open-input and closed-input resonant inverter classes. The comparison is not intended as a complete topology taxonomy, but as a compact source-side reference that supports the subsequent symmetry mapping and extended-duality analysis. In particular, it highlights that the open/closed classification defines the source-domain operating character, while the full regime interpretation still depends on frequency detuning, commutation tendency, path feasibility, and modal structure.

As shown in Table 2, source-domain duality establishes the input-side operating character of the inverter but does not by itself determine the full commutation or modal behavior of the resonant regime.

To clarify the physical meaning of the source-side regime descriptor used in the proposed signature formalism, Figure 2 presents the two simplified equivalent source-side interpretations that underlie the regime comparison developed in this paper. In the open-input regime, the resonant inverter is interpreted as effectively voltage-source-fed, whereas in the closed-input regime it is interpreted as effectively current-source-fed. The figure is conceptual and intended to support regime interpretation rather than to provide a detailed switching-topology schematic.

Figure 2 should therefore be read as an interpretive aid for the source-side meaning of the regime descriptor, rather than as a taxonomy of converter implementations. Its role is to make explicit the input-side distinction that supports the extended-duality comparison developed in the following sections.

2.2. Frequency-Domain Symmetry: Sub-Resonant and Super-Resonant Regimes

A defining symmetry feature of resonant and quasi-resonant inverters is the dependence of behavior on the relation between operating angular frequency ω and resonant frequency ω₀. A compact detuning coordinate is δ = ω/ω₀. Sub-resonant operation (δ < 1) and super-resonant operation (δ > 1) form a dual pair, while δ = 1 is a symmetry-centered operating point. Crossing resonance reverses the sign of the effective reactance and exchanges the phase-leading/phase-lagging behavior between voltage and current [3,5].

For a series RLC tank, the impedance is Z(jω) = R + j(ωL − 1/(ωC)) [3,9]. In the sign convention used here, operation at ω = ω₀ = 1/√(LC) is the resonance-centered symmetry point where the reactive part vanishes and voltage and current are in phase. A convenient normalized description follows by defining the characteristic impedance Z₀ = √(L/C), the detuning ratio δ = ω/ω₀, and the quality factor Q = Z₀/R. Then the tank impedance can be written as Z(jω) = R[1 + jQ(δ − 1/δ)], and the fundamental phase shift is φ(δ,Q) = arctan(Q(δ − 1/δ)). Crossing δ = 1 flips the sign of φ, exchanging lead/lag relations and reshaping the commutation environment. This detuning sign therefore acts as a frequency-domain symmetry axis that partitions sub-resonant (δ < 1) and super-resonant (δ > 1) regimes.

To make the frequency-side interpretation more explicit, Figure 3 visualizes the resonance-centered symmetry structure induced by the detuning ratio δ. The figure is intended as a conceptual frequency-domain map showing that resonance (δ = 1) acts as the central symmetry point, while operation below and above resonance forms a dual regime pair with opposite phase orientation. In this way, the figure provides a compact visual anchor for the role of detuning as a primary symmetry axis in the proposed framework.

Figure 3 therefore makes explicit that the frequency-domain symmetry used in this paper is not merely a resonance condition, but a regime-partitioning principle that reshapes phase relation, commutation tendency, and the interpretation of dual operating states.

Example 1 (phase sign flip and regime labeling). 

Consider a series RLC tank with L = 20 μH and C = 100 nF, which yields f₀ = 1/(2π√(LC)) ≈ 112.5 kHz and Z₀ = √(L/C) ≈ 14.14 Ω. For an equivalent load resistance R = 5 Ω, the quality factor becomes Q = Z₀/R ≈ 2.83. Using φ(δ,Q) = arctan(Q(δ − 1/δ)), we obtain φ(0.8,2.83) ≈ −51.8° (capacitive, δ < 1), φ(1,2.83) = 0°, and φ(1.2,2.83) ≈ +46.0° (inductive, δ > 1). Thus, crossing δ = 1 flips the sign of φ and swaps lead/lag relations, which in turn re-labels the commutation tendency on the signature map (e.g., for a voltage-fed half-bridge with reverse conduction paths, δ > 1 is typically ZVS-favorable, whereas δ < 1 tends to shrink the ZVS window and may shift operation toward ZCS-like or hard-switching behavior, depending on σP and dead time).

In signature notation, one may label the two operating points as s(δ = 0.8) = (open-input, sub-resonant, ZCS-like, bidirectional path, single-mode) and s(δ = 1.2) = (open-input, super-resonant, ZVS-like, bidirectional path, single-mode), emphasizing that the commutation tendency σC is regime-dependent and naturally linked to the detuning sign σF.

2.3. Commutation Symmetry and Modal Symmetry

Regardless of topology, inverter commutation can be interpreted as a boundary condition on switching waveforms. Voltage-symmetric commutation (ZVS-like behavior) corresponds to turn-on near a zero-voltage boundary, while current-symmetric commutation (ZCS-like behavior) corresponds to turn-off near a zero-current boundary. In resonant inverters, these tendencies often emerge as consequences of frequency-domain phase relations.

Inverters also exhibit modal symmetry because energy transfer is distributed across spectral components. Single-mode operation is dominated by one resonant mode (or the fundamental component), whereas multi-mode structures introduce additional symmetry degrees of freedom through multiple resonant frequencies and mode coupling [3,5].

Figure 4 summarizes the combined source-domain and frequency-domain symmetry coordinates into a compact signature map that highlights the dual pairing of sub- and super-resonant operation for both open-input and closed-input resonant inverter structures. The map combines input-constraint symmetry (open-input/voltage-fed versus closed-input/current-fed) with frequency-domain symmetry (sub-resonant, near-resonant, and super-resonant operation). The sign of the effective tank reactance determines the lead/lag phase relation and typical ZVS-like or ZCS-like commutation tendencies (topology dependent).

Table 3. Six inverter regime classes generated by input-constraint symmetry and detuning symmetry (qualitative trends).

Source-Domain Class	Sub-Resonant (δ < 1)	Near Resonance (δ ≈ 1)	Super-Resonant (δ > 1)
Open-input (voltage-fed)	φ < 0 (capacitive) Phase relation: current leads voltage Commutation tendency: ZVS window typically shrinks; ZCS-like boundary alignment is often easier than ZVS (topology-dependent) Dominant “payment”: increased RMS circulation; possible switching-loss increase if commutation is forced	φ ≈ 0 (symmetry-centered) Commutation tendency: “balanced” but low margin; sensitive to drift (Q, dead time, parasitics) Dominant “payment”: margin-limited operation; mode transitions may appear	φ > 0 (inductive) Phase relation: current lags voltage Commutation tendency: ZVS-like turn-on windows commonly expand when reverse paths exist Dominant “payment”: increased current peaks and RMS circulation (circulating/RMS burden)
Closed-input (current-fed)	φ < 0 (capacitive) Commutation tendency: ZCS-like turn-off windows are often accessible in discontinuous/transition regimes (topology-dependent) Dominant “payment”: increased voltage excursion/clamp stress + increased tank loss at light load	φ ≈ 0 (symmetry-centered) Commutation tendency: low margin; commutation safety becomes parameter-sensitive Dominant “payment”: margin-limited operation; voltage stress can rise under drift	φ > 0 (inductive) Commutation tendency: ZVS-like or mixed soft-switching windows may exist depending on available reverse commutation paths and topology Dominant “payment”: voltage excursion typically dominates; clamp/diode paths become critical

Note: The table is qualitative and intended for regime screening. The labels “ZVS-like” and “ZCS-like” denote typical commutation tendencies; actual soft switching depends on commutation-path feasibility (availability of reverse commutation paths), dead time, parasitics, and the specific inverter topology/control.

condenses the regime-level consequences of the symmetry axes introduced above. By combining the input-constraint symmetry (open-input/voltage-fed vs. closed-input/current-fed excitation) with the detuning coordinate δ (sub-, near-, and super-resonant operation), the table provides a compact qualitative guide to phase behavior, commutation tendency, and stress/circulation redistribution (“cost of symmetry”).

Figure 5 provides a time-domain template that complements the frequency-domain symmetry map. Since φ(δ,Q) = arctan(Q(δ − 1/δ)) changes sign at δ = 1, the lead/lag relation between tank current and the switching function flips when crossing resonance. This flip is not merely descriptive: it changes the commutation environment and thus the typical soft-switching tendency. In particular, when reverse commutation paths exist (σP) and dead time is properly set, operation on the inductive side (δ > 1) often supports ZVS-like turn-on because resonant current can complete capacitive charge/discharge during commutation, whereas operation on the capacitive side (δ < 1) typically reduces that window and may require different timing or auxiliary measures.

2.4. Switch-Path Symmetry: With and Without Reverse Diodes

Beyond source- and frequency-domain symmetries, practical inverter realizations are strongly influenced by a device-level constraint: whether the switch leg provides a reverse-current path via antiparallel (reverse) diodes. This “switch-path symmetry” determines if the resonant current can naturally reverse through the switching network and how reactive energy is redistributed during dead times [5,7,11].

In open-input (voltage-fed) bridge inverters, antiparallel diodes enable freewheeling intervals and clamp the switch-node voltage during commutation. Depending on the operating point, diode conduction can invert the instantaneous output voltage and may also allow partial energy return to the DC link.

In resonant inverters, antiparallel diodes (or MOSFET body diodes) typically support full-wave current trajectories and widen the domain of soft-switching-friendly operation, particularly in super-resonant regimes where current reversal naturally completes the charge/discharge paths of device and tank capacitances.

In contrast, resonant inverters without reverse diodes (or employing reverse-blocking switch legs) constrain current reversal and often reduce accessible operating regimes to half-wave or truncated trajectories unless an alternative commutation path is provided. As a consequence, operating modes become more tightly tied to detuning (ω/ω₀), and forced commutation in continuous conduction tends to increase switching stress.

A useful symmetry-centered boundary regime occurs at ω = ω₀, separating ω < ω₀ (discontinuous trajectories with predominantly natural commutation) from ω > ω₀ (continuous trajectories with forced commutation and a hard-switching tendency).

Therefore, the presence/absence of reverse diodes can be interpreted as a device-level symmetry axis that acts as a feasibility filter on the regime map: it does not change the source-domain (open-/closed-input) or frequency-domain (sub/near/super resonance) coordinates, but it affects which symmetry classes are practically achievable and how the “cost of symmetry” is distributed.

To make the device-level role of the switching path more explicit,

Table 4. Device-level symmetry of the switching network: influence of reverse (antiparallel) diodes.

Aspect	With Reverse (Antiparallel) Diodes	Without Reverse Diodes/Reverse-Blocking Path
Current path through switch leg	Bidirectional current path in the switching leg (two-quadrant current conduction).	Current path is constrained (typically one-quadrant conduction or reverse-blocking); reverse current must be blocked or commutated through an auxiliary path.
Waveform symmetry in the AC current	Full-wave current trajectories (current can naturally change sign), enabling richer resonant symmetry.	Half-wave or truncated trajectories are common; time symmetry is constrained by the missing reverse-current path.
Energy handling during dead time	Freewheeling and reactive energy return can occur naturally; the switch-node voltage may be clamped by diode conduction and can invert depending on the operating point.	Dead-time intervals require alternative commutation paths; reactive energy return is limited or relies on auxiliary networks (snubbers/clamps).
Soft-switching tendency	ZVS-like commutation is often supported because resonant current can complete capacitive charge/discharge paths during commutation.	Natural ZCS-like turn-off may be achievable in discontinuous resonant regimes; ZVS-like behavior may require additional measures or strict timing.
Mode interpretation	Operation can smoothly span sub-/near-/super-resonant regimes with continuous current reversal in many resonant families (CCM is common).	Modes are strongly tied to ω/ω0: DCM (ω < ω0) with natural commutation; BCM (ω = ω0); CCM (ω > ω0) with forced commutation (hard-switching tendency).
Design implication	Broader feasible symmetry region but potential diode/recirculation losses; reverse recovery or body-diode behavior may matter.	Reduced reverse recovery concerns but narrower symmetry-access region and potentially higher stress in forced-commutation regimes.

summarizes how the presence or absence of reverse (antiparallel) diodes modifies the practical symmetry accessibility of resonant inverter operation. The comparison is intended to show that this device-level symmetry axis does not redefine the source-domain or frequency-domain coordinates of a regime, but strongly affects waveform continuity, commutation path availability, and the practical distribution of soft-switching “payment” and stress. In this sense, reverse-current capability acts primarily as a feasibility filter on the multidimensional regime map introduced earlier.

As shown in Table 4, device-level symmetry mainly determines whether a formally meaningful regime remains practically accessible, and under what commutation or stress penalty this accessibility is achieved.

2.5. Symmetry Operators and Inverter Signature Vector

To make the symmetry framework operational (and closer to a formal symmetry language), it is useful to define a compact signature vector that records the discrete symmetry choices associated with a given inverter realization and regime. Let s = (σS, σF, σC, σP, σM), where σS encodes the source-domain excitation (open- vs. closed-input), σF encodes the detuning side relative to resonance (sub- vs. super-resonant), σC encodes the commutation tendency (ZVS-like vs. ZCS-like), σP encodes switch-path reversibility (with vs. without reverse conduction), and σM encodes modal structure (single- vs. multi-mode). The signature components and their qualitative interpretation are summarized in

Table 5. Definition of the symmetry signature vector components used in the proposed framework.

Signature Component	Meaning (Symmetry Axis)	Typical Values	Design Interpretation
σS	Source-domain excitation	{open-input, closed-input}	Sets primary stress channel (current-like vs. voltage-like)
σF	Frequency-domain detuning side	{δ < 1 (sub), δ > 1 (super)}	Sets sign of reactive behavior; swaps lead/lag relations
σC	Commutation tendency	{ZVS-like, ZCS-like}	Indicates whether soft switching is achieved via voltage or current boundary alignment
σP	Switch-path reversibility	{bidirectional, unidirectional}	Determines freewheeling symmetry and commutation path availability
σM	Modal structure	{single-mode, multi-mode}	Indicates whether operation is governed by one mode or by mode transitions

.

With this notation, classical duality transformations can be interpreted as operators that flip selected signature components. For example, source duality (VSI ↔ CSI) exchanges voltage and current variables and swaps the energy storage roles of capacitors and inductors, which corresponds to σS inversion; detuning inversion corresponds to σF inversion; and commutation duality corresponds to σC inversion. This operator viewpoint provides a concise bridge between the descriptive maps (Figure 1, Figure 2 and Figure 3) and the design workflow developed in Section 5.

To make the extended-duality viewpoint explicit and reusable,

Table 6. Symmetry operators acting on the inverter signature vector (conceptual).

Operator	Action on Signature Vector s = (σS, σF, σC, σP, σM)	Meaning (What Is Flipped)	Typical Regime-Level Consequence
D_S	D_S(s) = (¬σS, σF, σC, σP, σM)	Source-domain duality (open-input ↔ closed-input)	Shifts dominant stress “payment” channel (current-like ↔ voltage-like) and changes natural normalization references (UDC ↔ IDC).
D_F	D_F(s) = (σS, ¬σF, σC, σP, σM)	Detuning side inversion (δ < 1 ↔ δ > 1; φ → −φ)	Swaps lead/lag relations; changes commutation environment and may move the operating point between ZVS-favorable and ZCS-favorable corridors.
D_C	D_C(s) = (σS, σF, ¬σC, σP, σM)	Commutation tendency flip (ZVS-like ↔ ZCS-like)	Exchanges which boundary is “protected” (voltage vs. current) and re-labels the dominant stress trade.
D_P	D_P(s) = (σS, σF, σC, ¬σP, σM)	Switch-path symmetry flip (bidirectional ↔ unidirectional reverse path)	Acts as a feasibility filter: restricts current reversal/freewheeling, shrinks soft-switching regions, and may enforce additional modes/auxiliary paths.
D_M	D_M(s) = (σS, σF, σC, σP, ¬σM)	Modal-structure change (single-mode ↔ multi-mode)	Introduces mode boundaries (start-up/light-load transitions), altering commutation margins and circulation/RMS burden.
D_ext (example composition)	D_ext = D_S ∘ D_F ∘ D_C	One “fully dual” pairing	Maps an open-input super-resonant ZVS-like signature to a closed-input sub-resonant ZCS-like signature under the adopted sign convention (trend-oriented).

Here, ¬ denotes the binary flip (complementary state) of the corresponding signature component (e.g., open ↔ closed, sub ↔ super, ZVS-like ↔ ZCS-like, etc.). It does not denote logical negation in the strict Boolean sense. The symbol ∘ denotes operator composition, applied from right to left.

defines a minimal set of symmetry operators acting on the signature vector s = (σS, σF, σC, σP, σM). Each operator flips one symmetry axis, while compositions generate dual regime pairings. These operators are descriptive rather than prescriptive: σP and σM act as feasibility filters, and specific topologies/control laws determine which signatures are practically attainable.

The operator view is intended for regime organization and does not imply that every topology supports every signature without additional commutation paths or control constraints.

Example 2 (extended-duality pairing in signature space). 

Consider an operating signature: s₁ = (open-input, super-resonant, ZVS-like, bidirectional path, single-mode), which is representative of a voltage-fed bridge operated on the inductive side (δ > 1) with feasible reverse commutation paths. Applying the composed operator D_ext = D_S ∘ D_F ∘ D_C yields, s₂ = D_ext(s₁) = (closed-input, sub-resonant, ZCS-like, bidirectional path, single-mode). This pairing expresses, at regime level, how source-domain duality, detuning side inversion, and commutation-tendency inversion jointly map a ZVS-favorable operating corridor into its ZCS-favorable dual corridor under the adopted sign convention for φ(δ,Q).

In this interpretation, σP and σM do not generate duality by themselves; instead, they act as feasibility/robustness filters that determine whether a given signature is practically attainable and stable under drift.

2.6. Remarks on Operator Properties, Applicability, and Limits

The symmetry and duality operators introduced in this work are intended as regime-level descriptive mappings, not as a complete algebraic synthesis theory for all resonant inverter topologies. Their purpose is to organize operating regimes, reveal structured correspondences, and support early-stage interpretation of stress, commutation tendency, and dual operating behavior. In this sense, the framework is deliberately intermediate in scope: more structured than a purely qualitative analogy, but less general than a full graph-theoretic or network-theoretic equivalence formalism.

A useful distinction must therefore be made between descriptive commutation of operators and practical realizability of the corresponding transformed regime. At the descriptive level, operators such as frequency-side inversion and source-side inversion may be composed to generate meaningful regime pairings in the signature space. However, the physical interpretation of the transformed regime still depends on whether the resulting topology, current path, and switching sequence remain feasible under the relevant device, source, and resonant-tank constraints. Thus, operator composition is meaningful as a structured interpretive tool, but it does not guarantee direct implementability without additional topological and control verification.

Within this regime-level perspective, several quantities can be regarded as practical invariants or semi-invariants. These include:

(1)

the dimensional structure of the regime signature vector;

(2)

the resonance-centered interpretation of δ = ω/ω₀ as a separator between below-resonance and above-resonance behavior;

(3)

the descriptive pairing logic produced by combined source, frequency, and commutation inversion;

(4)

the normalized interpretation of stress and commutation screening metrics as comparative indicators across related operating regimes.

At the same time, quantities such as soft-switching feasibility, current circulation severity, and stress distribution are not strict invariants; they are precisely the properties whose redistribution motivates the use of the extended-duality mapping.

The commutativity of the operators must also be interpreted with care. At a descriptive level, D_S and D_F may often be applied in either order without changing the broad regime interpretation, since they act on different semantic components of the operating signature. By contrast, operators associated with commutation tendency, path availability, and modal structure are more sensitive to contextual constraints. In particular, D_C, D_P, and D_M should not be interpreted as universally commuting in a strict algebraic sense, because the feasibility of a transformed commutation regime depends on path continuity, resonant current polarity, device conduction direction, and control timing. For this reason, the present manuscript does not claim a complete commutative operator algebra; rather, it proposes a structured transformation logic whose applicability is bounded by converter topology and operating regime.

This is especially important for the roles of σP and σM. In the present formulation, these terms are best understood as feasibility and robustness descriptors, not as primary duality generators. The path descriptor σP indicates whether the transformed regime preserves or loses a physically meaningful resonant current path, while the modal descriptor σM indicates whether the regime remains structurally coherent across the interval of operation or undergoes boundary-sensitive modal transition. In other words, these descriptors act as filters on the practical usefulness of a regime transformation rather than as independent sources of duality.

The limits of the framework should therefore be stated explicitly. First, the proposed operators do not establish circuit isomorphism in the strict topological sense. Second, parasitics, dead time, nonlinear output capacitance, reverse recovery effects, and layout-dependent current paths may degrade or even invalidate an otherwise neat descriptive pairing. Third, mode transitions near resonance or near conduction-boundary conditions may destroy simple dual correspondence even when the signature-level mapping remains formally meaningful. Accordingly, the framework should be interpreted as a regime-screening and organization tool that supports insight, comparative reasoning, and early-stage design exploration, while detailed waveform verification, non-ideal simulation, and experimental assessment remain necessary for final engineering validation.

For these reasons, the extended-duality formalism proposed in this paper should be interpreted as a structured methodology for mapping, screening, and comparing resonant DC-AC inverter operating regimes under source-condition and frequency-side inversion. The additional path and modal descriptors are introduced primarily to assess practical feasibility and regime consistency.

It should also be emphasized that the purpose of the proposed symmetry operators is not to introduce a new analytical model of resonant converters. Instead, the operators provide a structured language for organizing and comparing operating regimes that are already described by classical resonant-tank models and switching analysis. In this sense, the framework complements existing modeling approaches rather than replacing them.

3. Extended Duality in Inverter Operation

Duality has long been used as an organizing principle in power electronics, most commonly framed as the correspondence between voltage-source and current-source structures (VSI vs. CSI) and their associated network duals [2,3]. Beyond conceptual symmetry, recent work formulates the VSI ↔ CSI correspondence explicitly at the averaged model level, showing how the underlying state-space dynamics transform under source duality [35]. In the present framework, inverter duality is extended by composing source-domain duality with frequency-domain detuning symmetry, commutation symmetry, and switch-path symmetry, leading to a higher-dimensional and regime-aware notion of “dual operation”.

A complementary unification viewpoint treats resonant inverters as RLC-centered converters, in which source type (open-input versus closed-input), frequency detuning (δ), and commutation tendencies can be interpreted within a single impedance-symmetry model. In this sense, the regime map in Figure 3 is naturally connected to the classical VSI/CSI distinction by viewing VSI and CSI as limiting cases obtained by constraining the reactive elements: C → ∞ yields a voltage-source (aperiodic) limit, whereas L → ∞ yields a current-source (hard-resonant) limit. This transition is illustrated in Figure 6 [4,6].

4. Soft Switching and Stress Distribution as Global Symmetry Consequences

The mathematical expressions used in this section follow standard resonant-tank relations widely used in the analysis of resonant power converters. These expressions are not introduced as new models, but rather as a common analytical basis that allows the symmetry-based regime interpretation to be expressed in a compact and comparable form.

Soft switching in resonant inverters is often presented as a design objective achieved through specific circuit arrangements or modulation strategies. Within the symmetry-based view, soft switching is interpreted as a global consequence of symmetry selection in the combined source-frequency–commutation space.

Voltage-symmetric (ZVS-like) commutation emerges when the switching-node voltage is naturally driven toward a near-zero boundary before turn-on via resonant charge/discharge processes. Current-symmetric (ZCS-like) commutation emerges when resonant current trajectories naturally cross zero near turn-off. In many resonant inverter applications, these behaviors are regime consequences governed by detuning and load phase rather than independent goals [2,35].

Importantly, symmetry restoration redistributes stress. When commutation symmetry protects one variable at the switching boundary, the conjugate variable typically experiences increased peak or RMS stress during the resonant interval. Thus, soft switching should not be interpreted as a lossless improvement, but as a trade between reduced switching losses and increased conduction/reactive losses or stress. This perspective motivates the notion of a cost of symmetry, expressed in stress margins and circulating energy. Section 4.1 formalizes these tendencies using normalized stress, circulation, and margin metrics [3,5].

4.1. Symmetry-Based Stress, Circulation, and Margin Metrics

To complement the qualitative symmetry axes introduced in Section 2 and the extended-duality discussion in Section 3, it is useful to attach compact, dimensionless metrics to inverter operating regimes. The purpose of these metrics is not to replace topology-specific loss models, but to provide symmetry-sensitive indicators that (i) quantify the commutation-stress “payment”, (ii) capture the circulating/RMS burden associated with resonant shaping, and (iii) express robustness margins under detuning and parameter drift.

Let u_sw(t) denote the switch-node voltage and i_sw(t) the switch current in a representative semiconductor device (or bridge leg) over one steady-state period. Let U_DC and I_DC denote the DC-link voltage and current, used as natural normalization references for open-input (voltage-fed) and closed-input (current-fed) excitation, respectively. Let I₁ denote the RMS value of the fundamental component of the AC tank/load current. On this basis, the following minimal metric set is introduced.

Commutation-stress factors (boundary-centered). We define the normalized peak-voltage stress factor and peak-current stress factor as:

k_V(AC) = max |u_sw(t)|/U_DC

k_I(AC) = max |i_sw(t)|/I_DC

These factors quantify the peak commutation stress associated with restoring a given commutation symmetry tendency. Regimes that are ZCS-like often shift the burden toward higher switch-node voltage excursions (higher k_V(AC)), whereas regimes that are ZVS-like often require resonant current trajectories that increase current peaks (higher k_I(AC)). The symmetry map predicts this directionality at family level, while topology-dependent details set the numerical magnitude.

RMS/circulation factor (cost of symmetry). Soft switching reduces switching loss but generally redistributes burden into conduction and reactive circulation. To express this effect, we define an RMS circulation factor normalized to the fundamental load current:

k_RMS(AC) = I_sw,rms/I₁

When k_RMS(AC) > 1, the switching network carries additional circulating current beyond what is needed to deliver the fundamental load power, which typically maps into increased conduction loss (in switches and passive elements) and increased tank loss. Under a fixed on-resistance (or equivalent static conduction model), conduction-related loss scales approximately with I_rms²; thus, the penalty associated with RMS inflation scales as k_RMS(AC)².

Frequency-domain phase margin. Because detuning relative to resonance is a primary symmetry axis, the fundamental phase shift provides a compact robustness handle. For a series-RLC interpretation of the tank (Section 2.2), the phase shift can be written as [5]:

φ(δ,Q) = arctan(Q(δ − 1/δ)), where δ = ω/ω₀ and Q = Z₀/R with Z₀ = √(L/C)

Crossing δ = 1 flips the sign of φ, exchanging lead/lag relations and reshaping the commutation environment. From a design viewpoint, |φ| provides a commutation “margin”: maintaining |φ| ≥ φ_min over the expected operating corridor (load drift, component tolerances, and temperature variation) preserves the intended detuning side symmetry and reduces the risk of mode transitions that invalidate soft-switching expectations.

Boundary-alignment margin metrics (commutation feasibility). In addition to peak/RMS stress and detuning margin, practical soft switching requires boundary alignment at the switching instants. To express this requirement in a compact, implementation-agnostic form, we define two dimensionless boundary-alignment margins.

ZVS-like boundary margin. Let Q_eq denote the effective charge swing required to commutate the switch-node voltage to (or near) zero before turn-on (e.g., based on device/node charge data at U_DC). Let i_comm(t) denote the commutating current available during dead time (typically a tank/leg current component that charges/discharges the effective node capacitances). Over the allocated dead-time interval DT, the available net commutating charge is:

$$Q_{av}=|{\displaystyle {\int }_0^{t_{DT}}{i}_{comm}}(t)dt|$$

The ZVS-like boundary-alignment margin is then defined as:

$$m_{ZVS}={\displaystyle \frac{Q_{av}}{Q_{eq}}}$$

A first-order estimate often used for screening is $m_{ZVS}\approx \left|I_{comm}\right|t_{DT}/Q_{eq}$ when i_comm(t) is approximately constant over DT.

ZCS-like boundary margin. Let i_start denote the switch-path current at the start of the turn-off commutation interval CT. Let L_eq be an equivalent commutation inductance governing the current change during CT and let u_L(t) be the corresponding voltage across this inductance (topology/control dependent). The available magnitude of current change during CT is:

$$\mathsf{\Delta }{i}_{av}=|{\displaystyle \frac{1}{L_{eq}}}{\displaystyle {\int }_0^{t_{CT}}{u}_L}(t)dt|$$

The ZCS-like boundary-alignment margin is defined as:

$$m_{ZCS}={\displaystyle \frac{\mathsf{\Delta }{i}_{av}}{\left|i_{start}\right|}}$$

A first-order screening estimate is $m_{ZCS}\approx U_{eq}{t}_{CT}/(L_{eq}|i_{start}|)$, when u_L(t) ≈ U_eq over CT.

In this interpretation, m_ZVS ≥ 1 indicates sufficient commutation “effort” to reach u_sw ≈ 0 within dead time, while m_ZCS ≥ 1 indicates sufficient volt–second action to drive the current to (or through) zero before turn-off. Both margins are intended for regime screening and robustness reasoning under drift (load/Q, detuning, parasitics), rather than as replacements for detailed time-domain verification.

The metric definitions and their design interpretation are summarized in

Table 7. Symmetry-based metrics for DC-AC inverters: stress, circulation, detuning margin, and boundary-alignment margins (qualitative).

Metric	Definition	Symmetry Axis	Main Meaning	Typical “Payment”
kV(AC)	max |usw|/UDC	σS, σC	Peak voltage stress at commutation	Switch voltage rating; clamp/diode stress
kI(AC)	max |isw|/IDC	σS, σC	Peak current stress at commutation	Switch current rating; thermal burden
kRMS(AC)	Isw,rms/I1	σF, σM, σP	Circulating-current inflation	Conduction + tank losses (RMS “cost of symmetry”)
|φ|	|arctan(Q(δ − 1/δ))|	σF	Detuning/commutation margin	Robustness vs. drift; preserves regime sign
mZVS	Qav/Qeq	σC, σP, σF	Charge-based boundary-alignment margin for achieving usw ≈ 0 at turn-on	Requires commutation current and/or longer dead time; may increase circulation and RMS conduction burden
mZCS	iav/|istart|	σC, σP, σF	Volt–second boundary-alignment margin for driving isw → 0 before turn-off	May require voltage excursion/commutation interval; may increase voltage stress and clamp/tank stress

Note: Q_eq is preferably evaluated using device/node charge data (e.g., Q_oss information at U_DC) rather than a linear capacitance approximation. The quantities i_comm(t), L_eq, and u_L(t) depend on the specific inverter topology and commutation path (σP) and are therefore used here as equivalent screening variables.

.

Illustrative dual examples (method demonstration). The following half-sinusoidal examples are intentionally illustrative and local to the dominant commutation interval; they demonstrate symmetry-induced RMS/peak inflation trends rather than full-period loss calculations.

Current-domain illustration (ZVS-like RMS inflation). Assume a commutation-stage current approximated over its dominant interval by a half-sinusoid i(t) = I_pk·sin(ωt), 0 ≤ ωt ≤ π. Its RMS value over that interval is I_pk/√2. If, illustratively, enforcing a ZVS-like boundary requires I_pk = 2·I₁, then k_RMS(AC) ≈ (2/√2) ≈ 1.41, and the conduction-loss penalty scales as k_RMS(AC)² ≈ 2.0 for a fixed on-resistance model.

Voltage-domain dual illustration (ZCS-like voltage excursion). Analogously, assume a commutation-stage switch-node voltage approximated by u(t) = U_pk·sin(ωt), 0 ≤ ωt ≤ π, with RMS value U_pk/√2. If enforcing a current-symmetric (ZCS-like) boundary requires U_pk = 2·U_DC, then k_V(AC) = 2 and a corresponding RMS-based voltage factor evaluates to (2/√2) ≈ 1.41. This dual example mirrors the current-based case and reinforces the “cost of symmetry” interpretation: ZVS-like regimes tend to pay primarily through increased current peaks and RMS circulation, whereas ZCS-like regimes tend to pay primarily through increased voltage excursions.

Taken together, these metrics provide a compact quantitative layer above the signature map: they enable early screening of feasible commutation classes, identification of the dominant stress channel, and prioritization of detailed circuit-level modeling in the subsequent symmetry-guided design workflow (Section 5).

4.2. Recommended Use of the Symmetry Formalism in Engineering Screening

The proposed symmetry formalism is intended to be used as a structured engineering screening tool rather than as a substitute for topology-specific switched analysis. Its practical role is to reduce ambiguity during early-stage regime comparison by organizing source-side interpretation, frequency-side detuning, commutation tendency, path feasibility, and modal coherence within a single descriptive framework.

A practical use sequence can be summarized in four steps. First, the candidate regime is classified using the signature vector s = (σS, σF, σC, σP, σM), which identifies the source-domain excitation, detuning side relative to resonance, intended commutation orientation, reverse-path feasibility, and modal structure. Second, the nominal regime is screened using the comparative indicators k_I(AC), k_V(AC), k_RMS(AC), |ϕ|, m_ZVS and m_ZCS, which identify the source-domain excitation, cost, stress redistribution, and commutation feasibility. Third, the screened regime is interpreted as margin-rich, boundary-sensitive, or stress-dominated, depending on whether the relevant commutation margin remains comfortably above unity or approaches the practical threshold. Fourth, only the most promising candidates are carried forward to more detailed non-ideal waveform simulation, timing-sensitivity assessment, and hardware-oriented validation.

In this role, the formalism does not claim to determine the final converter implementation directly. Instead, it provides a compact regime-screening layer that helps narrow the candidate operating space before more expensive validation steps are undertaken. This staged interpretation is particularly useful when several inverter families or detuning corridors must be compared under similar commutation or stress objectives.

5. Design Implications

The proposed symmetry framework is intended to be actionable: it turns qualitative regime selection into a structured methodology that connects (i) input constraints, (ii) detuning side, and (iii) device-level commutation paths to the expected soft-switching tendency and dominant stress/loss channel. The normalized stress/circulation and phase-margin metrics introduced in Section 4.1 provide compact quantitative handles for this screening.

5.1. Symmetry-Guided Design Methodology

The methodology starts by choosing the primary symmetry constraint imposed by the surrounding system. If the front end naturally behaves as a stiff voltage source (large DC-link capacitor), a voltage-fed (open-input) inverter is a natural match; if it behaves as a stiff current source (large DC-link inductor), a current-fed (closed-input) inverter is natural. The signature then guides the subsequent choices of tank type and operating region.

Next, detuning is treated as a symmetry control knob rather than an afterthought. Near resonance (δ ≈ 1) the tank is symmetry-balanced (small reactive part), often yielding good efficiency and reduced stress, but potentially reduced commutation margin. Moving away from resonance increases |φ| and may strengthen a particular commutation tendency, at the expense of increased RMS circulation and sensitivity. The map therefore suggests selecting a detuning corridor that preserves the desired sign of φ while meeting power regulation needs.

Finally, device-level symmetry (σP) and modal structure (σM) are checked. For example, antiparallel diodes may be essential to guarantee the intended commutation path during dead time, while start-up and light-load operation may introduce additional modes that require explicit treatment rather than being viewed as “exceptions”. Current-fed resonant inverter implementations in wireless power-transfer systems illustrate how blocking diodes and overlap-time management can become part of the symmetry signature that ensures safe commutation under frequency drift [31,32,33,34].

5.2. Symmetry-First Workflow and Robustness Checks

A key point is that the frequency-domain phase relation φ(δ,Q) provides a quantitative handle on frequency-domain symmetry: the sign of φ fixes whether the tank is effectively inductive or capacitive, while |φ| provides a commutation “margin.” In practice, designers may specify a minimum phase margin |φ| ≥ φ_min at the switching instants to maintain ZVS/ZCS under parameter drift (e.g., component tolerances, temperature variation, and load-dependent Q). Within this workflow, the symmetry signature s becomes a compact label for the assumptions that must remain invariant across the operating range.

When a fixed-frequency strategy is required (EMI constraints, magnetic design, or system-level synchronization), the map clarifies which additional degree of freedom must compensate for load drift: reactive-element control, phase shift, pulse density modulation, or auxiliary commutation networks that enlarge the symmetry-feasible region without changing the fundamental operating frequency [27,28,29,30].

To translate the proposed symmetry formalism into a more design-oriented perspective,

Table 8. Symmetry-first design workflow enabled by the proposed signature map (qualitative).

Step	Symmetry Question (Input)	Practical Output (Design Decision)
1	What is the feasible input constraint? (σS)	Choose open-input (voltage-fed) or closed-input (current-fed) excitation based on the front-end and energy buffer.
2	Where is the target commutation window relative to resonance? (σF)	Pick a detuning corridor (δ-range) that preserves the desired reactive sign under load drift.
3	Which commutation boundary is desired? (σC)	Target ZVS-like or ZCS-like operation; translate into required phase sign and margin.
4	Is reverse conduction allowed/available? (σP)	Decide on antiparallel diodes/body-diodes vs. reverse-blocking devices; verify freewheeling paths.
5	Is single-mode sufficient? (σM)	If mode transitions are unavoidable (start-up/light-load), include modal boundaries as additional design constraints.

summarizes a qualitative symmetry-first workflow derived from the signature map. The purpose of the table is not to prescribe a rigid synthesis algorithm, but to show how the regime descriptors (σS, σF, σC, σP, σM) can be used as a structured sequence of engineering questions that guide source-side selection, detuning choice, commutation targeting, device-path feasibility, and modal robustness. In this way, the symmetry map is connected more explicitly to early-stage inverter design reasoning.

As shown in Table 8, the proposed symmetry formalism is useful not only for regime interpretation, but also as a compact pre-synthesis framework for organizing early-stage resonant inverter design decisions.

To further delimit the intended use of the proposed framework,

Table 9. Scope, strengths, and limitations of the proposed regime-level symmetry formalism.

Aspect	What the Framework Captures Well	What Still Requires Detailed Validation
Source-side interpretation	Distinction between open-input and closed-input regime character	Actual front-end implementation, dynamic source interaction, and converter-specific realization
Frequency-side symmetry	Sub-resonant, near-resonant, and super-resonant regime pairing	Exact switching loss and dynamic behavior under non-ideal device models
Commutation tendency	ZVS/ZCS-oriented screening and relative commutation favorability	Dead-time sensitivity, parasitic inductance, nonlinear capacitance, and exact switching transitions
Stress redistribution	Relative “payment” shift between current stress and voltage stress	Absolute stress magnitudes, thermal loading, and device-safe operating limits
Path feasibility	Whether reverse-current capability or commutation return paths are structurally supported	Full waveform evolution under realistic conduction and recovery behavior
Modal behavior	Identification of single-mode versus boundary-sensitive or multi-mode regime structure	Detailed transient mode transition dynamics and control-driven mode interaction
Design use	Early-stage regime selection and topology-screening guidance	Final converter synthesis, layout optimization, and hardware qualification

summarizes what the regime-level formalism captures well and what still requires detailed converter-specific validation. This clarification is important because the value of the method lies in structured comparison and screening, not in replacing switched-model analysis or experimental engineering verification.

As shown in Table 9, the strength of the proposed symmetry formalism lies in early-stage regime organization, qualitative comparison, and screening-oriented engineering reasoning. Its limitation is equally important: final converter acceptance still depends on detailed switched-model simulation, parasitic-aware timing analysis, and application-specific validation.

5.3. Practical Design Conveniences

The main practical benefit of the symmetry map is that it provides quick, topology-agnostic screening rules before detailed time-domain design:

• Open-input (voltage-fed) realizations tend to “pay” for soft commutation in current stress; closed-input (current-fed) realizations tend to pay in voltage stress. This guides early semiconductor and passive sizing.
• For series-resonant voltage-fed bridges, super-resonant (δ > 1) operation is typically ZVS-favorable because the tank appears inductive and diode/freewheel paths naturally pre-commutate device capacitances; the dual current-fed case tends to favor ZCS under the corresponding detuning sign.
• Reverse diodes (or MOSFET body diodes) are not a minor implementation detail: they change the admissible commutation paths and therefore the effective symmetry class σP, especially near the resonance-centered boundary δ ≈ 1.
• A robust design target is not a single operating point but a symmetry-feasible region in (δ,Q) where the phase sign is preserved and the commutation margin is nonzero. Fixed-frequency control strategies can be interpreted as maintaining this region while regulating power by pulse density or phase shift.

5.4. Topology and Regime Selection Heuristics

Practitioners often ask a forward design question: given a target load corridor and a semiconductor platform, which inverter family is the most natural starting point? Although the symmetry map is intentionally topology-agnostic, it supports compact selection heuristics that mirror the ZVS/ZCS trade intuition in quasi-resonant DC–DC converters: protecting the voltage boundary (ZVS-like) typically increases current peaks and RMS circulation (k_I(AC), k_RMS(AC)), whereas protecting the current boundary (ZCS-like) typically increases voltage excursion (k_V(AC)). Device physics often provides the first commutation preference: MOSFET-based high-frequency legs tend to benefit from ZVS-like turn-on because of reduced capacitive switching loss, whereas IGBT-based high-power legs may benefit from ZCS-like turn-off to mitigate tail-current-related losses. Load drift primarily acts through the effective quality factor Q and detuning δ, often shrinking |φ| at lighter loading (larger effective R); therefore, |φ| should remain at or above φ_min over the expected load range to preserve the intended commutation tendency (Section 4.1).

To make this practitioner-oriented selection logic more explicit,

Table 10. Symmetry-guided topology and regime-selection heuristics (qualitative).

Scenario/Dominant Constraint	Recommended Symmetry Target (Signature Hints)	Practical Starting Point and Main Check Metric
High-frequency MOSFET inverter with stiff DC voltage bus; priority: ZVS-like turn-on across load drift	σS = open-input; σF: inductive side (φ > 0, often δ > 1); σC = ZVS-like; σP: reverse paths enabled; σM: single-mode	Voltage-fed series-resonant half-/full-bridge (Class-D/SRC family); check kI(AC), kRMS(AC), and |φ| margin.
High-power IGBT inverter or strong turn-off constraint; priority: ZCS-like turn-off	σS per front-end; σF: ZCS-favorable corridor (typically φ < 0); σC = ZCS-like; σP/clamp paths mandatory	Current-fed resonant inverter or commutated tank enforcing current zero; watch kV(AC) and clamp/diode stress; keep |φ| margin.
Open-circuit risk (detachable load, weak coupling/misalignment in WPT)	Prefer σS = open-input (or include explicit overvoltage protection in closed-input designs); preserve commutation margin	Voltage-fed resonant inverter with intrinsic current limiting by the tank; verify no-load kI(AC), kRMS(AC), and voltage peaks.
Short-circuit/low-impedance transients (start-up, fault)	Prefer σS = closed-input (current-limited) or add explicit current limiting for open-input designs	Current-fed inverter or voltage-fed with input inductor/limiter; evaluate kV(AC) under faults and associated clamp stress.
Fixed-frequency operation with wide load corridor (large Q variation)	Preserve sign (φ) and maintain |φ| ≥ φmin; consider σM = multi-mode and σP paths near δ ≈ 1	Use phase-shift/pulse-density/burst control or auxiliary reactive control; screen the corridor using φ(δ,Q) and kRMS(AC).
Reverse-blocking devices/limited reverse current paths	σP = without reverse conduction; commutation must be forced or alternative return paths must be added	Resonant-pole/auxiliary commutation networks; check both kV(AC) and kI(AC) and verify feasible commutation trajectories.

summarizes representative engineering scenarios together with the corresponding symmetry targets and first design checks. The table is not intended as a rigid design prescription, but as a compact guide showing how dominant constraints—such as semiconductor type, load uncertainty, fault exposure, fixed-frequency operation, or reverse-path limitations—map onto preferred regime choices within the proposed symmetry framework.

As shown in Table 10, the proposed symmetry framework can support not only descriptive regime classification, but also early topology-screening decisions by linking source-side choice, commutation objective, and stress-oriented verification metrics.

Practical note (quick estimation). For series-RLC-dominated tanks, the phase relation φ(δ,Q) can be estimated directly from nominal L, C and the expected equivalent-load corridor R, providing an immediate regime pre-check: the sign of φ selects the commutation tendency, while |φ| provides a robustness margin. A first-order circulation estimate can be obtained by relating I_sw,rms to the fundamental load current I₁ via waveform factors (e.g., half-sinusoidal commutation segments yield k_RMS(AC) ≈ I_pk/(√2·I₁)). If the resulting k_RMS(AC)² penalty becomes unacceptable at the target power level, the symmetry map suggests two systematic relief options: (i) shift the commutation tendency toward the dual boundary (ZVS-like ↔ ZCS-like), accepting the conjugate stress channel; or (ii) move to a different source constraint (open ↔ closed) or modal structure (single ↔ multi) so that commutation is protected without excessive circulation.

These heuristics formalize common inverter-design intuition into a symmetry-consistent selection step, allowing detailed circuit- and control-level optimization to be focused on the most structurally plausible regime class.

For fast early-stage screening, Figure 7 provides a compact, signature-driven decision tree that maps typical application constraints into a candidate symmetry signature s and highlights the primary check metrics.

5.5. Case Study A: Wide-Bandgap Voltage-Fed Series-Resonant Half-Bridge Above Resonance (ZVS Corridor and Q_oss Sensitivity)

This case study operationalizes the signature-guided workflow in a device-relevant setting by explicitly connecting the ZVS-like boundary-alignment margin m_ZVS to wide-bandgap (WBG) semiconductor node-charge characteristics. The target regime signature is sA = (open-input, super-resonant, ZVS-like, bidirectional path, single-mode), representing a voltage-fed bridge operated on the inductive side of resonance with reverse current paths available (σP).

Tank and regime coordinates. To preserve comparability with Example 1, the same series RLC tank is used: L = 20 μH and C = 100 nF (f₀ ≈ 112.5 kHz, Z₀ ≈ 14.14 Ω). The normalized detuning coordinate is δ = ω/ω₀ and the quality factor is Q = Z₀/R. The tank impedance is Z(jω) = R[1 + jQ(δ − 1/δ)], with phase shift φ(δ,Q) = arctan(Q(δ − 1/δ)). For a half-bridge producing a square output voltage ±U_DC/2, the RMS value of the fundamental component is V_1,rms = (√2/π)U_DC, yielding I_1,rms = V_1,rms/|Z| and I_pk = √2·I_1,rms.

WBG-linked ZVS screening margin. In the symmetry-based metric layer (Section 4.1), ZVS-like boundary alignment is captured by a charge-based margin m_ZVS = Q_av/Q_eq. For early-stage screening, Q_av can be approximated as |i_edge|·DT, where DT is the dead time and i_edge is the commutating current available during DT. Using a fundamental-only approximation, |i_edge| ≈ I_pk·|sinφ|. The effective node-charge swing Q_eq is preferably evaluated using device output-charge data at U_DC (e.g., Q_oss) rather than a linear capacitance approximation. For a symmetric half-bridge leg, a practical screening approximation is Q_eq,leg ≈ Q_oss,H(U_DC) + Q_oss,L(U_DC) ≈ 2·Q_oss,device(U_DC).

Table 11. Representative WBG device-class output-charge values used for ZVS screening.

Device Class	Voltage Class	Qoss,device at UDC (nC)	Qeq,leg ≈ 2·Qoss,device (nC)	Comment
Si SJ MOSFET-like	650 V	200	400	Higher node charge; ZVS corridor shrinks (screening trend)
SiC MOSFET-like	1200 V	80	160	Moderate node charge; robust at medium/heavy load
GaN HEMT-like	650 V	20	40	Low node charge; ZVS corridor expands toward δ → 1

summarizes representative (illustrative) device-class Q_oss values used here to visualize how WBG technology shifts the ZVS-feasible corridor. These values are not tied to a specific part number; they only represent typical separation between Si, SiC and GaN device classes.

Screening results and ZVS corridor shift.

Table 12. Screening ZVS margin m_ZVS for Case Study A (U_DC = 400 V, DT = 100 ns) under a fundamental approximation. Values ≥ 1 indicate robust ZVS-like boundary alignment.

Q	δ	|φ| (Deg)	mZVS (GaN-like, 20 nC)	mZVS (SiC-like, 80 nC)	mZVS (Si-like, 200 nC)
0.70	1.05	3.9	2.14	0.54	0.21
0.70	1.10	7.6	4.14	1.03	0.41
0.70	1.20	14.4	7.59	1.90	0.76
1.40	1.05	7.8	8.46	2.11	0.85
1.40	1.10	15.0	15.72	3.93	1.57
2.83	1.03	9.5	20.74	5.18	2.07

reports screening values of m_ZVS for representative operating points (δ,Q) on the super-resonant side. A robust ZVS-like boundary alignment is expected when m_ZVS ≥ 1, while m_ZVS < 1 indicates insufficient commutating charge within DT under the adopted screening assumptions. The table illustrates a key WBG implication: reducing Q_oss reduces Q_eq and therefore increases m_ZVS at fixed (δ,Q,DT), expanding the ZVS-feasible corridor toward lighter loading (smaller Q) and toward δ → 1.

Figure 8 visualizes the ZVS-feasible corridor by plotting the boundary m_ZVS(δ,Q) = 1 for the three device classes of Table 11. For a fixed tank and DT, the boundary shifts toward resonance as Q_oss decreases, which is particularly relevant for GaN and SiC devices.

Time-domain verification (Simulink/LTspice). To confirm the screening trends, a switching time-domain model is set up in Simulink (Simscape Electrical) or LTspice with: (i) an ideal half-bridge with explicit dead time DT; (ii) nonlinear device output charge implemented either via a C_oss(v) element or via a Q_oss(v) table; (iii) a bidirectional reverse-current path consistent with σP (body diode for Si/SiC MOSFETs, third-quadrant conduction model for GaN); and (iv) the series RLC tank and load corresponding to the selected Q values. Boundary alignment is checked by sampling the switch-node voltage at each device turn-on instant (u_sw(t_on)), while stress/circulation factors k_I(AC) and k_RMS(AC) are computed from peak and RMS device currents over a steady-state period. A practical validation point is that operating points with m_ZVS ≥ 1 from Table 10 should correlate with u_sw(t_on) approaching zero before turn-on, whereas m_ZVS < 1 should correlate with partial commutation and increased turn-on loss.

Simulation setup for Case A. A complementary half-bridge switching model was implemented with the same tank parameters as above (L = 20 μH, C = 100 nF), with the series resistance R chosen to realize the targeted Q at each operating point (R = Z₀/Q, Z₀ ≈ 14.14 Ω). The DC bus was set to U_DC = 400 V and complementary gating was applied with dead time DT = 100 ns. Device output charge was represented by an equivalent nonlinear node capacitance parameterized by the device-class Q_oss values of Table 10 (implemented either as a voltage-dependent C_oss in SPICE or as an energy/charge-consistent capacitor element in Simulink). All other non-idealities (gate-drive delays, package inductances, diode reverse recovery) were kept idealized in this verification step so that the waveforms isolate the regime- and Q_oss-driven ZVS margin trend predicted by m_ZVS.

ZVS-like alignment was evaluated by checking whether the switch-node voltage completed the transition to the opposite rail within DT before device turn-on (|v_SW| approaching 0 V or U_DC, respectively), while the tank current sign at the boundary matched the expected commutating direction. Each simulation was run for sufficient cycles to reach periodic steady state; reported waveforms correspond to the last cycle.

To validate the regime-level screening based on the ZVS boundary-alignment margin m_ZVS, time-domain switching simulations were carried out for two representative operating points located on different sides of the screening boundary m_ZVS = 1. Figure 9 compares a margin-poor point (m_ZVS < 1) close to resonance and under lighter loading with a robust super-resonant point (m_ZVS ≥ 1) at higher detuning and moderate load.

In the margin-poor case (e.g., δ ≈ 1.05, Q ≈ 0.7), the available commutating charge during dead time is insufficient to fully discharge the switch-node capacitances before turn-on. As a result, the switch-node voltage remains significantly above zero at the switching instant, indicating partial or lost ZVS-like boundary alignment. In contrast, in the robust case (e.g., δ ≈ 1.20, Q ≈ 1.4), the larger phase shift ∣φ∣ provides higher commutating current during dead time, enabling the switch-node voltage to approach zero before turn-on. This confirms the predictive value of the symmetry-based margin m_ZVS.

The waveforms also illustrate the associated cost of symmetry: strengthening ZVS feasibility by moving further into the super-resonant regime increases current excursion and RMS circulation, consistent with the trends captured by the stress and circulation metrics introduced in Section 4.1.

To make the waveform-level meaning of the screening margin more explicit, Figure 9 compares two representative operating points from Case Study A: a margin-poor point with m_ZVS < 1 and a margin-rich point with m_ZVS ≥ 1. The purpose of this comparison is not to replace detailed switched-model validation, but to illustrate how the proposed margin interpretation is reflected in the time-domain relation between switch-node voltage and resonant-tank current at the commutation instant.

Cost of symmetry note (WBG context). While lower Q_oss expands the ZVS corridor, WBG devices also enable higher dv/dt and di/dt, which can increase EMI and ringing sensitivity. In this framework, these effects can be interpreted as additional implementation-level “payment” (layout/clamp requirements) on top of the current-domain inflation captured by k_I(AC) and k_RMS(AC).

5.6. Case Study B: Wide-Bandgap Closed-Input Excitation Below Resonance (Dual ZCS Corridor and Voltage-Stress Payment)

This case study provides the dual counterpart of Case A under closed-input (current-fed) excitation. While Case A (open-input, super-resonant) protects the voltage boundary and shifts the dominant payment to the current domain, Case B (closed-input, sub-resonant) protects the current boundary and shifts the dominant payment to the voltage domain. In signature notation, sB = (closed-input, sub-resonant, ZCS-like, bidirectional path, single-mode) is obtained from sA by applying the composed symmetry operator D_ext introduced in Section 2.5.

Excitation model and screening normalization. For regime screening, the closed-input source is represented as an approximately constrained square-wave current excitation ±I_DC feeding the same series RLC tank as in Case A. The RMS value of the fundamental current component is approximated as I_1,rms ≈ (2√2/π)·I_DC (full-wave square excitation). Then V_1,rms = I_1,rms·|Z| and V_pk ≈ √2·V_1,rms provide a first-order estimate of voltage excursion. The peak-voltage stress factor is k_V,pk ≈ V_pk/U_DC,nom, where U_DC,nom is a nominal DC voltage used for normalization.

Voltage-stress payment and device voltage class.

Table 13. Screening voltage excursion and ZCS-like feasibility indicators for Case Study B (I_DC = 20 A, U_DC,nom = 400 V). The column m_ZCS is a screening estimate using CT = 1 μs, L_eq = 5 μH, and I_start = I_DC.

Q	δ	|φ| (Deg)	Vpk (V)	kVpk (Norm. 400 V)	Vpk/650 V	Vpk/1200 V	mZCS Est. (CT = 1 µs, Leq = 5 µH, Istart = 20 A)
0.50	0.60	28.1	816	2.04	1.26	0.68	3.84
0.50	0.75	16.3	750	1.88	1.15	0.63	2.10
1.00	0.60	46.8	527	1.32	0.81	0.44	3.84
1.00	0.75	30.3	417	1.04	0.64	0.35	2.10
2.83	0.85	42.7	173	0.43	0.27	0.14	1.18
2.83	0.95	16.2	133	0.33	0.20	0.11	0.37

reports screening estimates of V_pk and k_V,pk for representative sub-resonant operating points. The same table also evaluates V_pk relative to two common WBG voltage classes (650 V and 1200 V), illustrating how closed-input/light-load corridors can violate the 650 V class even when the normalized stress k_V,pk is moderate with respect to a 400 V nominal bus. This simple screening step therefore acts as an early feasibility filter when selecting GaN versus SiC platforms for closed-input resonant operation.

ZCS-like boundary-alignment margin (screening). In the metric layer of Section 4.1, ZCS-like feasibility is expressed by a volt–second margin m_ZCS comparing the available current-change capability during a commutation interval CT to the current that must be reduced to reach a zero-current boundary. For screening, one may use m_ZCS ≈ (|u_comm|·CT)/(L_eq·|i_start|). The commutating voltage u_comm is topology dependent; for a regime-level estimate it scales with the tank voltage at the commutation instant and therefore increases with |sinφ(δ,Q)|, while it collapses as φ → 0 near resonance. Accordingly, sub-resonant operation (δ < 1, φ < 0) tends to widen ZCS-like corridors, but at the price of increased voltage excursion (higher k_V).

It is important to emphasize that the proposed margins m_ZVS and m_ZCS are not formal proofs of commutation success. They are structured regime indicators whose usefulness lies in comparative pre-selection. Final acceptance of a candidate operating regime still requires waveform-level confirmation under non-ideal timing, parasitic, and device-dependent conditions.

Figure 10 visualizes this dual corridor by plotting (i) k_V,pk(δ,Q) contours and (ii) the boundary m_ZCS(δ,Q) = 1 for the chosen (CT,L_eq,I_DC) commutation setting. The combined plot makes the dual trade-off explicit: moving deeper sub-resonant strengthens ZCS-like feasibility (higher m_ZCS) while increasing voltage stress (higher k_V,pk), especially at light load (smaller Q).

Time-domain verification (Simulink/LTspice). A switching model of a representative current-fed resonant inverter (e.g., current-fed full-bridge or push–pull with input inductor and clamp network) is then used to verify: (i) that device current at turn-off reaches (or crosses) zero within the commutation interval (ZCS-like boundary alignment), and (ii) that peak switch-node/clamp voltages remain within the selected device voltage class. Measured waveforms should include switch current around turn-off, switch-node voltage, and clamp/diode currents (if present).

Simulation setup for Case B. A current-fed switching model was configured by enforcing the input constraint with a large input inductor (L_DC ≫ L, e.g., on the order of mH) or an ideal controlled current source, delivering I_DC = 20 A (square-wave excitation ±I_DC) into the same series RLC tank. A practical overvoltage path was represented with a clamp to the DC link (e.g., diode/active clamp to U_DC,nom = 400 V), allowing the model to capture the expected voltage-excursion ‘payment’ when operating below resonance. Operating points were selected with δ < 1 and Q values matching the screening table, using R = Z₀/Q for consistency with the normalized map.

ZCS-like alignment was evaluated by inspecting device current around turn-off and confirming that i_SW(t_off) reached (or crossed) zero within the commutation interval CT (used in the screening estimate of m_ZCS), while simultaneously checking peak switch-node and clamp voltages (V_pk) against the chosen device voltage class. Waveforms recorded for Figure 11 include i_SW, v_SW, and clamp current (if present) in the last steady-state cycle.

To corroborate the sub-resonant screening results of Figure 8, time-domain switching simulations were performed for representative operating points within and near the predicted ZCS-like corridor. Figure 11 illustrates a case in which the screening margin m_ZCS ≥ 1 is satisfied, highlighting the characteristic current-symmetric (ZCS-like) turn-off behavior and the associated voltage-domain “payment”.

At the selected sub-resonant operating point (δ < 1), the resonant current naturally approaches zero within the commutation interval CT, and the device current crosses (or nearly crosses) zero before turn-off. This confirms current-boundary alignment consistent with a robust ZCS-like margin. However, as predicted by the symmetry-based screening maps, the strengthened ZCS feasibility is accompanied by increased switch-node voltage excursion. The voltage rise during commutation activates the clamp/diode path, redistributing energy and limiting peak stress but introducing additional voltage-domain burden.

The combined current, voltage, and clamp-current waveforms therefore make explicit the dual trade-off identified in the regime map: moving deeper into the sub-resonant corridor increases m_ZCS while shifting the dominant stress channel toward voltage excursion and clamp involvement. This time-domain verification confirms that the symmetry-based metrics m_ZCS and k_V,pk provide consistent early-stage predictors of commutation feasibility and stress redistribution.

To illustrate the waveform-level meaning of the ZCS-oriented screening interpretation, Figure 11 presents the representative time-domain verification for Case Study B at the selected sub-resonant operating point. The figure is intended to show how current-boundary alignment, switch-node voltage rise, and clamp-path activation appear together when the regime is driven toward stronger ZCS-like turn-off. In this way, the waveform set provides a direct visual counterpart to the symmetry-based indicators m_ZCS and k_V,pk.

The numerical results presented in this paper are intended as regime-verification studies rather than as benchmark optimization campaigns. To improve reproducibility, the selected case studies specify the tank structure, detuning regime, normalized screening quantities, and the qualitative operating targets used for waveform verification. The figures were generated directly from the corresponding numerical simulations to ensure consistency between the analytical screening interpretation and the observed time-domain behavior.

5.7. Sensitivity of the Regime-Screening Interpretation to Non-Idealities

The regime-screening interpretation developed in this paper is intentionally formulated at an idealized or near-idealized descriptive level, so that the symmetry and extended-duality structure can be expressed in a compact and comparable way across operating conditions. However, practical resonant inverter operation is inevitably influenced by non-idealities that may alter commutation margins, redistribute stress, or weaken an otherwise clear regime pairing.

The most relevant non-idealities include:

(1)

dead-time variation and timing mismatch;

(2)

voltage-dependent output capacitance and nonlinear device charge effects;

(3)

parasitic inductance in the commutation path;

(4)

reverse-path conduction non-idealities associated with finite recovery or conduction asymmetry.

These effects do not necessarily invalidate the proposed regime-level interpretation, but they can reduce the reliability of margin-based screening if they are ignored in detailed design validation.

From a regime-screening perspective, the main impact of such non-idealities is to shift the practical threshold at which a nominally favorable commutation tendency becomes robust in waveform-level behavior. For example, a regime classified as margin-rich under idealized assumptions may become only boundary-feasible when dead time increases or when parasitic inductance delays the intended current transition. Similarly, nonlinear output capacitance may alter the effective charge-displacement requirement for voltage-side commutation, thereby modifying the practical interpretation of m_ZVS even when the idealized signature remains unchanged.

For this reason, the screening indicators proposed in this work should be interpreted as first-stage comparative metrics rather than as final acceptance criteria. Their value lies in identifying promising regimes, stress redistribution trends, and symmetry-consistent pairings before detailed non-ideal simulation or experimental refinement is performed. In practical design workflows, the regime-screening stage should therefore be followed by parasitic-aware simulation, timing-sensitivity analysis, and hardware-oriented verification.

To make this limitation more explicit,

Table 14. Qualitative sensitivity of the regime-screening interpretation to representative non-idealities.

Non-Ideality	Expected Influence on Screening Margins	Expected Influence on Stress Interpretation	Practical Implication
Increased dead time	Reduces effective commutation margin near switching boundary	May increase current distortion or shift soft-switching window	Regimes near (mZVS ≈ 1) or (mZCS ≈ 1) become more sensitive and require refined timing validation
Voltage-dependent output capacitance (Coss, (V))	Alters practical voltage-side commutation requirement	Can shift the apparent stress payment toward the switching node	Idealized ZVS-oriented screening should be confirmed using device-aware charge/discharge modeling
Added parasitic inductance in the commutation path	Delays current transition and may degrade commutation alignment	May increase overshoot and redistribute stress across the switching interval	Margin-rich regimes remain informative, but boundary cases may lose robustness under layout parasitics
Reverse-path conduction non-ideality	Weakens ideal current redirection or recovery behavior	Can increase circulation loss and asymmetry between dual-paired regimes	Path-feasibility interpretation should be treated cautiously unless reverse conduction is explicitly modeled
Parameter drift/component tolerance	Perturbs resonance alignment and threshold behavior	Can alter circulation severity and effective regime placement	Regime pairing remains useful descriptively, but practical margins should be interpreted over tolerance bands rather than nominal points

summarizes the expected qualitative influence of several common non-idealities on commutation margins and stress-oriented interpretation.

Table 14 reinforces an important point of the present work: the proposed formalism is most useful as a structured regime-screening framework, not as a substitute for non-ideal design validation. Non-idealities primarily affect the practical robustness of the margin interpretation rather than the descriptive logic of the regime pairing itself. This distinction is important for maintaining both the usefulness and the proper limits of the extended-duality approach.

5.8. Discussion: Dual Pairing and WBG Design Implications

Taken together, the two case studies instantiate the extended-duality pairing on the signature map. Case A (open-input, δ > 1) emphasizes a ZVS-like corridor whose feasibility scales with commutating current and the effective node charge Q_eq; WBG devices reduce Q_eq via lower Q_oss and therefore enlarge the ZVS-feasible region. The dual Case B (closed-input, δ < 1) emphasizes a ZCS-like corridor whose feasibility grows with available commutating volt–seconds, while the dominant cost of symmetry appears as voltage excursion and clamp/device voltage stress. Thus, the framework predicts and organizes a device-aware trade: WBG benefits (low Q_oss, high-speed commutation) directly strengthen soft-switching margins, but also demand explicit attention to voltage class selection, dv/dt-related parasitics, and EMI-oriented implementation constraints.

5.9. Consistency Between Screening Metrics and Time-Domain Verification

To clarify the practical meaning of the proposed screening indicators,

Table 15. Consistency between screening margins and time-domain verification in the representative case studies.

Case/Operating Condition	Dominant Screening Metric	Predicted Tendency from Screening	Time-Domain Waveform Observation	Interpretation
Open-input regime, margin-rich operating point	(mZVS > 1)	Robust ZVS tendency with favorable commutation timing	Turn-on transition occurs with low switch-node voltage and clear pre-commutation discharge	Screening prediction is consistent with waveform-level soft-switching behavior
Open-input regime, near-boundary operating point	(mZVS ≈ 1)	Borderline ZVS feasibility; sensitive to operating perturbation	Waveforms show near-threshold commutation with reduced margin and increased sensitivity to timing	Screening captures boundary-sensitive regime behavior rather than idealized robust ZVS
Closed-input regime, margin-rich operating point	(mZCS > 1) or corresponding current-boundary margin	Strong tendency toward current-relieved switching interval	Current waveform approaches switching boundary in a controlled manner, with reduced hard-switching severity	Screening prediction is consistent with current-side commutation relief
Closed-input regime, circulation-dominated point	Low commutation margin with elevated (kI)/(kRMS)	Increased reactive circulation and stress payment despite feasible operation	Time-domain waveforms remain operational but show stronger circulating current and less favorable switching conditions	Metrics correctly indicate that feasibility is preserved at the cost of higher stress/circulation
Dual-paired operating regimes (open- vs. closed-input)	Redistribution of (kI), (kV), and margin indicators	Dual pairing should preserve regime correspondence while shifting stress payment	Waveforms confirm qualitative regime correspondence, but with shifted stress concentration and commutation advantage	Extended duality is supported at regime level, not as strict waveform identity

summarizes the consistency between the regime-level commutation margins and the time-domain behavior observed in the representative numerical case studies. The purpose of this comparison is not to claim that the metrics replace detailed waveform validation, but to show that they provide a useful early-stage indication of soft-switching tendency, circulation severity, and regime robustness. In this sense, the metrics are intended as structured screening tools for comparative regime assessment rather than as stand-alone guarantees of final converter performance.

The comparison in Table 15 supports the intended role of the proposed screening metrics: they do not replace detailed switched-model simulation, but they do provide a meaningful regime-level indication of commutation favorability, circulation severity, and stress redistribution. This is particularly useful in early-stage exploration, where many candidate regimes must be screened before detailed non-ideal validation is performed.

5.10. Scope and Limitations

The proposed symmetry/extended-duality map is intended as a regime-level framework for early-stage reasoning, screening, and explanation. Accordingly, the quantitative corridor indicators (e.g., m_ZVS, m_ZCS, k_V,pk) are deliberately low-order and rely on simplifying assumptions (fundamental approximation for tank waveforms, idealized switch timing, and reduced device parasitic representation). They should be interpreted as comparative design metrics rather than as final-rating calculations.

In practical hardware, additional effects can shift the boundaries and alter the ‘cost of symmetry’, including package and layout inductances, voltage-dependent C_oss and reverse recovery behavior, magnetic nonlinearities, dead-time jitter, and EMI-constrained gate-drive shaping. For publication-quality design closure, the workflow therefore requires a second stage consisting of detailed device models, thermal limits, and experimentally validated parasitic extraction, while the symmetry coordinates (source constraint, detuning sign, commutation boundary, and mode count) remain useful as a consistent organizing backbone across that refinement.

6. Conclusions

This paper proposed a symmetry-oriented interpretation of resonant DC-AC inverter operation in which duality is treated as a global organizing principle rather than a topology-specific observation. While open-input versus closed-input excitation remains a fundamental source-domain duality axis, practical inverter behavior is jointly governed by frequency-domain detuning relative to resonance, commutation boundary alignment, and modal structure.

Within the proposed framework, soft switching is interpreted as an emergent consequence of symmetry selection, and stress redistribution is recognized as the cost of symmetry. The framework complements conventional topology-based classifications by providing a compact conceptual map linking operating regimes, phase behavior, soft-switching tendencies, and stress/loss trade-offs. Future extensions include explicit treatment of multi-resonant and multi-mode families, where modal symmetry and higher-dimensional detuning become central organizing variables.

The contribution of the present manuscript should therefore be understood as a structured regime-level formalism for interpreting symmetry and extended duality in resonant DC-AC inverter operation, rather than as a complete topology-isomorphism theory or a substitute for detailed non-ideal validation. Its main value lies in providing a consistent framework for comparing open-input and closed-input operating regimes, organizing dual-pair reasoning, and supporting early-stage screening of commutation tendency, circulation severity, and stress redistribution. In this sense, the proposed approach is intended to improve conceptual clarity and design-stage regime selection, while leaving final waveform-level verification, parasitic-aware simulation, and experimental assessment as necessary steps for engineering deployment.

Future work should extend this regime-level framework toward parasitic-aware validation, experimentally supported dual-pair assessment, and broader applicability across additional resonant inverter classes and modulation conditions.