1. Introduction
Recovering information from fewer samples is possible if data are sparse or compressible. In this case, an ADC can operate in a sampling rate closer to the actual information rate rather than the Nyquist one [
1]. The ADCs in this case are often called Analog to Information Converters (AIC) [
2]. Compressive Sampling or Sensing (CS) methods employ iterative optimization techniques like Regressive Analysis or Orthogonal Matching Pursuit [
3] to recover information from fewer measurements. The hardware implementation of a CS algorithm requires a large number of resources due to its increased complexity. CS techniques are applied in image processing applications such as radar, medical imaging (such as Magnetic Resonance Imaging (MRI), ultrasounds, X-ray imaging), surveillance systems, etc. For example, in [
4], the acquisition time needed for MRI scans is significantly reduced. In [
5], radar data are compressed and decompressed using CS techniques with Normalized Mean Square Error (NMSE) ranging between 1.5 and 2.5 under certain measurement conditions.
In OFDM environments channel estimation is achieved using CS techniques since it can be assumed that the OFDM channel is sparse. In this way, the number of pilots can be substantially reduced as described in [
6], where 511 subcarriers and 20 pilots are used, and only a few of the 40 channels taps are assumed non-zero. The Bit Error Rate (BER) is approximately 0.003 if Signal/Noise Ratio (SNR) is 30dB and 5 of the 40 channel taps are non-zero. The efficient implementation of sparse FFT and Inverse FFT (IFFT) in OFDM environments is an important target since these modules are computationally intensive and power greedy. In [
7] sub-sampling of the input signal is performed with O(k∙logk) complexity. For example, using a 280 × 280 pixel image in [
7] with the number of non-zero pixels being 3509, the NMSE is 0.0085 when 35308 samples are used.
In the work presented in [
8,
9], the sparse IFFT input samples of an OFDM transmitter are ordered appropriately to allow the information recovery on the receiver side from fewer FFT input samples. In this way, the power consumption of the receiver ADC is reduced down to the half while the memory requirements, power dissipation and the speed of the IFFT and the FFT modules can also be reduced. More specifically, a wired OFDM architecture is studied in [
8], where 1024-point FFT/IFFT is employed. The simulation results show that full information recovery can be achieved if 50% of the time the ADC operates in 7/8 of its normal rate and the sparseness
s in input data is less than 2% i.e., less than 2% of the input bits are non-trivial. If a lower ADC sampling rate is employed, an error floor appears that may be acceptable in some applications. Full information recovery can also be achieved if lower ADC sampling rate is applied when sparseness level is higher. The only noise source taken into consideration in [
8] is Additive White Gaussian Noise (AWGN). The effect of the ADC Quantization Errors (QE) and the Round-off Errors (RE) caused by the representation of the operands with limited number of bits is not studied in [
8]. The proposed undersampling technique is extended in [
9], to cover wireless OFDM transceivers with Space-Time Block Code (STBC) encoding. A general Signal to Interference, Distortion Noise Ratio (SIDNR) expression is derived taking into consideration the ADC quantization noise as modeled in [
10] as well as wireless channel features like Inter-Symbol-Interference (ISI).
In the present work, we focus on the most critical part of the OFDM transceiver system that is the FFT on the receiver side. A precise error model has been developed by describing how the employed undersampling technique can affect the overall error in the received data. This Undersampling Error (UE) is combined with the RE/QE errors. The target is to optimally select the appropriate word length for the representation of the FFT input values and coefficients in order to avoid excessive additional error overhead beyond the error caused by the UE. For example, the end user may ask for an RE error that will not exceed 10% of the UE. Selecting the desired modulation scheme and FFT size the developed error model will estimate the minimum word length to achieve the specified relation between RE and UE for a particular sparseness level of the input data. The real numbers (or the real/imaginary parts of a complex number) can be represented in IEEE-754 standard 32-bit floating-point format [
11]. In this format, a real number is described by one bit for the sign, a number of bits for the significand and a signed exponent. Although the IEEE-754 floating point format can cover a wide range of real numbers with a very high precision, the number of resources that it needs is excessively high. For this reason, fixed point format is employed in this work. In fixed point format (b,f),
b bits are used for the description of a number and
f of these
b bits are used for the fraction:
. Several operations such as multiplications and divisions by 2 can be implemented with simpler circuits in fixed point format but the results of these operations have to be monitored for scaling and overflow errors.
A memory-based pipeline configurable FFT has been developed in synthesizable Very high speed IC Hardware Description Language (VHDL) to accurately assess the proposed error model. Two FFT sizes have been tested (256 and 1024 points) with different number of word lengths (ranging from 5 to 10 bits). The alternative modulations tested were 16-QAM and 4-QAM with various levels of data sparseness ranging between 0.5% and 10%. The OFDM configuration in terms of FFT size, modulation and word length cannot change dynamically in real time. They are statically defined in order to measure the error for various sparseness levels. The average RMSE error between the predicted word length and the experimental results is less than 1, for the various QE error targets that have been set. The predicted word length can also be used as the ADC resolution.
This paper is organized as follows: In
Section 2, the undersampling method presented in [
8] and [
9] is briefly described as well as some indicative QE and RE error estimation methods presented in the literature. The combined UE, RE error model proposed in this paper is presented in
Section 3. The synthesizable memory-based pipeline FFT architecture used to assess the error model is presented in
Section 4. Finally, in
Section 5 the simulation results are presented along with a discussion on how the error modeling followed can be useful for other non-OFDM telecommunication systems.
3. Proposed UE, RE Error Model
We focus on a 16-point FFT on the OFDM receiver side that is used as a case study and appears in
Figure 2. It is attempted to estimate first, how the error, caused by the undersampling process described in
Section 2.1, propagates and calculate the expected error on the FFT outputs. The FFT output error affects the Symbol Error Rate (SER) and the Bit Error Rate (BER) of the OFDM system. However, in this work the FFT output error caused by the undersampling process (
PUE) is compared to the QE error (
PQE) in order to find an acceptable word length for the FFT.
In the four propagation cases examined, a single error is caused by a QAM symbol
that does not have the expected trivial value
(they differ by
ε) in order to generate FFT outputs equal to zero (that can be pruned) or the expected trivial intermediate butterfly outputs. Instead, let us assume that:
. The propagation of the error in the first two levels of butterflies (a pair of 2-point and one 4-point FFT) is denoted with the dashed lines in
Figure 2. In the first case, the error
ε appears at the even input
i of the 2-point FFT at the top. Τhe error at the outputs of the 4-point FFT is
. In the second case that appears from top to the bottom of
Figure 2, the non-trivial
yi symbol appears at the even input
i+2 of the four-point FFT. The error in this case is
. In the third case the error appears at the odd input
i+1:
. In the last case at the bottom of
Figure 2, the error at the odd input
i+3 is
. In the previous expressions of
elogN-1 the twiddle factors
are used without the index
N for simplicity. The differences in the four
elogN-1 expressions are owed to the different twiddle factors that multiply the error ε as it propagates through different paths.
Figure 3 shows how the
elogN-I error of stage
logN-p propagates to the next butterfly stage
logN-(p-1). The arrows in
Figure 3 are buses and
Figure 3a shows the propagation of the error from the top butterfly input, while
Figure 3b shows the propagation of the error from the bottom input. In the first case
while in the latter case
. The symbol “.*” implies multiplication of the corresponding elements of the vectors and
w is the vector of all the twiddles of a specific butterfly stage. If multiple errors exist in the FFT inputs, their effect is added at the FFT output. For example, if the errors ε
3 and ε
7 occur in the bit reversed 16-point DIT FFT inputs
y3 and
y7 (corresponding to
Y12 and
Y14 outputs), the individual output errors (
and
, respectively) would be:
The combined output error if both ε
3 and ε
7 occur is
. Of course, the same error propagation model holds for the IFFT on the transmitter side. Moreover, the estimation of the error ε is easier on the transmitter side since, the IFFT inputs are QAM symbols with integer values. The 16-QAM constellation shown in
Figure 4 is used as a case study, and we assume that X
c = ”1111”, i.e., the trivial input is ‘1’. We can see that there are: a) N
(2) = 4 neighboring QAM symbols (
X(2)) that differ by 2 in the real or imaginary direction from
Xc (the continuous arrows), b) N
(2,2) = 4 symbols (
X(2,2)) that differ by 2 in each direction from
Xc (dashed arrows with big dashes), c) N
(2,4) = 4 symbols (
X(2,4)) that differ by 2 in one direction and by 4 in the other from
Xc (dotted arrows), d) N
(4) = 2 symbols (
X(4)) that differ by 4 in either the imaginary or real direction from
Xc (dashed arrows with small dashes), and e) a single (N
(4,4) = 1) symbol (
X(4,4)) that differs from
Xc by 4 in each direction.
X(2) symbols correspond to 4 input bits with one ‘0’ while
X(2,2) and
X(4) symbols are derived from 4 input bits with 2 zeros. Finally, the
X(2,4) symbols correspond to 4 input bits with 3 zeros and the QAM symbol (-3,-3) is derived by “0000”. The corresponding probability of each symbol is p
c, p
(2), p
(2,2), p
(4), p
(2,4), p
(4,4). The order of these probabilities is p
c > p
(2) > p
(2,2) = p
(4) > p
(2,4) > p
(4,4) due to data sparseness.
Since X
c = (1,1), the minimum error in 16-QAM modulation is
. The rest of the errors are:
,
,
,
. The expected value of ε will be:
For 16-QAM, E[ε]=3.37 if only the symbols that are different than
Xc are taken into consideration and they have equal probability. In general, E[ε] depends on the sparseness level
s<1 of the input and the QAM modulation. The sparseness level
s means that a fraction
s of the input data bits is non-trivial. If all the non-trivial symbols have equal probability to appear, then p
(k)=s/(N-1). In this case, Equation (15) can be rewritten as:
The effect of the employed modulation scheme to the BER/SER of a telecommunications’ system is explained in detail in Appendix C of [
12]. The estimation of E[ε] for different modulation schemes can be assisted by the analysis performed in [
12]. There are several alternative options to place the constellation symbols that correspond to a specific number of bits. The lower error is achieved when adjacent constellation symbols differ only in one digit (Gray mapping). In one-dimensional or ring constellations, the Gray mapping can be easily found while square QAM constellations can be Gray encoded hierarchically by examining smaller blocks. There are, however, constellations where there is no perfect Gray mapping. Each constellation
X is surrounded by a decision region with minimum distance called Voronoi. When a received symbol
Y resides within the Voronoi region of
X it is decoded as
X on the receiver. The higher the minimum distance of a modulation scheme, the lower the BER/SER that can be achieved. For example, if hard decoding is employed, i.e., if a received QAM symbol is first demodulated to its corresponding bits and then these bits are corrected by the supported FEC method, SER can be expressed as [
12]:
where
Y is the received symbol,
X is the constellations of a specific modulations scheme,
p(Y|X) is the probability to get
Y at the receiver given that the symbol transmitted is
X and
Rx is the decision region (Voronoi) of
X. In the 16QAM modulation examined earlier, if one of the constellation bits is inverted, the effect on the BER of this error is 1/4 of the effect on the SER. It can be stated that SER represents the worst case effect of the error to the OFDM system. This is also confirmed by various simulations performed in the Appendix C of [
12] where several modulations schemes are tested.
In order to estimate the variance of the UE in each one of the FFT outputs we have to define all the possible paths that the error can follow from the FFT input. The paths can be determined in a systematic way starting from a specific output. Let us assume that when a butterfly crossing is reached following the upper branch is denoted by ‘0’ while following the lower branch is denoted by ‘1’. All the paths can be determined in this way by the combination of log
2N bits. For example, in
Figure 2, the dashed line that reaches output
Y12 shows a potential path that the error has followed from input
y6. The error propagation path in this case can be denoted by “0110” and the initial error ε can be multiplied in each branch by 1, a twiddle factor
w or
–w.
Table 1, lists for example, all the potential errors that can occur at each output of an 8-point FFT as well as the expected output error values (in all cases they are 0 except from
Y0 due to orthogonality) and its complex variance. Since the complex variance is the sum of the variances of the real and imaginary parts and the expected values of the error at each output is 0 (except
Y0), the complex variance is actually the sum of the squares of the sine and cosine of the same number (the power of the corresponding twiddle factor) which results in 1. Thus, the complex variance is equal to 1×ε
2 in all cases but
Y0. This fact holds for any N-point FFT. If
R is the number of samples substituted by the undersampling procedure (e.g., R=1/16 means that N/16 of the FFT inputs have been substituted by others), the total power of the UE error (P
UE) can be estimated as a function of
N, R, s,
E[ε]:
The selection of an appropriate FFT word length and ADC resolution should target to the restriction of QE and RE errors within a fraction or a multiple
pf (e.g., P
QE, P
RE ≤ 10% of the P
UE) of the UE error estimated in the way described above. More specifically, using
from Equation (11) and defining
,
PRE can be expressed as:
If
, Equation (20) can be expressed as a 2
nd degree equation as follows:
The determinant
Det in Equation (20) above is
. Solving (21) and keeping only the positive square root of the determinant (the negative square root is not applicable) we get:
The first two terms of the Taylor series approximation of the square root were preserved in Equation (20). Since the variables
α and
u in the definition of
c change in the various operations of the FFT, it is attempted to estimate only
c and not
α and
u separately. Replacing
g in Equation (20), the required word length
b can be estimated as follows:
If
, and Equation (18) is written in a general form in order to adjust the weight of the parameters
s, N, pf, R, the word length
b can be expressed as:
In order to select appropriate values for the unknown
ci values, the Octave fsolve function for non-linear equations is used with a small number of instances of Equation (23) i.e., with a small number of
b, pf, s, R, N, combinations. The experimental results show that Equation (23) can be used then to accurately estimate the required word length
b for other
pf values given a specific OFDM configuration (
s, R, N, ε). The physical meaning of the estimated
ci parameters will be explained in
Section 5.
4. The Employed FFT Architecture
A DFT requires O(N
2) operations that are reduced to O(N∙logN) if the original FFT architecture is employed [
18]. The number of points used by the FFT can be expressed as a product of numbers that are powers of 2. Thus, a 1024-point FFT can be implemented by 10 Radix-2 stages, or 5 Radix-4 stages. If the number of points of the FFT is not a power of 2, then Radix-3 or Radix-5 butterflies can also be employed. For example, a 100-point FFT can be implemented with one stage of Radix-4 and two stages of Radix-5 butterflies [
26]. The round-off errors depend on the architecture of the FFT (serial/parallel, Decimation in Time or Frequency, etc.) and the number of stages. An FFT can be implemented either in software if slower operation is acceptable or in hardware for faster response. Modern telecommunication systems require high speed hardware FFTs. Hardware FFTs can either consist of a large number of hardware resources working in parallel or reusable components for more compact, low power implementations with a slightly higher latency overhead.
In this paper, a robust memory-based pipeline FFT has been developed to test the effect of round-off errors in conjunction with the undersampling scheme described in
Section 2. It consists of log
2N stages (one of them appears in
Figure 5). The inputs of stage
l are stored in the double buffer
l (its size is 2×N×b bits). The word length of a butterfly output can be larger by one bit compared to its inputs for optimal resource utilization. However, we use a constant size of b-bits for the inputs/outputs and twiddles of all stages in order to get similar results with the case where a single reusable pipeline stage was used iteratively. One buffer
l of the pair is used to store the real and the other for the imaginary part of the FFT inputs/outputs. Buffer
l is accessed for write through the buses w1(
l) and w2(
l), and for read through the buses r1(
l) and r2(
l). Each one of these buses consists of a log
2N bits, address bus (ra(
l) or wa(
l)) and a pair of b-bits data buses (Re{rd(
l)} and Im{rd(
l)}, or Re{rd(
l)} and Im{rd(
l)}). Each data bus carries real numbers in fixed point format with a size of
b bits. The inputs of each Radix-2 butterfly are the rd1(
l) and rd2(
l) while its outputs are wd1(
l) and wd2(
l). The real and imaginary parts of the twiddle factors
w are retrieved from the twiddle Read Only Memory (ROM). The size of the twiddle ROM of stage
l is 2×N/2
l+1.
The operations performed at a Butterfly block are:
The address buses ra(
l) and wa(
l) are driven by the Address Generator module that is based on an up counter with log
2(N)-1 resolution. In each stage
l the pair of addresses used for the retrieval of the butterfly inputs/outputs (
Addr0 for I
0 and O
0,
Addr1 for I
1, O
1) and
AddrT for the corresponding twiddle factor are the following:
In Equations (28)–(30), % is the modulo operator, is the floor function, and Cnt is the current value of the counter in the Address Generator. The stages of the developed FFT operate in a ping-pong manner. For example, in the first N/2 clock cycles the FFT inputs are loaded on the input Buffer at stage l=logN-1. In the next N/2 cycles, the butterfly of stage l is driving its outputs to Buffer l-1. Then in the next N/2 cycles, the stage l-1 is reading inputs from Buffer l-1 and driving the outputs to the Buffer l -2. At the same time the input Buffer l can be loaded with the next set of FFT inputs. The FFT latency is cycles and the throughput is an FFT output completed every N cycles.
The FFT architecture described in this section can be used to evaluate the complexity of the system in relation with the word length. Focus is given on the main FFT blocks: adders/subtractors and multipliers in the butterflies, counter in the address generator, input/output buffers and twiddle factor ROM. The silicon area or gate count of a ripple carry adder/subtractor is proportional to the word length of the operands. However, if the word length of an b-bit adder with carry look-ahead is increased by 1 (b+1) the required gate count will be increased by more than 1/b since the carry look-ahead logic needed to generate the additional carry is more complicated than the logic needed to generate the carry of the least significant bits. The gate count required by a multiplier depends on its architecture. For example, an b-bit Scaling Accumulator Multiplier (SAM) consists of b AND gates, a b-bit adder, a b-bit shift register and the b-bit output register. Thus, the SAM multiplier gate count is proportional to the word length b. The same holds for Serial by Parallel Booth Multipliers i.e., the gate count is proportional to the word length. In these kind of multiplier architectures one of the operands has to be inserted serially bit by bit. Ripple Carry Multipliers (RCM) require all the operand bits in parallel but the area needed is proportional to the square of the word length. Other multiplier architectures like row adder tree and carry-save multipliers require approximately the same gate count as RCM but can achieve faster operation. The storage area needed by the twiddle ROMs and the input/output buffers is proportional to the word length but the area needed by the corresponding address decoders is proportional to the logarithm of the word length. In general, it can be stated that the complexity of the FFT/IFFT modules in an OFDM transceiver is approximately proportional to the employed word length.
The proposed FFT architecture has been described in synthesizable VHDL and has been tested in Modelsim. The description of this module in VHDL is sufficient for the assessment of the effect of the finite word length in the overall error in the OFDM receiver. Implementation on a Field Programmable Gate Array (FPGA) would also be useful to estimate the speed and the power consumption of this module and this will be part of our future work.
5. Simulation Results and Discussion
In this section, the word length estimation based on Equation (23) is evaluated. The combinations examined are the following: 16QAM or Quadrature Phase Shift Keying (QPSK) modulation, N=256 or 1024, R=1/4 or 1/16, s=0.5%, 1%, 2% or 10%. When 16QAM is used E[ε]=3.37 as estimated in
Section 3. In a similar way E[ε]=2.276 is estimated for QPSK. The number of bits estimated as the required word length
b were between 5 and 10. The total number of configurations simulated are 116. A number of these configurations (four sets including between 5 and 16 non-linear equations) have been used in Octave in order to solve the non-linear Equation (23) for the unknown values of the
ci parameters. Then, the rest of the L=116 configurations were tested and the RMSE between the real value of
b and the estimated
best for a specific
pf value is extracted as shown in Equation (31). In this way, the minimum number of non-linear equations that have to be solved in order to determine the
ci parameters precisely is found.
The sets of non-linear equations described in
Table 2,
Table 3,
Table 4 and
Table 5 have been used to estimate the values of the
ci parameters. The average RMSE achieved in the word length estimation of all the 116 configurations is also listed in the 1
st row of these tables along with the estimated
ci values for each case. As can be seen from
Table 3, determining the
ci values from 12 instances of Equation (23) leads to the lowest RMSE (0.736 for 16QAM and 1.09 for QPSK modulation). A relatively low RMSE is also estimated if 16 equations are used as shown in
Table 2. The
ci parameters estimated in
Table 2 and
Table 3 are rounded to c
1 = −5, c
2 = −2, c
3 = 2, c
4 = 1, c
5 = 2 in order to explain the physical meaning of these values and how they lead to an accurate word length estimation.
Using the specific
ci values, Equation (23) can be written as:
From
we get that
or
which is impossible unless
u and
a are assumed complex numbers. When the set of equations listed in
Table 4 is used
and
which is more consistent with the model presented in [
22] and Equation (11). However, the initial definition of
c1 will be ignored in an attempt to define the overall error model that matches the experimental results more accurately. In this perspective, the rest of the terms in the right side of Equation (23) are interpreted as follows:
takes its minimum value (−0.185) for the experiments conducted in this paper when R=1/16 and E[ε]=2.276 with QPSK modulation and its maximum value (0.2) with R=1/4 and E[ε]=3.37 when 16QAM modulation is employed. The term
is close to a constant since
pf is proportional to the sparse level
s: if only non-sparse FFT inputs were present, there would be errors in all the FFT outputs and
. The higher value measured for
pns is 0.3. If the input is sparse, the ratio
pf of the quantization error to the undersampling error is proportional to the sparseness level
s: . When the input is too sparse, the UE and QE errors are both low. When the input is less sparse (
s value is higher), UE raises but the raise of QE is even higher. This is owed to the fact that although UE gets worse, there may be still FFT outputs unaffected by the undersampling process if some samples are replaced by the others with identical value. However, if
s is higher, more operations with numbers that are not zero will be performed and the QE will increase respectively since all the results of these non-trivial operations will have QE error. In this sense,
counterbalances
and the maximum value for the 3rd term of Equation (23) will be
. If
pns is lower, a higher positive offset in Equation (23) occurs.
The last term of Equation (23) can have two values in the results presented in this paper: either
or
. This is the larger positive offset that counterbalances the negative value of the constant value
c1. The specific
ci parameters have been approximated for these two FFT sizes. Should different FFT sizes be covered, the set of nonlinear equations that have to be used for the approximation of
ci parameters must also include configurations with these FFT sizes. If we try to use the approximated
ci parameters of
Table 3 for the case of a 64-point FFT size,
would be 0. The term
results in small signed offsets between −0.185 and 0.2 as explained above and thus, the word length would be actually determined by the factor
. In order to get a realistic estimation of at least 5 bits as a word length,
pns should be 10
-3, or, in other words, UE error should be 1000 times larger than QE error. Such a relation between UE and QE errors is not always guaranteed.
The estimated and expected word lengths for all the 16QAM and QPSK OFDM configurations tested when the
ci parameters listed in
Table 3 are used, are compared in
Figure 6 and
Figure 7, respectively. In these figures, the required minimum ADC resolution is also included. This ADC resolution
bADC has been estimated in Equation (33) that has been derived from Equation (8), the definition
and the specification that
PQE should be equal to
PRE.
Vref was selected equal to 1V but approximately the same results would have been achieved if a different voltage reference had been selected, such as 3V. The ADC resolution
bADC should match the FFT word length
b thus,
bADC should be selected equal to
b since
in all cases as shown in
Figure 6 and
Figure 7.
The procedure followed in this paper to define a model that optimizes the word length subject to error restrictions and a predetermined relation between undersampling error and quantization/rounding error can be followed in other non-OFDM telecommunication systems. For example, in optical networks, a model can be created that selects the appropriate modulation (number of bits/symbol:
Rs) in order to achieve a desired capacity, given a specific power budget
Po. Based on the analysis presented in [
12], the capacity
Co can be expressed as:
The noise term
NoRs can be expressed as a weighted combination of the various noise sources in an optical channel [
12]: the beat noise
, the shot noise
and the thermal/electronic noise
. Concerning the constants (we assume that their values are known) used in these noise variance expressions,
Sb is the photodetector responsivity,
No is the noise spectral density,
PLO the optical power,
Be the power equivalent bandwidth of the entire receiver and
e the elementary charge. The most important optical noise is Amplified Spontaneous Emission (ASE) which actually describes the attenuation of the optical signal by a factor
. The distortion posed by the required
NA repeater/amplifiers placed at distance
can be described by the noise spectral density
or
if Erbium-doped fiber amplifiers (EDFAs) or Ideal Distributed Raman Amplification (IDRA) is used, respectively. The parameters used in these noise spectral densities are also assumed to have known values:
h is the Plank constant,
vs is the optical frequency,
KT is the photon occupancy factor and
the spontaneous emission factor. The model can be trained by a number of non-linear equations that combine the channel error sources with various capacity and power requirements for specific predefined modulations schemes. The target of this training would be to estimate the weights of the channel error sources. After updating the error model with these weights, it can be used to select an appropriate modulation scheme for different capacity and power specifications or channel conditions.