Ferroelectric Memory Based on Topological Domain Structures: A Phase Field Simulation

Abstract

The low storage density of ferroelectric thin film memory currently limits the further application of ferroelectric memory. Topologies based on controllable ferroelectric domain structures offer opportunities to develop microelectronic devices such as high-density memories. This study uses ferroelectric topology domains in a ferroelectric field-effect transistor (FeFET) structure for memory. The electrical behavior of FeFET and its flip properties under strain and electric fields are investigated using a phase-field model combined with the device equations of field-effect transistors. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. External tensile stress increases the memory window and off-state current, while compressive stress decreases it. This study shows that a ferroelectric topology can be used as memory and could significantly increase the storage density of ferroelectric memory.

1. Introduction

Ferroelectric memory, which features non-volatile memory, is used in defense and civilian products, such as security systems, aerospace and automotive electronics, and smart cards [1,2]. However, the low storage density of ferroelectric memory based on ferroelectric thin film limits its further application. Numerous methods have been proposed to improve the storage density of ferroelectric memory. The most frequently mentioned is the increasing of the storage density in ferroelectric memory by reducing the area of a single memory cell. Chiu demonstrated the switchable diode characteristics in highly strained BiFeO₃(BFO) thin films, significantly reducing the memory dimension with the same storage capacity [3]. The size reduction would result in a noticeable degradation of ferroelectric performance, which would impact data storage and reading [4,5,6,7,8,9]. It has been reported that novel polarized topological domain structures are formed when ferroelectric materials are scaled down to the nanoscale [10,11,12,13,14]. Li demonstrated that central topological domains could spontaneously form in BFO nano-islands [15]. Under the application of electric fields, a reversible switch can be found between two morphologies of central convergence and central divergence. Tang observed the atomic morphology of the flux-closure quadrant, as well as a periodic array of flux closures in ferroelectric PbTiO₃ films, which were mediated by tensile strain on a GdScO₃ substrate using aberration-corrected scanning transmission electron microscopy [16]. It has been noted that the different states of ferroelectric topology can be used to record the “1” and “0” of binary information [17]. Using the ferroelectric topological domain structure as the basic information storage unit efficiently achieves high-density storage. Biswas achieved the reversible switching of partial topological domains by applying an electric field to two pairs of electrodes on Pb(Mg_1/3Nb_2/3)O₃-PbTiO₃ substrates [17]. Ping realized that skyrmions could be created locally via an electric field in the magnetoelectric helimagnet Cu₂OSeO₃ [18]. Significant domain wall conduction was found in diamond-shaped BFO nano-islands embedded in a tetragonal phase matrix, leading to current readout in different types of center states and promising the development of non-volatile memories with current readout [19]. Other topological states have been found in isolated nanostructures. For instance, Schilling [20] et al., McGilly [21] et al., and McQuaid [22] et al., reported closed quadrant states in the single crystal nanoplates of BaTiO₃. The application of polarized topological domains in ferroelectrics has potential application prospects in ferroelectric memory. These studies primarily investigated the flip-flop of ferroelectric topology under external field conditions. They did not investigate storage properties such as memory windows. These studies also identified critical issues, which must be addressed before ferroelectric topology domain structures can be realized for storage. To the best of our knowledge, there are still relatively few systematic studies on the electric properties of the output characteristics of topology-based domain memory. Additionally, the experimental tuning of topological domain structures is already complicated; it is even more challenging to implement when used as a basic storage unit for memory.

In this study, to model the generation of ferroelectric topological domain structures and realize storage, a phase-field approach was applied to obtain the topological domain structure of ferroelectrics. Topological domain structure-based ferroelectric memory is controlled using electric and force fields based on field-effect transistor device equations. The simulation results establish a theoretical foundation for topological domain storage.

2. The Simulation Methodology

PbTiO₃ (PTO) has a high Curie temperature (490 °C) and a substantial spontaneous polarization, allowing it to be used in various ferroelectric devices. The research objective in this work was PTO. The topological domain structure of ferroelectrics was obtained by using the phase field method. F is the total free energy of the ferroelectrics, which is described as [23]:

$$\begin{array}{ll}F={\alpha }_i{P}_i^2& +{\alpha }_{ij}{P}_i^2{P}_j^2+{\alpha }_{ijk}{P}_i^2{P}_j^2{P}_k^2+\frac{1}{2}{c}_{ijkl}{\epsilon }_{ij}{\epsilon }_{kl}-q_{ijkl}{\epsilon }_{ij}{P}_k{P}_l\\ & +\frac{1}{2}{g}_{ijkl}{P}_{i,j}{P}_{k_{l}l}-\frac{1}{2}{\epsilon }_0{\epsilon }_r{E}_i{E}_i-E_i{P}_{i,}\end{array}$$

(1)

where $P_i,{\epsilon }_{ij}$, and E_i are the polarization, strain, and electric field components, respectively. The electric field E_i = (E₁, E₂, E₃) in Equation (1) is extended to include the uncurled electric field E^Unc generated by the inhomogeneous polarization, the depolarization field, and a prescribed curled electric field. S is the coiled field’s vorticity vector and u is the displacement vector [24,25]. In Equation (1), α_i, α_ij, and α_ijk are the higher-order dielectric stiffness coefficients, c_ijkl is the elastic constant, q_ijkl is the electrostrictive coefficient, g_ijkl is the gradient energy coefficient, ε₀ is the gradient energy coefficient, and ε_r is the relative dielectric constant. The topological domain of the ferroelectrics was then obtained by solving the time-dependent Ginzburg–Landau (TDGL) equation [26,27]:

$$\frac{\partial P_i\left(r,t\right)}{\partial t}=-L\frac{\delta F}{\delta P_i\left(r,t\right)}\left(i=1,2,3\right)$$

(2)

where r and t are the spatial vector and time, respectively. L is the kinetic coefficient; i = 1, 2, 3 corresponds to the x, y, and z directions, respectively. To facilitate the calculation, the parameters were dimensionless in the simulation. The dimensionless process of the cyclic vorticity S and the toroidal moment G is where the characteristic moment is defined as G₀ = u₀P₀ =1 nm × 0.757 C/m² = 0.47 e/Å, in which u₀ and P₀ are the duple characteristic length and characteristic polarization, respectively [28]. The selection and details of other dimensionless parameters are described in our previous work [26]. Transistors based on ferroelectric nanodots with topology domain structures were studied in the simulation. The cross-section of the transistors is shown in Figure 1a. The different chirality of the ferroelectric layer vortex indicates the stored “0” and “1”. The top metal electrode is metal Pt with an extremely high work function (5.6 eV) and a thickness of 80 nm, and the ferroelectric layer is a PTO under the metal electrode. The semiconductor layer is Si with a thickness of 600 nm, the most widely used semiconductor material, and the insulating layer is a SiO₂ layer with a thickness of 140 nm, which can easily be grown on a silicon substrate. In addition to the two-dimensional case, which reflects most of the critical properties of the ferroelectric topological domain structure, topological domains were found to exist in the plane in our previous study; therefore, we used a two-dimensional phase field model in this study [29]. The ferroelectric topology domain structure in PTO is modeled on a discretely sized grid and the grid spacing is set as Δx* = Δz* = 0.3, corresponding to the actual size of 7.2 nm; the time step is set as Δt* = 10,000.

The device equations of field-effect transistors were then developed to study the electric properties of the ferroelectric memory. Gate voltage is expressed as [28]:

$$V_g=V_f+V_i+{\psi }_s$$

(3)

where V_f = d_fE_f denotes the corresponding voltage drop on the ferroelectric layer and V_i = d_iE_i denotes the corresponding voltage drop on the insulator layer; d_f and d_i are the corresponding thicknesses of the ferroelectric layer and the insulator layer, respectively. E_f and E_i represent the electric field applied on the ferroelectric and insulator layers and ψ_s denotes the corresponding surface potential of the silicon substrate. The electric displacement is written as [30]:

$$D={\epsilon }_0{\epsilon }_f{E}_f+P(E_f)={\epsilon }_0{\epsilon }_i{E}_i={\epsilon }_0{\epsilon }_{si}{E}_{si}=-Q_s$$

(4)

where ${\epsilon }_f$, ${\epsilon }_i$, and ${\epsilon }_{si}$ are the relative dielectric constant of the ferroelectric layer, the relative dielectric constant of the insulator layer, and the relative dielectric constant of the silicon substrate, respectively. P(E_f) denotes the polarization of the switching dipoles and Q_s denotes the space charge density on a silicon substrate, which can be written as [29]:

$$Q_s({\psi }_s)=-sign({\psi }_s)\frac{\sqrt{2}{\epsilon }_0{\epsilon }_i}{\beta L_D}{(\frac{n_i^2}{N_D{}^2}(e^{-\beta {\psi }_s}+\beta {\psi }_s-1)+(e^{\beta {\psi }_s}-\beta {\psi }_s-1))}^{1/2}$$

(5)

According to Gauss’s theorem, the capacitance of a ferroelectric capacitor can be described as [31]:

$$C_{Si}({\psi }_s)=\frac{A_i{\epsilon }_i{\epsilon }_0}{\sqrt{2}{L}_D}\cdot \frac{(\frac{{n_i}^2}{{N_D}^2}(-e^{-\beta {\psi }_s}+1)+(e^{\beta {\psi }_s}-1))}{{(\frac{{n_i}^2}{{N_D}^2}(e^{-\beta {\psi }_s}+\beta {\psi }_s-1)+(e^{\beta {\psi }_s}-\beta {\psi }_s-1))}^{1/2}}$$

(6)

where $L_D=\sqrt{{\epsilon }_0{\epsilon }_S{\varphi }_t/q{N}_D}$ represents the bulk Debye length. The capacitance of ferroelectrics and insulation is written as C_f = A_fε₀ε_f/d_f, C_i = A_iε₀ε_i/d_i and the total capacitance as C_total = (C_f⁻¹+ C_i⁻¹+ C_Si⁻¹)⁻¹. The leakage current (I_ds) is [32]:

$$I_{ds}=q\mu \frac{W}{L}{\displaystyle \underset{0}{\overset{V_{ds}}{\int }}}{\displaystyle \underset{{\psi }_b}{\overset{{\psi }_s}{\int }}\frac{(n_i{}^2/N_D)e^{\beta }(\psi -V)}{\xi (\psi ,V)}}d\psi dV$$

(7)

where q is the electron charge and W and L are the effective conductive channel width and effective conductive channel length on the surface of the substrate, respectively. ψ is the difference between the Fermi level and the intrinsic Fermi level of the substrate.${\psi }_b=-\varphi \ln (\frac{N_D}{n_i})$, $\varphi =kT/q$ is the thermodynamic potential of the system, whereby $k$ denotes the Boltzmann constant and thermodynamic temperature. The C-V_ds relation and the output characteristic (I_ds-V_ds) curve can be obtained.

3. Results and Discussion

Figure 1a depicts the structure of the ferroelectric topology domain transistor. At room temperature, Figure 1b shows annular moment G* and its response to cyclic vorticity S*(d_f = 20 nm). The superscript * indicates the corresponding dimensionless posterior parameter. The counterclockwise start domain structure, denoted as A, is shown in Figure 1c in illustration A3, and the toroidal moment is −2.6775. After that, cyclic vorticity S* is increased from −0.6 to 0.6 with a magnitude of −0.6. The inset A1 and A2 depict the evolution of the topological domain structure with time at point A, with time increments of 500 steps and 5000 steps, respectively. When the vorticity increases to 0.3, the polarized vortex switches and the topological domain structure becomes anti-counterclockwise. When S* grows to 0.6 with a toroidal moment of 2.3166, the topological domain structure at this point is shown in Figure 1c in illustration F. When cyclic vorticity S* decreases from 0.6 to −0.6, cyclic vorticity switches from the F-I-B point and the toroidal moment change decreases from 2.7431 to −2.3056. The response to cyclic vorticity shows an asymmetric rectangular hysteresis line, which indicates that polarized vortices in ferroelectric topological domains have potential applications in future high-density memories, such as the P-E loop of the ferroelectric thin film. Cyclic vorticity from the F-I-B point and the vorticity moment change drops from 2.7431 to −2.3056 when cyclic vorticity S* declines from 0.6 to −0.6. An asymmetric rectangular hysteresis line appears in response to the cyclic vorticity, indicating that polarized vortices in ferroelectric topological domains could be used in future high-density memory.

The C-V_ds and I_ds-V_ds characteristic curves were then investigated under the influence of cyclic vorticity. When the memory window is 1.3407 V, the open-state current is 2.487 mA and the closed-state current is 1.7388 mA (Figure 1e) (d_f = 20 nm). The C-V_ds curve is shown in Figure 1d (d_f = 20 nm), which is larger than the memory window of 1.08V in the literature [33]. The results indicate that the ferroelectric topology domain structure is feasible for storage and that transistors are based on a topological domain structure with a large memory window. Information storage cells based on this polar architecture are theoretically capable of achieving ultra-high density memory with an area density of more than 12 Tbit/in².

A change in the thickness of the ferroelectric layer leads to a change in the voltage shared on the ferroelectric layer, which in turn affects the magnitude of the ferroelectric layer capacitance and thus the size of the storage window of the device [34]. Therefore, it is important to study the effect of a ferroelectric layer’s thickness on its memory window. Figure 1f shows the effect of different ferroelectric layer thicknesses on the storage window of FeFETs. It is evident that as the thickness increases, the storage window tends to increase and then decrease, reaching a maximum thickness of 80 nm. This is because the voltage on the ferroelectric layer increases as the thickness increases, and the increase in voltage makes the ferroelectric film polarization of the ferroelectric layer more adequate, thus making the storage window larger. However, as the thickness continues to increase, the voltage of the ferroelectric layer is no longer sufficient to simultaneously produce better polarization characteristics of the ferroelectric topology domains; this also leads to poor saturation performance, so the thickness of the ferroelectric layer continues to increase instead of reducing the storage window. However, the increase in the thickness of the ferroelectric layer will also lead to an increase in the size of the device, which is not in line with the development requirements of today’s information technology. For this consideration, in the following simulations, we choose a PTO thickness of 20 nm. The development of ferroelectric topological domains is mainly due to the rivalry of distinct energies. To realize topological domain storage, the influence of the applied electric field on topological domains was thoroughly examined. Figure 2a shows the C-V_ds curves for various external electric fields ($E_1^{*}$), with the C-V_ds curves becoming narrower as $E_1^{*}$ increases. The memory window shrinks from 2.49 to 0.6 V when $E_1^{*}$ grows from −0.1 to 0.1 (Figure 2b). This can be explained as an increase in polarization due to the total system energy of the system’s increase caused by the external electric field. Figure 2c shows I_ds-V_ds of ferroelectric memory as a function of $E_1^{*}$, with magnitudes of −0.10, −0.05, 0.05, and 0.10. When $E_1^{*}$ increases from −0.10 to 0.10, the open-leakage current decreases from 2.516 mA to 1.951 mA and the closed-leakage current increases from 1.532 mA to 1.887 mA (Figure 2d). The rise in $E_1^{*}$ makes the G*-S* curve thinner (Figure 2e) and the positive residual toroidal moment of the PTO decreases (Figure 2f). In addition, the positive charge generated in semiconductor Si decreases accordingly, which leads to resistance of the channel increases and open-state current increases [35]. Furthermore, as $E_1^{*}$ climbs, the negative residual toroidal moment of the ferroelectric film diminishes, resulting in a decrease in the negative charge created in the semiconductor channel. More charge accumulates in the semiconductor channel with a large $E_1^{*}$ and causes the transistor’s closed-leakage current to decrease.

The force has a significant impact on the ferroelectric topology domain structure, which in turn has an impact on transistor performance. Here, we investigated the effect of stress on the behavior of topological domain structure transistors. Figure 3a represents the C-V_ds curves of the ferroelectric memory when σ₁₁ = −2 × 10⁸ Pa and σ₁₁ = 2 × 10⁸ Pa. When σ₁₁ increases from −2 × 10⁸ Pa to 2 × 10⁸ Pa, the memory window decreases from 2.498 to 0.367 V (Figure 3b). When compressive stress becomes tensile stress, the elastic energy in the system progressively climbs and the elastic energy in the system grows as the polarization value increases. The voltage drop in the ferroelectric layer is raised. With a constant gate voltage, the pressure drop at both ends of the PTO rises, but the pressure drop at both ends of the insulating layer SiO₂ remains unchanged; therefore, the surface potential of the semiconductor Si layer decreases, resulting in a smaller memory window. At σ₁₁ = −2 × 10⁸ Pa, the closed-leakage current is 1.701 mA and the open-state current is 2.911 mA. The open-state current is 1.887 mA at σ₁₁ = 2 × 10⁸ Pa, while the closed-leakage current is 2.304 mA (Figure 3c). The open-state current drops as it intensifies, but the closed-state current flows (Figure 3d). The positive residual toroidal moment decreases as the stress increases from −2 × 10⁸ Pa to 2 × 10⁸ Pa (Figure 3e,f), causing the charge induced in the Si channel to drop and the Si surface to progressively transition from an electron-accumulated to an electron-depleted state. As a result, channel resistance rises while the open leakage current falls. Furthermore, when the topological domain transistor channel is closed, the Si substrate surface is inverted. The value of the negative residual toroidal moment decreases during this process, resulting in a smaller degree of Si substrate inversion and, eventually, an increase in the closed-state leakage current.

4. Conclusions

In conclusion, we used circulating eddy currents to successfully flip ferroelectric eddy currents. The response of toroidal moment G* to cyclic vorticity S* was obtained at room temperature. It was confirmed that the topological domain structure can be used for storage and this substantially increases the storage density of ferroelectric memory. Furthermore, topology is modulated by electric field and stress, and the C-V_ds relationship curve and output characteristic I_ds-V_ds relationship curve are obtained under various conditions using the semiconductor device equation. When the dimensionless electric field changes from −0.10 to 0.10, the memory window drops from 2.49 V to 0.6 V and the on-state current drops from 2.511 mA to 1.951 mA; the off-state current grows from 1.532 mA to 1.877 mA. When σ₁₁ increases from −2 × 10⁸ Pa to 2 × 10⁸ Pa, the memory window decreases from 2.498 to 0.367 V. At σ₁₁ = −2 × 10⁸ Pa, the closed-leakage current is 1.701 mA and the open-state current is 2.911 mA. The open-state current is 1.887 mA at σ₁₁ = 2 × 10⁸ Pa, while the closed-leakage current is 2.304 mA. This points us in the right direction for the development of new non-volatile random access memory with an ultra-high density.