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Computers 2017, 6(2), 19;

Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications

Department of Industrial Engineering, University of Salerno, 84084 Fisciano (SA), Italy
Author to whom correspondence should be addressed.
Academic Editor: Laith Al-Jobouri
Received: 14 April 2017 / Revised: 13 May 2017 / Accepted: 15 May 2017 / Published: 17 May 2017
Full-Text   |   PDF [1127 KB, uploaded 17 May 2017]   |  


Exploiting the Bachet weight decomposition theorem, a new two-dimensional filter is designed. The filter can be adapted to different multimedia applications, but in this work it is specifically targeted to image processing applications. The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board. View Full-Text
Keywords: visual search; multiplier; 2D filtering modules; Gaussian filtering visual search; multiplier; 2D filtering modules; Gaussian filtering

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Licciardo, G.D.; Cappetta, C.; Di Benedetto, L. Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications. Computers 2017, 6, 19.

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