Next Article in Journal
Kinetostatic Modeling and Performance Analysis of a Symmetric Redundant-Actuated 4-PSS Compliant Parallel Micro-Motion Mechanism
Previous Article in Journal
Thermoelectric Materials and Devices
Previous Article in Special Issue
Impact of Fabrication Defects on FPGA Logic Using Memristor-Based Memory Cells
 
 
Article
Peer-Review Record

Topology Reconfiguration for NoCs: A Fast Reconfiguration Algorithm Based on Monotonic Path Shifting

Micromachines 2026, 17(4), 438; https://doi.org/10.3390/mi17040438
by Mingzhi Zhang, Zhijia Wang, Zhenxing Wang, Dali Xu and Na Niu *
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Micromachines 2026, 17(4), 438; https://doi.org/10.3390/mi17040438
Submission received: 8 February 2026 / Revised: 25 March 2026 / Accepted: 29 March 2026 / Published: 31 March 2026
(This article belongs to the Special Issue Advances in Field-Programmable Gate Arrays (FPGAs))

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper proposes a Monotonic Path Shift (MPS) topological reconstruction algorithm for REmesh NoCs with core-level redundancy, based on local rapid recovery. The paper addresses a significant problem in Network-on-Chip (NoC), which restores regular logical topology following permanent core failures. The proposed algorithm exhibits near-linear time complexity, with a reconstruction success rate comparable to the ACTR algorithm, both maintaining high repair rates under high fault density. The paper is well-structured and easy to follow.

 

I mainly have the following concerns,

  • The novelty is incremental. It builds heavily on the REmesh framework from Wu et al. [14] and related algorithms (BTTR [16], BSTR [15], ACTR [18]). The paper claims "main contributions" like modeling monotonic paths and analyzing complexity, but these feel like refinements of existing ideas (e.g., path-based remapping in [13]). A clearer differentiation from prior work (e.g., how MPS avoids the exponential complexity pitfalls of backtracking in BTTR) would strengthen this.
  • How is the deadlock avoided after reconstruction? The paper does not explicitly discuss whether the resulting physical routing (after MUX reconfiguration) introduces new potential deadlocks.
  • While the paper mentions reducing area and search overhead, it lacks a quantitative comparison of the hardware area and power consumption with the original REmesh.
Comments on the Quality of English Language

The English needs significant editing. There are grammatical errors such as "nuclear failure", "auxthors",  "Logicla Faulty Core", etc. And the section Related Works repeats a lot of Introduction content such as the paragraph “Within the REmesh framework, ......”.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper proposes a topological reconstruction algorithm for REmesh NoC architectures with core-level redundancy. It tackles the challenge of efficiently recovering from core failures while maintaining topological regularity. MPS constructs monotonic paths from faulty cores to redundant cores in spare columns, enabling localized recovery instead of global reconstruction. The algorithm uses region retention and local fallback mechanisms to resolve conflicts when multiple cores fail simultaneously. Experimental results show that MPS achieves near-linear time complexity and reconstruction success rates comparable to existing algorithms. 

The monotonic path-shifting concept is innovative. By limiting topology changes to the vicinity of faulty cores rather than requiring global reconstruction, MPS reduces search complexity and migration overhead. In addition, the region retention and local fallback mechanisms are theoretically grounded and practically demonstrated through multiple examples.

However, the algorithm is specifically designed for REmesh architectures with certain routing constraints. The paper does not discuss how MPS might adapt to non-square meshes or other topologies, limiting its applicability. The authors could improve the paper by discussing how the proposed technique can be extended to other topologies and at least evaluating non-square mesh topologies (e.g., 4x8, 6x10, etc.) in the evaluation section.

Additionally, although the algorithm's performance is reported in nanoseconds, the paper does not provide the target technology node, clock frequency, or hardware platform for these measurements. Please specify the hardware details in the revision.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

NoC failures, especially permanent ones, could significantly degrade performance and make deployment complex. The authors propose a Monotonic Path Shift algorithm for REmesh architectures that utilizes localized path replacement, region retention, and local fallback mechanisms to bypass defective cores. Their method provides a high successful reconfiguration rate, improves the average core reuse rate, and reduces the average recovery time.

This paper shows some novelty on an interesting topic. However, this seems incremental over the authors' prior work [18], ACTR. The difference between this work and [13] is not clearly presented. The related work section is a bit narrowly scoped, with no overall view of the broader field. The authors should further clarify on this topic.

The paper claimed an average O(k), which is not justified. The distribution assumption is not elaborated, and the O(k) seems to be the enumeration of the frameworks. As in the last paragraph of Section 4, the worst case is O(|F|^2 n^2), with an empirical claim of |F| is far smaller than N^2, which does not seem to be supported as well. Given this, the claim in the abstract of near-linear time complexity seems a bit overclaimed.

The comparison between algorithms seems to be all from the same research group. The authors may need to compare with other existing work in addition to those to make sure the baseline is adequate. It is understood that adoption of other work to this architecture may require some work. However, without those metrics, whether the authors' algorithmic contribution is significant or not cannot be evaluated.

Minor Issue: Equation 4: x 100% on a time (ART) does not make any sense. Similarly, on ACRR x 100% on a ratio number. Fig 10 (a) and (b) show 110% on the y-axis, which should be hidden. Also, the base y-axis is 85%, 40%, 20%, and 15%, which inflates the visualization and is considered a bad practice.

Typos: auxthors, Logicla, Inrechable.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report

Comments and Suggestions for Authors

The authors have partially addressed my previous concerns. The improved writing and corrections to the complexity claims and ART equation are appreciated. However, several issues remain unresolved.

The revision still lacks external baselines. I understand that REmesh is an architecture designed by the authors' group with no prior work from others. However, this does not justify the complete absence of external comparisons. Adapting general NoC remapping or fault-tolerance methods as additional baselines would significantly strengthen the evaluation's credibility and allow the community to assess the contribution's significance.

Regarding related work, the additions primarily cover FPGA-based reconfiguration. A broader discussion for the wider NoC fault-tolerance landscape is still needed.

Several editorial issues also require attention: (1) The sentence "Theoretical analysis shows that MPS provides an upper bound on the algorithm's runtime..." is duplicated. (2) Multiple broken cross-references display "Error! Reference source not found." (3) Table 1 uses an excessively large font. (4) "Figure 8Figure 8" is duplicated at line 520. (5) Previously flagged typos ("Logicla," "Inrechable") remain uncorrected. (6) The y-axes of Figures 10 and 11 still use non-zero baselines, which inflate visual differences between algorithms.

Finally, I want to flag that there is substantial content reused from the authors' prior work, "An Optimized Core Distribution Adaptive Topology Reconfiguration Algorithm for NoC-Based Embedded Systems," without acknowledgment. While this largely concerns background material rather than the core contribution and is therefore relatively benign, the authors should properly cite or acknowledge the reused passages to avoid concerns of self-plagiarism.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 3

Reviewer 3 Report

Comments and Suggestions for Authors

I appreciate the authors' effort in revising the paper, especially the addition of external benchmarks. FPGA-related work is also added - while still narrow, I would consider it acceptable.

I only have minor concerns: I am not sure if it is a system issue or what, but most of my previously raised editorial issues remain unaddressed. Fig. 10.'s y-axis starts with 10%, which is funny - it does not contribute much in inflating the number but still confuses readers. The copy-paste is not explicitly noted. But I will leave those issues to the editor and recommend acceptance without another round.

Back to TopTop