A Parameter-Agnostic Adaptive Compensation in Memristor-Based Neuromorphic Systems for Parasitic Resistance

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The work entitled: "A Parameter-Agnostic Adaptive Compensation in Memristor-based Neuromorphic Systems for Parasitic Resistance"  could make a valuable contribution to simplifying the simulation and modelling of memristor crossbar arrays. The overall approach of the study is interesting, and the methodology used is appropriate, as there is a clear improvement in the accuracy of the simulation results when compared with a real-world case.

However, there are certain aspects which, in our view, should be improved or clarified as appropriate:

(1) The model assumes a single (mean) value for all memristors in the array. This is unrealistic, even though the simulation results are reasonable. The point is that, if this were the case, a similar result could be obtained by using resistors with that same value R_mean instead of memristors. The authors should address this apparent contradiction, as otherwise the value and benefit of using memristors would not be apparent.

(2) Along the same lines, one of the key advantages of memristors is their plasticity, which allows the weights of synaptic connections within the neural network to be modified. This aspect is not included in the proposed model and, in a sense, once again obscures the intrinsic benefits of using memristors. How might this plasticity be incorporated into the proposed model?

(3)  Nor does the assumption that all entries in the array are identical reflect reality. The authors should explain how the model manages to simulate a realistic scenario based on this unrealistic assumption.

(4) Even in this case, the higher the column number, the lower the voltage at the top terminal of the memristors (Eq. 15), and the lower the row number, the higher the voltage at the bottom terminal. Therefore, the voltage drop across the memristors located in the top-right corner of the circuit diagram in Figure 5(a) has the minimum value, whereas this voltage drop is maximum in those located in the bottom-left corner. It is therefore necessary to explain why setting identical values for the memristor resistances, the currents in all SL lines and the potential drops across all memristors enables the accuracy in the overall behaviour on which the proposed model is based.

Finally, throughout the paper there is a sense of uncertainty regarding the state of the memristor. For example, in Figure 2, error coefficient values are obtained across a voltage range of 0 to 0.3 V for different scenarios. It is unclear whether these results were obtained for the LRS or HRS states. According to Figure 2(a), no change in state would occur within this voltage range. At higher voltages, transitions from one state to the other would occur. Furthermore, memristors may exist in intermediate states between these two extreme states. For an adequate modelling of a realistic scenario, all these possibilities should be considered, and this is not addressed in the manuscript. It is essential to consider all these possibilities in order to describe a real-world scenario, and the authors should conduct a study in this regard.

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper proposes a Parameter-Agnostic Adaptive Compensation (PAAC) method to correct output current distortion caused by input and line parasitic resistances in memristor crossbar arrays, using a simplified linear model that requires only a single pre-calibration step. The method is validated through both board-level hardware experiments, which reduced current distortion from 71% to 2%, and large-scale HSPICE simulations, which restored neural network classification accuracy from 89% to 95%. These comments can help authors improve their paper:

1. In your line resistance model, you assume all input voltages are equal to simplify the analysis. In a real VMM operation, voltages are different. How does this assumption affect the accuracy of the linear model for the line resistance compensation? Does the PAAC method implicitly account for this during the pre-experiment step?
2. In real hardware, there might be small offset currents due to leakage or amplifier bias. How robust is the method to such non-idealities?
3. The parasitic effects on the most critical, computation-heavy layers (convolutions) are not validated. 
4. Improve your literature review by refereing in new paper in line with your research, such as DOI: 10.1002/aisy.202500806.
5. You emphasize that the method requires no prior knowledge of parasitic values, but the pre-experiment still relies on knowing the average conductance of the column. In a real system, this average might drift over time or vary with temperature. 
6. Is there any interaction or coupling in the input and line resistance combined effect that a single linear factor might not capture?

 

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

In this revised version of the paper, the authors have clarified the issues raised with precision. They have also clearly defined the scope of the model they propose. This has helped to eliminate some potential problems of interpretation regarding the content of the paper. In its current form, I believe the paper is ready for publication, and I encourage the authors to continue along this interesting line of research to further improve this promising model.