Investigation on the Isolation Approaches for High-Voltage GaN-on-Sapphire Monolithic Power Integrated Circuits

Abstract

Gallium Nitride (GaN) fabricated on an insulated sapphire substrate achieves a higher rated voltage of monolithic power integrated circuits compared to that fabricated on a conductive silicon substrate. In this paper, the effectiveness of isolation approaches considering substrate bias and crosstalk effects between adjacent devices in GaN-on-Sapphire monolithic power integrated circuits is investigated. It is demonstrated that the substrate bias and crosstalk effects between high-side and low-side power devices are effectively suppressed regardless of substrate termination with the implantation isolation approach. Thanks to the ultrathin buffer upon an insulated sapphire substrate, the ion implantation can also isolate the adjacent high-voltage (power) and low-voltage (logic) devices. However, a weak crosstalk effect that is caused by capacitive coupling is still observed between high-voltage devices and low-voltage devices with the implantation approach; the degradation rate is calculated to be up to 3%. Experimental results prove that a shallow trench isolation structure in the implantation region can be adopted to mitigate the crosstalk effects, to further improve the stability of integrated logic circuits and drivers under dynamic high-voltage switching conditions.

1. Introduction

Gallium Nitride (GaN)-based power devices provide high efficiency and high power density for power converters and supplies [1,2,3]. The reliability and stability of GaN devices are of paramount importance in applications, and there remain some key challenges. For example, the high-frequency operation makes the devices sensitive to the parasitic inductances from interconnections between power switches and other functional blocks, and then the parasitic voltage/current spikes or overshoots could occur and lead to failure of power electronic systems. To reduce the parasitic inductances, GaN power integrated circuits (ICs) based on monolithic integration have been intensively investigated for more than a decade [4,5,6,7,8,9,10,11,12].

As reported by prior investigations, substrate bias and crosstalk effects are the main obstacles to the development of monolithic half-bridge integration on a conductive Si substrate. The GaN-on-SOI technology and the GaN-on-EBUS technology have resolved substrate bias and crosstalk problems [7,8]. The key purpose of the above technologies is to achieve effective substrate isolation between adjacent devices. Up to now, the trench isolation on SOI and the PN junction isolation have mainly been proved to be effective when devices switch at voltages up to 200 V [13,14,15,16,17,18]. For higher voltage applications, GaN-on-Sapphire technology achieves the breakdown voltage of over 2000 V since it avoids vertical breakdown [10]. Upon a sapphire substrate, the substrate isolation can be neglected; meanwhile, the isolation of adjacent devices can be achieved by ion implantation with an ultra-thin buffer structure. As a traditional method, ion implantation even meets the requirements for 900 V applications, as is widely used in the production of commercial discrete GaN devices. Therefore, the GaN-on-Sapphire technology can be utilized for high-voltage discrete devices [19,20]. However, a successful high-voltage monolithic integration not only requires high-voltage blocking bias but also requires mitigation of crosstalk effects under high-voltage dynamic switching conditions, which is rarely discussed in previous reports on GaN-on-Sapphire power integration technology.

This work investigates the effectiveness of isolation approaches considering substrate bias and crosstalk effects in a novel GaN-on-Sapphire monolithic half-bridge power integration platform. With the help of experiments, both the substrate bias effect and the crosstalk effect under dynamic high-voltage switching conditions are explored to investigate the effectiveness of the implantation isolation approach. Then, an improved isolation structure is proposed to further enhance the stability of the high-voltage power ICs on such an integration platform.

2. Device Fabrications and Characteristics

The GaN-on-Sapphire monolithic half-bridge integration structure is schematically depicted in Figure 1, including high-voltage (HV) devices and low-voltage (LV) devices. Other elements, like diodes and capacitors, are not presented here. The GaN epi-structure is for an enhancement-mode high electron mobility transistor with a p-type GaN gate cap (p-GaN HEMT). Upon a 6-inch sapphire substrate, a 100 nm AlN ultrathin buffer (UTB) is grown using a metal organic chemical vapor deposition (MOCVD) system from Aixtron (AIXTRON Ltd., Aachen, Germany), followed by a 300 nm unintentionally doped (UID) GaN channel layer, a 15 nm Al_0.23GaN barrier layer, and a 100 nm p-GaN layer doped with 2 × 10¹⁹ cm⁻³ Mg. The surface is passivated by Si₃N₄, which is etched via a dry etching method using a Lam9500 etcher (Lam Research Corp., Fremont, CA, USA) at room temperature to open the windows for other processes, with CHF₃ as the process gas and an RF power of 350 W. The field plates help redistribute the surface electric field for breakdown voltage optimization. The gate to drain length (L_GD) is 22 μm, the gate to source distance (L_GS) is 1.5 μm, and the gate length (L_G) is 1.7 μm. The power devices have a gate width of 32 mm. The isolation is achieved by 150 keV N⁺ ion implantation at a dose of 1 × 10¹³ cm⁻² using the GSD200 (Axcelis Technologies Inc., Beverly, MA, USA), and the width (W_ISO) is 120 μm.

The typical electrical characteristics measured by a curve tracer (B1505A) are presented in Figure 2. The fabricated devices have a high threshold voltage (Vth) over 2 V, as shown in Figure 2a, when extracted at a drain current (I_D) equal to 10μA/mm at 25 °C and 150 °C, respectively. The output characteristics are presented in Figure 2b, which are suitable for further analysis. The gate leakage current (I_GSS) maintains a normal level of the p-GaN gate, as seen in Figure 2c. The above current-voltage characteristics indicate that the p-GaN HEMT fabricated by UTB technology achieves performance comparable to conventional GaN HEMTs.

The blocking characteristic measured by a curve tracer (B1505A) is shown in Figure 3a. The breakdown voltage (V_BR) of fabricated HV p-GaN HEMT reaches over 1800 V even at 150 °C. Meanwhile, the drain leakage current (I_DSS) is smaller than that of the GaN-on-Si device (usually >1 nA/mm), indicating the superiority of the sapphire substrate in the fabrication of HV GaN HEMT. The leakage current of the implantation isolation structure with W_ISO of 120 μm is shown in Figure 3b. It is observed that the BV of the implantation isolation structure is over 1500 V at 25 °C and 150 °C, respectively. The leakage current is less than 10 μA/mm² at 1000 V and 150 °C. The measured results indicate that the implantation isolation may meet high-voltage applications.

3. Results and Discussions

For traditional GaN-on-Si technology without any substrate isolation, different substrate terminations bring different problems according to previous studies [4,5,6]. When the substrate termination is connected to low-side source, a negative voltage drops on the substrate to the source of high-side devices, forming a substrate bias condition that causes significant Vth shifts of the HV and LV devices in high-side region; when the substrate termination is floating, the charges stored in the substrate cause severe dynamic on-state resistance (R_on) degradation under high-voltage dynamic switching condition; when the substrate termination is connected to the switching (SW) node, a positive voltage is applied between the substrate to source of HV and LV devices in the low-side region, resulting in serious dynamic R_on degradation under high-voltage dynamic switching condition due to buffer trapping [21]. On a sapphire substrate, the above problems are expected to be further explored. The following sections focus on them by conducting comparative investigations between GaN-on-Si and GaN-on-Sapphire platforms, analyzing substrate bias and crosstalk effects, particularly the isolation between high-side and low-side regions, and between high-voltage (power) and low-voltage (logic) devices.

3.1. Isolation Between High Side Region and Low Side Region

A half-bridge configuration is considered a typical topology that includes a high-side region and a low-side region, with working scenarios summarized in Figure 4 according to the above statements, considering substrate biasing effects and half-bridge effects. When on-state devices are stressed, they experience a substrate bias problem, and the Vth of these devices may shift. When off-state devices are stressed, they experience a crosstalk problem, and their I_D may decrease after stress withdrawal. To observe the suppression effectiveness of the GaN-on-Sapphire devices, experiments under these stress conditions are carried out.

For substrate biasing effects, typical IV measurements using a curve tracer (B1505A, Keysight Technologies, Santa Rosa, CA, USA) can demonstrate the issues. The source to substrate voltage (V_SB) is applied when measuring the transfer characteristics of the device. As presented in Figure 5a,b, when positive V_SB is applied, which corresponds to the situations of high-side devices in Figure 4a,b, the Vth of GaN-on-Si devices shifts a lot, while the Vth of the proposed GaN-on-Sapphire devices remains stable. As shown in Figure 5c,d, when a negative V_SB is applied, which corresponds to the situations of the low side device in Figure 4c, the Vth of both kinds of devices performs stably. The results indicate that GaN-on-Si monolithic half-bridge devices will not work well under high-voltage conditions with the configurations shown in Figure 4a,b. However, GaN-on-Sapphire monolithic half-bridge devices will work well without substrate bias problems.

For crosstalk effects, the negative V_SB will stress the devices. This negative bias corresponds to the high side device in Figure 4c and the low side devices in Figure 4a,d, then the R_on of stressed devices will increase after the stress is withdrawn. For the proposed GaN-on-Sapphire power integration platform, the substrate is mainly floating. However, after making back-metal, the substrate can also be connected to different terminations if necessary. In this way, the dynamic R_on degradation under high-voltage switching conditions with different substrate connections can be verified. A test circuit shown in Figure 6a is adopted to test the dynamic R_on under floating and positive-biased substrate conditions. In the circuit, a power device D1 and a diode D2 are connected to the monolithic half-bridge, and the common substrate can be selected to different terminations. As seen in Figure 6b, during period I, the low-side device is turned on without being stressed; during period II, D1 is turned on and the R_on of the low-side device can be measured with the help of a clamping circuit, and this R_on value can be used as the initial value for normalization; during period III, the low-side device suffers the stress; during period IV, the R_on degradation can be measured. All the terminal voltages are monitored by an oscilloscope (MSO44) with voltage probes (TPP0500B), and the drain current is measured by a current probe (TCP0030A).

To make the comparisons, two adjacent p-GaN HEMTs sharing the Si substrate are also tested. The measured R_on of GaN-on-Si and GaN-on-Sapphire devices after a 400 V stress is presented in Figure 7. It is observed that the GaN-on-Si devices suffer from serious dynamic R_on degradation of the low-side device when the substrate is floating or connected to the SW node. On the contrary, the monolithic GaN-on-Sapphire devices are stable no matter which termination is connected to the substrate. The advantages of GaN-on-Sapphire devices can be attributed to the elimination of electron injection to the buffer because of the thick sapphire substrate, and meanwhile, no charges can be stored in the insulated substrate. In detail, the floating substrate and SW-connected substrate could bring a high negative V_SB. For GaN-on-Si devices, the conductive substrate withstands a small voltage drop, leading to a high longitudinal electric field in the channel and buffer layers. Hence, the electrons are injected into the buffer layer under the high longitudinal electric field, causing the degradation of R_on. For GaN-on-Sapphire devices, the insulated substrate withstands most of the voltage drop, leading to a small longitudinal electric field on the channel and buffer layers. Hence, the electron injections are suppressed, bringing minimal degradation of R_on. Those results indicate that the crosstalk effects under dynamic high-voltage switching conditions are successfully suppressed between high-side and low-side power devices in a half-bridge configuration, regardless of the substrate connection or termination.

3.2. Isolation Between High-Voltage Devices and Low-Voltage Devices

Power ICs can also include low-voltage peripheral devices for implementing a variety of functions, such as gate drive and sensing [22]. The performance of the peripheral devices may be influenced by the high-voltage signals from monolithically integrated high-voltage devices via crosstalk effects. To evaluate crosstalk effects between high-voltage and low-voltage devices, the two devices are connected to different voltage source-meters [10], as shown in Figure 8. When a pulsed V_stress is applied to the high-voltage device, the I_D of the low-voltage HEMT is monitored to observe the crosstalk effects. The voltage source and source-meter used for crosstalk tests are 2410 and TH1992, respectively.

The measured results are shown in Figure 9. It is observed that before V_stress is applied, the I_D gradually decreases within 0.5% due to the self-heating effect; when the V_stress is switched to a high level, I_D increases slightly; when the V_stress is switched to a low level again, I_D decreases within 3%, but gradually recovers. To inspect the mechanisms behind those phenomena, further mixed-mode Technology Computer Aided Design (TCAD) simulations have been carried out. In the simulations, a low-voltage HEMT is built, beside which is a highly resistive isolation region of 120 μm. A high-voltage electrode is also built across the isolation region to apply V_stress. The high resistivity of such an isolation region is achieved by adding acceptor traps with an energy level of 2.6 eV and a density of 4.5 × 10¹⁸ cm⁻³. Finally, the leakage current of this isolation region in the simulation is about 2.5 × 10⁻⁷ A/mm² under 400 V, approximately meeting the measured data in Figure 3b. Other model parameters in the simulation can be found in [23].

Figure 10 gives the simulated I_D of the low-voltage HEMT over one duration of V_stress. We can see that the variation trend of I_D meets the measured trend: I_D increases when V_stress transitions to a high level, and I_D decreases when V_stress transitions to a low level. To understand the results, the physical parameter distribution under three typical states (State A to C in Figure 10a) is extracted, as presented in Figure 10b. Compared with states A and C, a higher electron concentration can be observed in the low-voltage HEMT channel at state B, which directly results in high I_D. Since the implantation region withstands the high V_stress voltage, it acts as a capacitor (C_imp). Then, the channel region becomes the negative terminal of such a capacitor. During the switching process, the varying V_stress leads to a varying electric field near the isolation area, which causes the movement of charges in the dielectric (implantation region); electrons displace and accumulate in the channel region. Finally, the carrier concentration in the channel layer increases and total I_D increases, as presented in Figure 11a. To further prove this process, the electron distributions during transient I have been extracted and presented in Figure 11b, from which it is observed that the electron concentration in the lower part of the channel layer increases as V_stress gradually increases. Considering the electrons captured by implantation-induced acceptor traps [24] could be released under a high electrical field, the electrons injected into the channel layer may come from the implantation region.

Conversely, during transient II, C_imp discharges as V_stress drops. Then, the electrons in the channel layer move back to the implantation region, as seen in Figure 12a. Consequently, the carrier concentration in the channel layer decreases, and I_D decreases. The electron distributions during transient I have been extracted and presented in Figure 12b, which proves that the electron concentration in the channel decreases with time. The varied electric field near the implantation region causes high displacement current (I_disp), and the total I_D decreases below the initial value. As for the electrons driven into the implantation region, they could become trapped by implantation-induced acceptor traps again. However, unlike state B, there is no high electric field in the implantation region at state C, so the charges near the implantation region should finally come to an equilibrium state. Therefore, the electrons captured by traps are released, and I_D will recover gradually. It is noted that the simulations in this paper only provide phenomena validation; the duration of V_stress and the trap levels are not carefully matched with actual situations. Hence, the recovery phenomena in the TCAD simulation results do not repeat the test results.

The above measured instability of I_D does not seem significant; however, these kinds of monolithic power ICs are usually operated under high voltage, so some undulations may cause fault turn-on of some transistors, and, finally, lead to the failure of the system function. These discussions indicate that the capacitance of implantation (C_imp) region should be reduced to suppress I_disp during switching transient and charge accumulations in the channel layer under high voltage bias. Increasing the width of the isolation region can be a possible method to reduce the capacitance of the isolation region. However, a large width will increase the chip area, which is unacceptable for commercialization. To eliminate the capacitance more effectively, an implantation with a trench structure can be adopted [10], as shown in Figure 13a. With a trench isolation structure, the capacitance can be reduced. Thus, the capacitive coupling-induced I_disp is reduced a lot; at the same time, the accumulated charges (Q = C_imp × V_stress) can be reduced. In this way, a highly stable I_D can be achieved, which is helpful for circuit design. When adopting the test method in Figure 8a, the measured I_D results are presented in Figure 13b, indicating perfect elimination of crosstalk effects even under 175 °C and 900 V stress.

4. Conclusions

The isolation approaches in GaN-on-Sapphire power monolithic integrated circuits, considering substrate bias and crosstalk between adjacent devices, are investigated in this paper. In conclusion, an implantation isolation within a trench structure is recommended as the isolation structure for more stable performances. Thanks to the insulated sapphire substrate, the substrate bias effects between the high side region and the low side region can be readily suppressed in the fabricated monolithic power ICs. Meanwhile, experiments demonstrate that the implantation isolation can successfully suppress the crosstalk between the high side region and the low side region, as well. However, the implantation isolation leads to weak crosstalk effects between HV and LV devices, showing a 3% degradation in I_D under 400 V stress. A trench inside the implantation isolation is proposed to suppress the crosstalk effects, and experiments successfully prove its effectiveness.