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Micromachines
Volume 16
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10.3390/mi16010064
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Article

Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications

by
Chakali Chandrasekhar
1,
Mohammed Mahaboob Basha
2,*,
Sari Mohan Das
3,
Oruganti Hemakesavulu
4,
Mohan Dholvan
2 and
Javed Syed
5,*
1
Department of ECE, Sri Venkateswara College of Engineering, Tirupati 517507, AP, India
2
Department of ECE, Sreenidhi Institute of Science and Technology (Autonomous), Hyderabad 501301, TG, India
3
Department of ECE, SVR Engineering College, Nandyal 518501, AP, India
4
Department of EEE, Annamacharya University, Rajampet 516126, AP, India
5
Department of Mechanical Engineering, College of Engineering, King Khalid University, Abha 61421, Saudi Arabia
*
Authors to whom correspondence should be addressed.
Micromachines 2025, 16(1), 64; https://doi.org/10.3390/mi16010064
Submission received: 9 December 2024 / Revised: 28 December 2024 / Accepted: 30 December 2024 / Published: 5 January 2025
(This article belongs to the Section E: Engineering and Technology)
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Abstract

In modern ICs, sub-threshold voltage management plays a significant role due to its perspective on energy efficiency and speed performance. Level shifters (LSs) play a critical role in signal exchange among multiple voltage domains by ensuring signal integrity and the reliable operation of ICs. In this article, a Pass-Transistor-Enabled Split Input Voltage Level Shifter (PVLS) is designed for area, delay, and power-efficient applications with a wide voltage conversion range. The represented low-power LS structure is a general blend of both pull-up and pull-down networks that perform level-up or level-down shifts. The proposed PVLS is incorporated with the multi-threshold CMOS technique and a load-balancing driving split inverter to limit high static current, leakage power, and performance degradation. The schematic structure could be able to convert voltages from low to high as well as high to low. The architecture design has the lowest silicon area. The implementation of the proposed design was taken under 55 nm CMOS technology. The represented LS could be able to convert voltage ranges between 0.3 V and 1.3 V, which has a dynamic power of 2.00 nW. The overall propagation delay of the LS is 90 ps and an area of 7.66 µm2 for an input frequency of 1 MHz.
Keywords: low threshold voltage; power-efficient; sub-threshold operation; multi-threshold CMOS; IoT applications low threshold voltage; power-efficient; sub-threshold operation; multi-threshold CMOS; IoT applications

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MDPI and ACS Style

Chandrasekhar, C.; Basha, M.M.; Das, S.M.; Hemakesavulu, O.; Dholvan, M.; Syed, J. Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications. Micromachines 2025, 16, 64. https://doi.org/10.3390/mi16010064

AMA Style

Chandrasekhar C, Basha MM, Das SM, Hemakesavulu O, Dholvan M, Syed J. Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications. Micromachines. 2025; 16(1):64. https://doi.org/10.3390/mi16010064

Chicago/Turabian Style

Chandrasekhar, Chakali, Mohammed Mahaboob Basha, Sari Mohan Das, Oruganti Hemakesavulu, Mohan Dholvan, and Javed Syed. 2025. "Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications" Micromachines 16, no. 1: 64. https://doi.org/10.3390/mi16010064

APA Style

Chandrasekhar, C., Basha, M. M., Das, S. M., Hemakesavulu, O., Dholvan, M., & Syed, J. (2025). Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications. Micromachines, 16(1), 64. https://doi.org/10.3390/mi16010064

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