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Open AccessArticle

Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device

by Yinhua Cui 1,†, Jeong Yeul Jeong 2,†, Yuan Gao 1 and Sung Gyu Pyo 1,*
1
School of Integrative Engineering, Chung-Ang University, Seoul 06974, Korea
2
Process Development Center, Magnachip Semiconductor, Seoul 15213, Korea
*
Author to whom correspondence should be addressed.
These two authors contributed equally to this work.
Micromachines 2020, 11(2), 170; https://doi.org/10.3390/mi11020170
Received: 29 November 2019 / Revised: 24 January 2020 / Accepted: 6 February 2020 / Published: 6 February 2020
(This article belongs to the Special Issue Selected Papers from the ICAE 2019)
Here, we developed the optimal conditions in terms of physical and electrical characteristics of the barrier and tungsten (W) deposition process of a contact module, which is the segment connecting the device and the multi-layer metallization (MLM) metal line in the development of 100 nm-class logic devices. To confirm its applicability to the logic contact of barrier and W films, a contact hole was formed, first to check the bottom coverage and the filling status of each film, then to check the electrical resistance and leakage characteristics to analyze the optimal conditions. At an aspect ratio of 3.89:1, ionized metal plasma (IMP) Ti had a bottom coverage of 40.9% and chemical vapor deposition (CVD) titanium nitride (TiN) of 76.2%, confirming that it was possible to apply the process to 100 nm logic contacts. W filling was confirmed, and a salicide etching rate (using Radio Frequency (RF) etch) of 13–18 Å/s at a 3.53:1 aspect ratio was applied. The etching rate on the thermal oxide plate was 9 Å/s. As the RF etch amount increased from 50–100 Å, the P active resistance increased by 0.5–1 Ω. The resistance also increased as the amount of IMP Ti deposition increased to 300 Å. A measurement of the borderless contact junction leakage current indicated that the current in the P + N well increased by more than an order of magnitude when IMP Ti 250 Å or more was deposited. The contact resistance value was 0.5 Ω. An AC bias improved the IMP Ti deposition rate by 10% in bottom coverage, but there was no significant difference in contact resistance. In the case of applying IMP TiN, the overall contact resistance decreased to 2 Ω compared to CVD TiN, but the distribution characteristics were poor. The best results were obtained under the conditions of RF etch 50 Å, IMP Ti 200 Å, and CVD TiN 2 × 50 Å.
Keywords: junction leakage; contact resistance; contact metallization junction leakage; contact resistance; contact metallization
MDPI and ACS Style

Cui, Y.; Jeong, J.Y.; Gao, Y.; Pyo, S.G. Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device. Micromachines 2020, 11, 170.

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