A Novel Real-Time Multi-Channel Error Calibration Architecture for DBF-SAR

Abstract

Digital Beamforming SAR (DBF-SAR) provides high-resolution wide-swath imaging capability, yet it is affected by inter-channel amplitude, phase and time-delay errors induced by temperature variations and random error factors. Since all elevation channel data are weighted and summed by the DBF module in real time, conventional record-then-compensate approaches cannot meet real-time processing requirements. To resolve the problem, a real-time calibration architecture for Intermediate Frequency DBF (IFDBF) is presented in this paper. The Field-Programmable Gate Array (FPGA) implementation estimates amplitude errors through simple summation, time-delay errors via a simple counter, and phase errors via single-bin Discrete-Time Fourier Transform (DTFT). The time-delay and phase error information are converted into single-tone frequency components through Dechirp processing. The proposed method deliberately employs a reduced-length DTFT implementation to achieve enhanced delay estimation range adaptability. The method completes calibration within tens of PRIs (under 1 s). The proposed method is analyzed and validated through a spaceborne simulation and X-band 16-channel DBF-SAR experiments.

1. Introduction

With the development of spaceborne synthetic aperture radar (SAR) towards multi-mode, high-resolution wide-swath (HRWS), traditional single-channel SAR cannot simultaneously achieve wide swath and high image resolution due to the inherent limitations imposed by the minimum antenna area constraint [1,2,3]. Digital Beamforming (DBF) enhances the signal-to-noise ratio (SNR) and ambiguity performance of wide-swath SAR imagery without degrading resolution [4]. This is achieved through flexible beam steering with digital arrays [5] and joint space-time processing of multi-channel signals [6]. By improving system SNR and extending single-observation coverage, next-generation DBF-SAR systems offer substantial advantages for interferometric mapping techniques, including InSAR [7,8] and MTInSAR [9,10]. DBF has emerged as a critical research direction for next-generation spaceborne SAR systems due to its demonstrated advantages in HRWS imaging [11,12].

However, inter-channel inconsistencies in DBF systems can directly degrade signal coherence and reduce SNR [13,14,15]. The real-time beamforming process presents significant challenges for on-orbit channel error calibration [16]. Channel errors in DBF systems include amplitude errors, phase errors, and time-delay errors. Most conventional error estimation algorithms are based on echo signal processing, employing a record-then-compensate approach. Wu et al. proposed using isolated scatterers to extract unambiguous signals for channel mismatch correction [17]. Liu et al. achieved reference-free calibration by leveraging clutter spatial correlation [18]. Zhou et al. achieved joint high-precision estimation of Doppler centroid and phase errors through signal subspace uniqueness and antenna pattern weighting [19]. Cai et al. established an explicit model of virtual target amplitude-phase errors based on the minimum L1 norm in the image domain [20]. This approach eliminates the requirement for redundant channels while achieving high-precision channel error estimation. The above-mentioned methods demand significant computational resources. The latency between data acquisition and error estimation exceeds one second, failing to meet hard real-time requirements.

The Cal-Tone-based approach offers a feasible solution for real-time multi-channel error estimation [21,22,23]. However, it requires additional Radio Frequency (RF) components for cal-tone to support real-time calibration. Moreover, due to the periodic characteristics of single-tone signals, this method can only measure amplitude and phase errors, whereas time-delay errors cannot be estimated. Phase shifts exceeding ${360}^{°}$ due to time-delay errors cannot be distinguished from those caused by smaller delays in tone-signal-based methods, leading to measurement ambiguity. Existing time-delay error estimation methods primarily depend on external reference sources and encounter difficulties in attaining real-time processing capabilities [24].

Amplitude and phase errors primarily stem from temperature variations in the short term and component aging in the long term. Time-delay errors mainly originate from synchronization mismatches during initialization among multiple polyphase Analog-to-Digital Converters (ADCs) in multi-channel DBF systems. The sampling timing deviation introduces ns-level delays [25], typically manifesting as a full-sample or half-sample shift relative to the reference channel.

To ensure DBF-SAR’s inter-channel consistency, a real-time multi-channel error calibration architecture for calibrating amplitude, phase, and time-delay errors without requiring additional Radio Frequency (RF) components is proposed in this paper. The proposed method achieves a latency of only tens of Pulse Repetition Frequency (PRF) cycles (under 1 second). In synthetic aperture radar signal processing, the Dechirp algorithm serves as a critical bandwidth compression technique that downconverts wideband radar returns to narrowband signals, enabling efficient subsequent processing [26]. As a key innovation of our methodology, Dechirp-based preprocessing is applied to reduce the wideband Linear Frequency Modulation (LFM) calibration signal to a single-frequency component, enabling precise error calibration. This transformation enables high-accuracy error estimation through two distinct approaches. First, time-delay errors are translated into frequency offsets of the tonal signal. This linear conversion enables direct measurement through a basic Field-Programmable Gate Array (FPGA) counter, eliminating complex spectral processing. Second, the spectrally concentrated energy of the single-tone signal facilitates phase error detection through Discrete-Time Fourier Transform (DTFT) analysis. The proposed method achieves $\pm 0.1\mathrm{dB}$ amplitude and $\pm 1$ degree phase accuracy under 20 dB SNR internal calibration conditions.

The internal calibration loop of the DBF-SAR system is illustrated in Figure 1. The direct digital synthesizer (DDS) produces an LFM waveform that undergoes in-phase/quadrature (I/Q) mixing to upconvert it to the RF carrier frequency. An RF switching matrix precedes the TR module, providing configurable signal routing to either the transmission path or TRM calibration loop. The signal coupled into the TRM calibration loop [27] is output through a circulator during the internal calibration procedure. The TRM’s output signal is amplified, mixed down, and filtered in the receiver chain to obtain the Intermediate Frequency (IF) signal.

Figure 1. Block diagram of the top-level hardware structure of the DBF-SAR internal calibration loop. The received signals from each channel are amplified, downconverted (antialiasing filter follows), and digitized to the IF signals. The FPGA performs real-time multi-channel error calibration and DBF synthesis processing.

A weight generator and Intermediate Frequency Digital Beamforming (IFDBF) real-time processing architecture is proposed in [28]. In the IFDBF architecture, the ADC-sampled IF signal is converted to I/Q base-band via Digital DownConvertor. The IFDBF architecture supports multi-channel error compensation capabilities. Specifically, amplitude and phase errors are compensated through DBF weighting, while time-delay errors are corrected via digital delay components. In [28], errors are assumed as prior knowledge without addressing their acquisition methods. The proposed error estimation approach, which utilizes the IFDBF architecture for simultaneous estimation and compensation, can be effectively integrated with existing techniques to guarantee on-orbit operational reliability of DBF-SAR systems.

This paper is organized as follows. Section 2 introduces the proposed multi-channel error estimation and compensation algorithm. Section 3 presents the FPGA-based real-time processing architecture implementation. Section 4 verifies the performance and efficacy through simulations and experiments. Section 5 discusses the algorithm’s applicability to other multi-channel systems. Section 6 concludes the paper.

2. Proposed Methods

The proposed method employs a sequential three-stage architecture to address amplitude, time-delay, and phase errors, where each error type undergoes dedicated measurement followed by immediate compensation.

Considering a linear frequency modulation (LFM) signal. The calibration pulse $\mathrm{s}\left(t\right)$ transmitted by the internal calibrator can be expressed as

$$\begin{array}{c}\hfill \mathrm{s}\left(t\right)=rect\left({\displaystyle \frac{t}{T_r}}\right)cos\left(2\pi f_{0}t+\pi K_r{t}^2\right)\end{array}$$

(1)

where $T_r$ and $f_0$ represent the pulse width and the carrier frequency, respectively; and $K_r$ and t denote the chirp rate and the fast time, respectively.

The calibration signal is transmitted through the internal calibration loop, passing sequentially through the TR module, microwave module, and calibrator before being received. A short delay $\Delta t$ occurs from signal transmission to reception. For a system exhibiting simultaneous amplitude error $\Delta A_n$, phase error $\Delta {\phi }_n$, and time-delay errors $\Delta t_n$, the baseband signal ${\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}\left(t\right)$ received at the nth channel is expressed as follows:

$$\begin{array}{c}\hfill {\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}\left(t\right)=\Delta A_n·rect\left({\displaystyle \frac{t-\Delta t_n}{T_r}}\right)exp\left(j·\left(\pi K_r{\left(t-\Delta t_n\right)}^2-2\pi f_0\Delta t_n+\Delta {\phi }_n\right)\right)\end{array}$$

(2)

The amplitude error can be estimated by performing a simple summation over the real part of the baseband signal ${\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}\left(t\right)$.

$$\begin{array}{c}\hfill A_n=\sum abs\left(real\left({\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}\left(t\right)\right)\right)\end{array}$$

(3)

The amplitude compensation value $CAL\_A_n$ for the nth channel is:

$$\begin{array}{c}\hfill CAL\_A_n=A_1/A_n\end{array}$$

(4)

After compensating for channel amplitude errors, all channels demonstrate consistent amplitude $A_1$. This common scaling factor is algebraically eliminated in subsequent analyses. When recalibrating, the baseband signal received by the nth channel becomes:

$$\begin{array}{cc}\hfill {\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}^{\prime }\left(t\right)& =CAL\_A_n·{\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}\left(t\right)\hfill \\ \hfill & =rect\left({\displaystyle \frac{t-\Delta t_n}{T_r}}\right)exp\left(j·\left(\pi K_r{\left(t-\Delta t_n\right)}^2-2\pi f_0\Delta t_n+\Delta {\phi }_n\right)\right)\hfill \end{array}$$

(5)

The next step is time-delay error estimation. A critical challenge arises from the substantial frequency disparity between the space-grade FPGA primary clock (typically around 100 MHz) and the ADC’s sampling clock (typically exceeding 1 GHz). This frequency mismatch creates a fundamental limitation in accurately characterizing GHz-range clock timing errors using only a 100-MHz-range reference clock.

For precise time-delay estimation, the signal requires initial dechirping processing. Let ${\mathrm{s}}_{\mathrm{REF}}\left(t\right)$ denote the dechirping reference signal:

$$\begin{array}{c}\hfill {\mathrm{s}}_{\mathrm{REF}}\left(t\right)=rect\left({\displaystyle \frac{t}{T_r}}\right)exp\left(j·\left(-\pi K_r{t}^2\right)\right)\end{array}$$

(6)

The dechirped signal received from the nth channel is:

$$\begin{array}{cc}\hfill {\mathrm{s}}_{{\mathrm{CAL}}_{\mathrm{n}}}^{\prime }\left(t\right)& ={\mathrm{s}}_{{\mathrm{BB}}_{\mathrm{n}}}^{\prime }\left(t\right)·{\mathrm{s}}_{\mathrm{REF}}\left(t\right)\hfill \\ \hfill & =rect\left({\displaystyle \frac{t-\Delta t_n}{T_r}}\right)·rect\left({\displaystyle \frac{t}{T_r}}\right)exp\left(j·\left(\pi K_r\left(-2\Delta t_{n}t+\Delta t_n^2\right)-2\pi f_0\Delta t_n+\Delta {\phi }_n\right)\right)\hfill \end{array}$$

(7)

The signal $s_{{\mathrm{CAL}}_n}^{\prime }\left(t\right)$ is essentially a single-tone waveform with a rectangular envelope and constant phase terms. The frequency of the single-tone waveform is:

$${\mathrm{f}}_{dcp}=\left(-K_r\Delta t_n\right)$$

(8)

Dechirp processing amplifies the inter-channel timing differences, making even minor discrepancies in the high-speed clock clearly observable in low-speed clock measurements. Section 4 validates the proposed algorithm’s effectiveness in compensating synchronization errors at sub-sample precision, specifically addressing half-sample-grid misalignments that may occur in polyphase ADC (time-interleaved ADC) clock architectures.

The single-tone signal is converted to a square wave, then the frequency is derived from period measurements instead of being measured directly. In FPGA implementations, square wave measurement can be efficiently realized through dedicated trigger circuits and digital counters.

Direct application of conventional single-threshold triggering would introduce glitches in the shaped square wave due to noise interference, as illustrated in Figure 2a. To mitigate this problem, a hysteresis comparator with Schmitt-trigger characteristics (with ±TH threshold window) was implemented. Although the shaped square wave demonstrates a consistent propagation delay compared to the source signal, this shift has no impact on cycle duration or frequency measurement, as demonstrated in Figure 2b.

Figure 2. (a) Conventional single-threshold triggering would introduce glitches. (b) The Schmitt trigger generates a square wave from the single-tone signal, with its inherent delay having no impact on frequency measurement.

The square wave frequency is

$$\begin{array}{c}\hfill {\mathrm{f}}_{{\mathrm{CAL}}_n}=\left|-K_r\Delta t_n\right|\end{array}$$

(9)

The end-to-end absolute latency of the nth channel, spanning from transmitter to receiver, is calculated in real-time within the FPGA:

$$\begin{array}{c}\hfill \Delta t_n={\displaystyle \frac{N_p·F_{\mathrm{FPGA}}}{\mathrm{CNT}·\left|K_r\right|}}\end{array}$$

(10)

where $N_p$ represents the number of square wave periods (typically ⩾8 for averaging to achieve better noise immunity), $F_{\mathrm{FPGA}}$ is the FPGA primary clock frequency for the accumulated counter, and CNT indicates the accumulated counter value over $N_p$ periods. Using Channel 1 as the reference, the relative delay compensation of all other channels can be calculated as follows:

$$\begin{array}{c}\hfill CAL\_t_n=\Delta t_1-\Delta t_n\end{array}$$

(11)

In DBF-SAR systems, inter-channel time-delay errors primarily originate from asynchronous ADC sampling clocks during initialization. Taking a ${180}^{°}$ dual-phase ADC configuration as an example, the minimum clock misalignment unit is half the sampling clock period. Thus, the calibrated delay (in samples) is given by:

$$\begin{array}{c}\hfill {FrGrid}_n=round\left(F_r·\mathrm{CAL}\_t_n·2\right)/2\end{array}$$

(12)

The integer part of $FrGri{d}_n$ is compensated by directly shifting sample points, while its fractional part is corrected via sinc interpolation. In IFDBF systems, employing digital delay elements for active time-delay compensation introduces a parasitic phase shift [28]. The parasitic phase requiring compensation is

$$\begin{array}{c}\hfill \varphi I{F}_n=-2\pi f_{\mathrm{IFB}}{\displaystyle \frac{FrGri{d}_n}{F_r}}\end{array}$$

(13)

where $F_r$ is the ADC sampling frequency. $f_{\mathrm{IFB}}$ is not the original Intermediate Frequency (IF) $f_{\mathrm{IF}}$ sampled by the ADC, but rather its aliased “complex digital frequency” within the baseband principal interval under Nyquist sampling.

$$\begin{array}{c}\hfill f_{\mathrm{IFB}}=mod\left(f_{\mathrm{IF}},\left({\displaystyle \frac{F_r}{2}}\right)\right)-mod\left(floor\left({\displaystyle \frac{f_{\mathrm{IF}}}{\frac{F_r}{2}}}\right),2\right)\times \left({\displaystyle \frac{F_r}{2}}\right)\end{array}$$

(14)

For example, with an ADC sampling rate $F_r$ of 1200 MHz and an input signal centered at $f_{\mathrm{IF}}$ = 900 MHz, the resulting $f_{\mathrm{IFB}}$ becomes −300 MHz due to spectral folding, as illustrated in Figure 3:

Figure 3. Under Nyquist sampling, the observed complex frequency of a digital I/Q signal is constrained to its principal value range. A 900 MHz tone sampled at 1200 MHz appears aliased at −300 MHz.

After compensating for channel delay errors, all channels maintain temporal synchronization with Channel 1, each possessing the same propagation delay $\Delta t_1$. When the signal passes through the calibration loop again, the dechirped signal of the nth channel is:

$$\begin{array}{cc}\hfill & {\mathrm{s}}_{{\mathrm{CAL}}_{\mathrm{n}}}^{″}\left(t\right)\hfill \\ \hfill & =rect\left({\displaystyle \frac{t-\Delta t_1}{T_r}}\right)·exp\left(j·\left(\pi K_r\left(-2\Delta t_{1}t+\Delta t_1^2\right)-2\pi f_0\Delta t_n+\Delta {\phi }_n+\varphi I{F}_n\right)\right)\hfill \end{array}$$

(15)

The Fourier transform enables high-precision computation of inter-channel phase differences.

$$\begin{array}{c}\hfill S_{{\mathrm{CAL}}_n}\left(f\right)={\int }_{-\infty }^{+\infty }{s}_{{\mathrm{CAL}}_n}\left(t\right)exp(-j2\pi ft)dt\end{array}$$

(16)

However, even FFT operations impose high computational costs for FPGA-based real-time estimation of a long sampled sequence. Fortunately, the dechirped signal’s energy is predominantly concentrated in a single-tone component, thus permitting replacement of the full-spectrum FFT with a targeted DTFT computation at this specific frequency bin.

$$\begin{array}{c}\hfill S_{{\mathrm{CAL}}_n}\left(f_{dcp}\right)={\int }_{-\infty }^{+\infty }{s}_{{\mathrm{CAL}}_n}\left(t\right)exp(-j2\pi f_{dcp}t)dt\end{array}$$

(17)

In practical implementations, the FPGA utilizes M-points’ discrete summation operations to approximate the continuous integration process.

$$\begin{array}{c}\hfill S_n\left(f_{dcp}\right)=\sum _{k=1}^M{s}_{{\mathrm{CAL}}_n}\left(k\right)exp\left(-j2\pi {\displaystyle \frac{f_{dcp}}{F_r}}k\right),S_n\left(f_{dcp}\right)\in {\mathbb{C}}^{1\times 1}\end{array}$$

(18)

Note that the discrete summation in DFT with finite points leads to different widths of spectral response. The half-power width of the main lobe for a single-tone frequency response is given by:

$$\begin{array}{c}\hfill {\mathrm{Width}}_{3\mathrm{dB}}\approx 0.886·{\displaystyle \frac{F_r}{M}}\left(Hz\right)\end{array}$$

(19)

Normally, wider main lobes reduce frequency resolution in spectral estimation. However, the proposed method uses optimized short-window DTFT to improve error detection adaptability. For a spaceborne DBF-SAR system, the physical cable length L of the calibration signal path is known a priori. Although the actual signal path length differs from L by less than 1 meter, this deviation is within acceptable tolerance.

Under the simulation parameters described in Section 4 (sampling frequency $F_r$ = 1200 MHz, calibration signal chirp rate $K_r$ = $-{10}^{13}$ Hz/s, M = 2000 sampling points, and reference length L = 10 m), the 3 dB bandwidth is approximately 531 kHz, whereas the reference $f_{dcp}$ frequency is around 333 kHz. Therefore, any single-tone signal between 67.5 kHz and 598.5 kHz falls within the effective detection range of the DTFT-based digital filter. The DTFT filter responses are illustrated in Figure 4.

Figure 4. A DTFT with fewer points exhibits a wider frequency bandwidth, enabling phase estimation across a broad range (green shaded area).

With reduced summation points, one DTFT detects all channels’ phase responses. The phase response of signal $s\left(t\right)$ is derived via DTFT.

$$\begin{array}{c}\hfill angle\left(S_n\left(f_{dcp}\right)\right)=\pi K_r{\left(\Delta t_1\right)}^2-2\pi f_0\Delta t_n+\Delta {\phi }_n+\varphi I{F}_n\end{array}$$

(20)

The phase error estimate for the nth channel is:

$$\begin{array}{c}\hfill \Delta {\phi }_n=angle\left(S_n\left(f_{dcp}\right)\right)-\pi K_r{\left(\Delta t_1\right)}^2+2\pi f_0\Delta t_n-\varphi I{F}_n\end{array}$$

(21)

Omitting terms common to all channels simplifies the expression to:

$$\begin{array}{cc}\hfill \Delta {\phi }_n& =angle\left(S_n\left(f_{dcp}\right)\right)-2\pi {\displaystyle \frac{f_0}{F_r}}{FrGrid}_n+2\pi {\displaystyle \frac{f_{\mathrm{IFB}}}{F_r}}{FrGrid}_n\hfill \\ \hfill & =angle\left(S_n\left(f_{dcp}\right)\right)+2\pi {\displaystyle \frac{{FrGrid}_n}{F_r}}\left(f_{\mathrm{IFB}}-f_0\right)\hfill \end{array}$$

(22)

The above equation demonstrates that accurate phase error estimation requires eliminating parasitic phase effects from two distinct sources: RF and IF. The RF parasitic phase arises from delay errors, while the IF parasitic phase is induced by active digital delay compensation.

The phase compensation value is:

$$\begin{array}{c}\hfill \mathrm{CAL}\_P_n=\mathrm{wrapToPi}\left(\Delta {\phi }_1-\Delta {\phi }_n\right),CAL\_P_n\in [-\pi ,\pi ]\end{array}$$

(23)

The $\mathrm{wrapToPi}(•)$ function maps angles exceeding ${360}^{°}$ to the principal value interval $[-\pi ,+\pi ]$. This operation must be performed as the final step after absolute phase values from all channels have been obtained.

3. Real-Time Processing Architecture

During error estimation, only one channel’s signal is permitted to pass per PRF interval. The IFDBF signal flow diagram in Figure 5 indicates active channels with colored highlighting, while blocked signal paths remain uncolored.

Figure 5. Signal path during internal calibration error correction in IFDBF.

For an IFDBF architecture with N channels in elevation, the error estimation process comprises three sequential stages: amplitude, time delay, and phase. Each stage requires N consecutive PRFs to measure absolute errors from all N channels, followed by relative error and compensation value generation. The error correction diagram is shown in Figure 6.

Figure 6. Proposed error correction flow diagram.

The first step estimates amplitude errors. Only the calibrated k-th channel’s weight is set to 1, while all others are zero. After N PRIs to scan all channels, the amplitude compensation values ($\mathrm{CAL}\_A_1$ to $\mathrm{CAL}\_A_n$) are fed back. The second step estimates time-delay errors. Here, only the k-th channel’s weight is set to $\mathrm{CAL}\_A_k$ (others are zero). After N-PRI (Pulse Repetition Interval) scanning, time-delay compensation values ($FrGri{d}_1$ to $FrGri{d}_n$) are fed back. The third step estimates phase errors. The k-th channel’s weight remains $\mathrm{CAL}\_A_k$ (others zero), with all channels now applying pre-calibrated delays (${FrGrid}_1$ to ${FrGrid}_n$). After N-PRI scanning, phase compensation values ($\mathrm{CAL}\_P_1$ to $\mathrm{CAL}\_P_n$) are fed back. The FPGA implementation architecture is illustrated in Figure 7.

Figure 7. Proposed FPGA implementation architecture.

The compensation methods for amplitude and phase errors in real-time IFDBF weight generation were introduced in [28]. As illustrated in Figure 8, the digital delay compensation employs distinct approaches for integer and fractional sample compensation. Integer-sample delays are implemented through direct data shifting. Fractional-sample delays are achieved using an 8-tap FIR filter with coefficients derived from sinc interpolation kernels sampled at 0/32, 1/32, 2/32, …, 31/32 intervals.

Figure 8. Digital delay component with integer and fractional delay.

The Single bin DTFT implementation closely resembles the DBF process, as both involve time-varying weighting and summation of input signals. For DTFT, the weighting coefficients are generated by multiplying a constant term $(-2\pi f_{dcp}/F_r)$ with a time-varying counter k to obtain the phase, followed by CORDIC [29] IP core-based computation of cosine/sine weights. The frequency response at $f_{dcp}$ is obtained by performing complex multiplication between the DTFT’s time-varying weights and the dechirped single-tone signal, followed by summation. The FPGA implementation block diagram of the Single bin DTFT is shown in Figure 9.

Figure 9. FPGA implementation block diagram of the Single bin DTFT.

By estimating only a single channel’s error component per PRI, the design achieves significant resource sharing, reducing hardware implementation costs. The architecture utilizes: nine multipliers and two dividers, two CORDIC IP cores (including one dedicated to DTFT frequency response phase estimation) and one DDS IP core for signal generation.

4. Simulation and Experimental Results

This section presents simulation and experimental results to validate the performance of the proposed real-time multi-channel error calibration architecture. The impact of elevation multi-channel errors on DBF signal synthesis and imaging quality is also evaluated. The parameters of the simultated spaceborne DBF-SAR system are given in Table 1.

Table 1. Simulation system parameters.

Parameters	Symbol	Value
Carrier Frequency	$f_0$	$9.6$ GHz
Number of Elevation Channels	$N_{ch}$	16
Pulse Repetition Frequency	$PRF$	2000 Hz
Sample Rate	$F_r$	$1.2$ Ghz
IF Frequency	$f_{\mathrm{IF}}$	900 MHz
Digital Complex IF Frequency	$f_{\mathrm{IFB}}$	$-300$ MHz
FPGA Prime Clock	$f_{\mathrm{FPGA}}$	100 MHz
Signal Pulse Duration	$T_r$	50 μs
Signal BandWidth	$B_r$	500 Mhz
Chirp Rate	$K_r$	$-{10}^{13}$ Hz/s
Sample Points	$N_r$	66,000
Signal-to-Noise Ratio	$SNR$	20 dB
Internal Calibration Loop Reference Length	L	10 m

The ranges of randomly introduced amplitude, phase, and sample-grid time-delay errors are specified in Table 2.

Table 2. Randomly introduced errors.

Errors	Ranges	Unit
amplitude	−3~3	dB
phase	$-180$~180	degree
time-delay	[−3:0.5:3]	SaGrid

As shown in Equation (8), after dechirp processing, the complex frequency of the tone signal equals the negative product of the chirp rate $K_r$ and the absolute time delay of the internal calibration loop. Setting a negative chirp rate $K_r$ yields a positive complex frequency for this tone signal. Figure 10 presents the signal processing chain of the IF sampled signal (Figure 10a), including the sequential stages of (1) down-conversion via the IFDBF architecture (Figure 10b), (2) dechirping (Figure 10c), and (3) pulse shaping (Figure 10d). Since the internal calibration loop is designed with a 10 m reference length, the dechirped signal frequency $f_{dcp}$ is set to a reference value of 333 kHz.

Figure 10. (a) The IF sampled signal. (b) The down-converted baseband signal. (c) The dechirped signal. (d) The pulse-shaped signal.

The dechirp operation amplifies the sub-sample-grid errors (including half-grid offsets) through the chirp rate $K_r$. Figure 11 demonstrates significant error estimation performance with zero residuals. The simulated internal calibration signal has an SNR of 20 dB. In practice, spaceborne SAR calibration loops typically show better SNR performance. Under the 20 dB SNR condition, the proposed algorithm achieves an amplitude error estimation residual within 0.1 dB and a phase error estimation residual within 1 degree. Higher SNR conditions can further improve error estimation performance. Multiple rounds of random error simulation show that the proposed architecture achieves precise and robust estimation of amplitude, phase, and time-delay errors.

Figure 11. (a) Sub-sample-grid time-delay error estimation results. (b) Amplitude and phase error estimation results.

Proper coherent synthesis of DBF signals can be prevented by amplitude, phase, and time-delay errors. In severe cases, coherent cancellation phenomena may even be caused by these errors. Figure 12 demonstrates the effects of point targets before and after channel error compensation. The simulation results demonstrate that due to incoherent signal superposition caused by channel errors, sideband raising and mainlobe broadening are observed in the point target response.

Figure 12. Error correction effects on point target response and SNR. (a,c) DBF with channel error. (b,d) DBF after channel error calibration.

In addition to point target distortion, SNR degradation is another effect of channel errors on DBF systems. Given perfectly correlated signals, an N-channel DBF architecture yields an N-times SNR improvement. In this simulation case, the single-channel pulse-compressed SNR is approximately 64 dB. The 10-channel configuration provides a 10 dB gain. Figure 12a demonstrates a maintained SNR enhancement of 4.8 dB under amplitude-phase errors alone, excluding time-delay error components. Figure 12c demonstrates that when amplitude, phase, and time-delay errors coexist, the DBF-processed signal exhibits lower SNR than the single-channel output. Coherent cancellation effects further significantly distort the point target response. After error correction, the system can successfully reach its designed performance targets, as shown in Figure 12b,d.

To validate the effectiveness of the proposed error estimation algorithm and real-time processing architecture, experiments were conducted using a 16-channel X-band DBF-SAR system with an elevation of 16-channel capability. The raw data was acquired by an airborne SAR experimental system from the Aerospace Information Research Institute, Chinese Academy of Sciences (AIRCAS). The SAR system parameters are summarized in Table 3.

Table 3. Experimental system parameters.

Parameter	Value
Carrier frequency	9.6 GHz
Velocity	70 m/s
Height	4200 m
Incident angle	${65}^{°}$
Signal bandwidth	500 MHz
Sampling frequency	1200 MHz
Signal pulse duration	10 μs
Number of elevation channels	16

The imaging experiment scenario is located in a rural area, where strong scattering points are present within a weak background to observe the impact of channel errors on DBF imaging. The experimental results are shown in Figure 13. Figure 13a displays the uncorrected channel errors, where the point target exhibits significant defocusing along the range direction due to time delay errors between channels. Figure 13b demonstrates the corrected channel errors, showing well-focused point targets.

Figure 13. Airborne DBF-SAR images (provided by the AIRCAS). (a) Before DBF multi-channel error calibration. (b) After DBF multi-channel error calibration.

5. Discussion

The proposed method discusses the IFDBF implementation case while remaining equally applicable to baseband Digital Beamforming (BBDBF) architecture [30]. Compared with BBDBF architecture, the IFDBF architecture significantly reduces the number of required filters, thereby decreasing implementation complexity [28,31]. The LFM was merely employed as a calibration tool, and the error-compensated system operates independently of the transmitted signal type. In fact, the proposed real-time multi-channel error estimation architecture is universally applicable to most multi-channel systems, including azimuth multi-channel, elevation multi-channel, and 2D multi-channel architectures. The IFDBF architecture inherently integrates amplitude, phase, and digital delay compensators to support its real-time complex weighting and time-delay operations. Only the error estimation module needs to be added, while the error compensation module can be shared with the DBF processing chain to conserve hardware resources. For other multi-channel systems such as the TerraSAR [32] azimuth multi-channel architecture, additional amplitude, phase, and time-delay error estimation and compensation modules must be incorporated.

The proposed method is inspired by the cal-tone technique [21,22,23], which estimates amplitude and phase errors through single-tone frequency analysis. Focusing on single-frequency spectral analysis significantly reduces the noise impact on error estimation. The proposed method generates a cal-tone-like single-tone signal via dechirp processing, but eliminates the need for additional RF components by implementing all necessary digital modules in an FPGA. Moreover, the method utilizes dechirp processing to estimate time-delay errors from single-tone frequency bias analysis, extending the functionality beyond conventional cal-tone techniques.

6. Conclusions

Digital beamforming serves as the cornerstone technology for next-generation spaceborne SAR systems to achieve HRWS imaging. The SNR improvement of DBF critically depends on inter-channel consistency. However, non-ideal channel matching introduces amplitude, phase, and time-delay errors due to thermal deformation and random synchronization errors among multi-channel ADCs. Conventional echo-based error estimation methods demonstrate satisfactory performance. However, the stringent real-time requirements imposed by DBF-SAR are not met. A novel real-time error calibration architecture, characterized by low cost and high estimation accuracy, is proposed in this paper. Although optimized for IFDBF real-time processing, the proposed multi-channel error calibration architecture can be widely applied to other spaceborne multi-channel systems requiring joint amplitude/phase/time-delay compensation. Simulation and experimental results validate the method’s effectiveness. In the future, we will continue to focus on implementing the SAR theory in practice.