High-Precision Digital Clock Steering Method Based on Discrete Σ-Δ Modulation for GNSS

Abstract

A high-precision time reference is fundamental to the positioning, navigation, and timing (PNT) of global navigation satellite systems (GNSS). The precision of clock steering determines the accuracy of practical applications that rely on the time–frequency reference. With the invention of direct digital synthesizer (DDS) technology, digital clock steering (DCS) has gradually become a mainstream technology. However, the key factor limiting DCS accuracy is the system quantization noise, which leads to a low frequency and phase adjustment accuracy. Here we propose a DCS method based on $\Sigma$-$\Delta$ modulation to address the issue of low resolution of DAC through shaping the quantization noise. A simulated GNSS time–frequency reference system experimental platform is constructed to validate the effectiveness of the proposed method. The experimental results demonstrate that this method achieves a phase adjustment accuracy of 0.48 ps and a frequency adjustment accuracy better than 0.48 pHz, which is two orders of magnitude higher than that of existing GNSS time–frequency reference systems. Thus, the proposed method offers a significant improvement in time–frequency reference systems, leading to better performance, reliability, and accuracy in a wide range of practical applications.

1. Introduction

High-precision positioning, navigation, and timing (PNT) services are provided by global navigation satellite systems (GNSS), which rely on a high-precision time–frequency reference [1,2]. The time–frequency reference sources of major navigation satellites commonly comprise multiple long-term stable onboard atomic clocks and short-term stable high-quality crystal oscillators. The generation of the atomic timescale (ATS) and clock steering are the two main components of a time–frequency reference system. The global positioning system (GPS) time–frequency reference is produced by a timekeeping system (TKS). A TKS operates by comparing the phase difference between the reference atomic clock and the output of a highly stable crystal oscillator, it then adjusts the frequency by using a loop filtering algorithm. Next, the signal is converted to a voltage-controlled voltage by a digital-to-analog converter (DAC) to ensure that the output time–frequency signal is locked to the reference frequency source. The phase measurement accuracy of the TKS is 0.8 ps, whereas the frequency adjustment accuracy is 1 µHz [3]. The Galileo satellite, which is based on GPS TKS technology, employs a clock monitoring and control unit (CMCU) with a phase measurement accuracy of 24 ps and a frequency adjustment accuracy of 0.056 µHz as its onboard time–frequency reference equipment [4]. The time–frequency reference equipment for the Beidou-3 satellite is designed considering the advantages of a TKS and CMCU. Thus, the satellite achieves a phase measurement accuracy of 0.4 ps, frequency adjustment accuracy better than 30 nHz, and phase adjustment accuracy better than 0.1 ns [5]. Currently, the phase measurement accuracy of mainstream GNSS time–frequency reference equipment has reached the subpicosecond level. However, the phase adjustment accuracy of clock steering is only 0.1 ns, constituting a difference of two orders of magnitude.

To further enhance the PNT service capabilities of navigation satellites, GPS-Block-IIIA, Galileo-CMCU+, and other mainstream GNSS have implemented several improvements to their time–frequency reference systems. For instance, the performance and robustness of clock exception handling can be improved by improving the exception handling algorithm [6], and the phase-hopping problem of traditional primary and standby clocks can be solved by using the working mode of composite atomic clocks [7]. To meet the requirements of the new-generation Beidou navigation satellite time–frequency reference system, Yi et al. [8] conducted research on the ATS production algorithm and clock steering technology and provided solutions to improve frequency stability and enable reliable applications of single-star autonomous timekeeping. However, current improvements in the time–frequency reference system primarily focus on enhancing reliability and robustness; there is a lack of research on improving steering accuracy. Nevertheless, improving the steering accuracy of the time–frequency reference is crucial not only for providing higher precision PNT services but also for solving fundamental scientific research problems, such as local Lorentz invariance [9] and gravitational redshift verification [10]. Therefore, this study focuses on a high-precision digital clock steering (DCS) method.

The role of clock steering is to convert the local paper time into physical time–frequency reference signals to achieve fine adjustments in frequency and phase. Traditional clock steering is performed using analog circuits, which suffer from long adjustment time, large size, and poor programmability. With the rapid development of digital integrated circuits, direct digital synthesizer (DDS) technology has emerged [11]. Although DDS can achieve frequency and phase adjustment, its output time–frequency signal often exhibits discontinuities that fail to meet the requirements of a high-precision time–frequency reference system. Currently, DCS technology typically comprises a combination of a digital phase-locked loop (DPLL) and DDS. Most studies on DCS technology have focused on reducing the noise of the DPLL and DDS. For instance, Chimakurthy et al. [12] proposed a nonlinear addressing scheme that adaptively varies the number of interpolation points to reduce the size of the read-only memory (ROM) and optimize the quantization noise of the DDS. Stevanovic et al. [13] derived an enhanced model for a GPS PLL using the reference deviation of the tracking error as the phase-jitter index to optimize the effect of PLL noise. In addition, Zhao et al. [14] introduced a sinusoidal encoder phase discrimination method based on the Kalman filter to enhance the noise suppression capability of digital phase-locked loop phase discrimination and eliminate phase errors related to acceleration. Cardenas Olaya et al. [15] provided a phase noise function based on the power and frequency of an external reference voltage source to aid in the prediction of the stability of a PLL with respect to the frequency and power of the external reference. Furthermore, Murphy et al. [16] used multiple phase discriminators (PDs) and a linear DAC for overclocking counting to eliminate quantization noise in the PLL. Dartizio et al. [17] proposed a bang-bang fractional-N PLL with quantization noise shaping to overcome the noise limitations of the PD. The analysis of the DPLL primarily focuses on reducing the noise from the PD and loop filter (LPF). However, the low resolution of the DAC results in high quantization noise, which is the primary reason for the lack of high accuracy in frequency and phase adjustments by DCS.

Using a DPLL alone in DCS is impractical, as it would require significant time to manually adjust the phase by changing the frequency. Similarly, traditional phase shifters cannot be used independently [18], owing to issues such as sudden phase hopping and discontinuous phase tracking. To address these challenges, this study proposes a DCS method based on discrete $\Sigma$-$\Delta$ modulation. This study aims to resolve the quantization noise resulting from the low resolution of the DAC while enabling high-precision and continuous frequency and phase adjustments. We offer important insights into the enhancement of the steering accuracy of time–frequency reference signals, which is of significant research value for high-performance time–frequency reference systems in the next generation of GNSS.

Section 2 introduces the principle of the proposed method. Section 3 focuses on the DCS simulation results based on discrete $\Sigma$-$\Delta$ modulation. Section 4 designs the experimental procedure and presents the results. Finally, Section 5 presents the conclusions of the study and future work.

2. Methodology

In this section, we present the transfer function of the DCS noise model and analyze the noise in each component of the model. The results of the analysis revealed that the most significant factor affecting the phase adjustment accuracy was the quantization noise resulting from the low resolution of the DAC. To address this issue, we proposed a DCS method based on discrete $\Sigma$-$\Delta$ modulation. Furthermore, a method based on augmented Lagrangian optimization was designed to ensure the best performance of the $\Sigma$-$\Delta$ modulator. Finally, we designed a loop filter to ensure clock steering speed while maintaining steer accuracy.

2.1. Noise Analysis

Noise analysis is a crucial step for understanding the precision of DCS. The noise model of DCS can be treated as a linear system, with each component introducing independent and uncorrelated random noise. The total phase noise was calculated, and the power spectral density of the output phase noise was analyzed. Figure 1 illustrates the noise transfer model of the DCS model, comprising the DDS, PD, LPF, DAC, and voltage-controlled oscillator (VCO), each of which contributes to the introduced noise.

The noise transfer function of the output signal is expressed as follows:

$$H_{DPLL}\left(z\right)={\displaystyle \frac{{\theta }_o\left(z\right)}{{\theta }_{ref}\left(z\right)}}={\displaystyle \frac{K_d{K}_0{H}_{LPF}\left(z\right)H_{VCO}\left(z\right)/N}{1+K_d{K}_0{H}_{LPF}\left(z\right)H_{VCO}\left(z\right)/N}},$$

(1)

where z is a complex variable, $K_d$ is the PD gain, $K_0$ is the LPF gain, N is the allocation coefficient of the frequency divider, $H_{LPF}\left(z\right)$ is the transfer function of the LPF, and $H_{VCO}\left(z\right)$ is the transfer function of the VCO.

The phase noise power spectrum of the output signal can be generated by employing the superposition theorem. The obtained phase noise power spectral density of the output signal is expressed as follows:

$$\begin{array}{cc}\hfill & S_o\left(f\right)=S_{ref}\left(\begin{array}{c}f\end{array}\right)|H_{DPLL}\left(f\right){|}^2+S_{DDS}\left(\begin{array}{c}f\end{array}\right)|H_{DDS}\left(\begin{array}{c}f\end{array}\right){|}^2\hfill \\ \hfill & +S_{PD}\left(\begin{array}{c}f\end{array}\right)|H_{PD}\left(\begin{array}{c}f\end{array}\right){|}^2+S_{DAC}\left(f\right)|H_{DAC}\left(f\right){|}^2\hfill \\ \hfill & +S_{LPF}\left(f\right)|H_{LPF}\left(f\right){|}^2+S_{VCO}\left(f\right)|H_e\left(f\right){|}^2\hfill \end{array},$$

(2)

where f is the frequency.

Based on noise theory analysis, the main sources of noise are the DDS, DAC, frequency source, and PD. The level of noise introduced by a DDS depends on its frequency control word (FCW) and phase control word (PCW). The quantization noise can be reduced by increasing the number of bits in the FCW and PCW. Similarly, it can be minimized in a purely digital PD by increasing the number of bits. Thus, the quantization noise can be characterized as independent and uniformly distributed white noise, with the quantizer power spectral density given by

$$S\left(f\right)={\displaystyle \frac{2{\left(2T_{ref}\right)}^2}{12f_s}},$$

(3)

where $f_s$ is the sampling rate and $(-T_{ref},T_{ref})$ is the quantization noise range.

Frequency source noise is inevitable and is often represented as a linear combination of five independent noises [19]. To mitigate this noise, selecting a clock with a higher accuracy can be beneficial. The power spectral density of the frequency source noise is given by

$$S_{VCO}\left(f\right)={\displaystyle \frac{1}{{\left(2\pi \right)}^2}}\sum _{a=-2}^2{h}_{\alpha }{f}^{\alpha },$$

(4)

where f is the Fourier frequency, $h_{\alpha }$ is the amplitude, and $\alpha$ is the power-law spectral index.

The quantization noise introduced by the DAC can be mitigated by increasing its resolution. However, it is currently challenging to fulfill the requirements of a time–frequency reference system. Moreover, a higher-resolution DAC is often associated with a higher cost. Consequently, upgrading the hardware to address the issue of a low-resolution DAC and the resulting quantization noise may not be the most effective solution.

2.2. Discrete $\Sigma$-$\Delta$ Modulator Design

We designed a discrete $\Sigma$-$\Delta$ modulator to shape the quantization noise caused by insufficient resolution of the DAC. Figure 2 depicts the DCS model based on discrete $\Sigma$-$\Delta$ modulation. In this model, the reference and steering clocks function as sampling clocks for the two DDSs. Frequency and phase adjustments of the DDSs were achieved by varying the FCW and PCW. The phase discrimination of the output time–frequency signals from the two DDSs were carried out by the DPLL. The resulting phase difference is converted into digital frequency adjustment signals via loop filtering; it is then converted into an analog voltage-controlled voltage by the discrete $\Sigma$-$\Delta$ modulator. Ultimately, this voltage regulates the steering clock, thereby enabling the accurate output of the time–frequency signal after frequency and phase adjustments. The system transfer function of the DCS based on discrete $\Sigma$-$\Delta$ modulation can be represented as follows:

$$H\left(z\right)={\displaystyle \frac{{\theta }_o\left(z\right)}{{\theta }_{ref}\left(z\right)}}={\displaystyle \frac{K_d{K}_0{H}_{LPF}\left(z\right)H_{VCO}\left(z\right)H_{\Sigma -\Delta }\left(z\right)/N}{1+K_d{K}_0{H}_{LPF}\left(z\right)H_{VCO}\left(z\right)H_{\Sigma -\Delta }\left(z\right)/N}},$$

(5)

where $H\left(z\right)$ is the transfer function of the DCS system and $H_{\Sigma -\Delta }\left(z\right)$ is the transfer function of the discrete $\Sigma$-$\Delta$ modulator.

In the DCS model, the phase adjustment is accomplished by integrating the frequency adjustment. After the phase difference signal passes through a high-order loop filter, the output includes not only the filtered result of the phase difference but also high-order information such as the speed and acceleration of phase difference changes [20]. In a discrete $\Sigma$-$\Delta$ modulator, the input $X\left(n\right)$ is a frequency-adjusted signal, which is the integral of the phase signal. Therefore, $X\left(n\right)$ can be represented as:

$$X\left(n\right)={\Delta }_{f}u\left(n\right)+{\Delta }_{\tilde{f}}nu\left(n\right),$$

(6)

where ${\Delta }_f$ is frequency step amplitude, ${\Delta }_{\tilde{f}}$ is frequency increment magnitude, and $u\left(n\right)$ is unit step sequence. Its z-transform is:

$$X\left(z\right)={\displaystyle \frac{{\Delta }_f}{1-z^{-1}}}+{\displaystyle \frac{{\Delta }_{\tilde{f}}{z}^{-1}}{{(1-z^{-1})}^2}},$$

(7)

According to the final value theorem, we need to design a second-order $\Sigma$-$\Delta$ modulator to ensure that the steady-state error of the system is 0. Figure 3 shows the transfer function model of a second-order discrete $\Sigma$-$\Delta$ modulator.

Based on the system block diagram of the second-order discrete $\Sigma$-$\Delta$ modulator, the noise transfer function can be defined as follows:

$$Y\left(z\right)={\displaystyle \frac{k_1{k}_{2}X\left(z\right)+{(1-z^{-1})}^{2}E\left(z\right)}{{(1-z^{-1})}^2-k_2(g_2+g_2{z}^{-1}-k_1{g}_1)z^{-1}}},$$

(8)

where $Y\left(z\right)$ is the noise transfer function of the discrete $\Sigma$-$\Delta$ modulator, $k_1$ and $k_2$ are the gain of the integrator, $g_1$ and $g_2$ are the loop gain, and $E\left(z\right)$ is the noise transfer function introduced by the quantizer, which can be seen as a type of uniformly distributed noise. The noise transfer function of $E\left(z\right)$ can be defined as follows:

$$E\left(z\right)={\displaystyle \frac{{\Delta }_{res}{z}^{-1}}{{(1-z^{-1})}^2}},$$

(9)

where ${\Delta }_{res}$ is the resolution of the DAC.

To achieve system convergence, with all zeros and poles of the system transfer function inside the unit circle, we provide constrains as follows:

$$\left\{\begin{array}{c}{u}_1(k_1,k_2,g_1,g_2)<0\\ u_2(k_1,k_2,g_1,g_2)<0\\ u_3(k_1,k_2,g_1,g_2)<0\\ u_4(k_1,k_2,g_1,g_2)<0\end{array}\right.,$$

(10)

where $u_1$, $u_2$, $u_3$, and $u_4$ are functions for finding zeros and poles.

The frequency adjustment resolution is primarily influenced by the DAC reference voltage and DAC resolution. Equation (11) represents the calculation formula for the frequency-adjustment resolution.

$$d{f}_{res}={\displaystyle \frac{V_{ref}}{2^N}},$$

(11)

where $d{f}_{res}$ is the frequency-adjustment resolution, $V_{ref}$ is the DAC reference voltage, and N is the DAC bit.

The minimum resolution of the voltage-controlled voltage output of the DAC is directly proportional to the frequency-adjustment resolution, which differs from the frequency adjustment accuracy. The frequency adjustment resolution refers to the minimum resolution of the actual tuning frequency of the VCO output, which is determined by the hardware parameters.

To enhance the accuracy of frequency and phase adjustments, it is important to analyze the relationship between the DCS frequency and phase and the loop update period, while also designing the gains for the $\Sigma$-$\Delta$ modulator. Additionally, increasing the value of g provides a loop with sufficient gain, improves the tracking capabilities, and reduces the steady-state error in the DCS model. Moreover, decreasing the value of k helps to control the range of $V\left(z\right)$.

The objective function can be represented as follows:

$$\begin{array}{cc}\hfill & G\left(z\right)=Y\left(z\right)-X\left(z\right)\hfill \\ \hfill & ={\displaystyle \frac{(k_1{k}_2-{(1-z^{-1})}^2+k_2(g_2+g_2{z}^{-1}-k_1{g}_1)z^{-1})X\left(z\right)+{(1-z^{-1})}^{2}E\left(z\right)}{{(1-z^{-1})}^2-k_2(g_2+g_2{z}^{-1}-k_1{g}_1)z^{-1}}}\hfill \end{array},$$

(12)

where $G\left(z\right)$ is the frequency adjustment deviation between the actual value and the ideal value, with minimax values reducing quantization errors.

Combining Equations (10) and (12), the $\Sigma$-$\Delta$ modulator design problem can be posed as follows:

$$\begin{array}{c}{\displaystyle \underset{z}{\min }}\left\{\max \left[G\left(z\right)\right]\right\}\hfill \\ \mathrm{s}.\mathrm{t}.\left\{\begin{array}{c}{u}_1(k_1,k_2,g_1,g_2)<0\hfill \\ u_2(k_1,k_2,g_1,g_2)<0\hfill \\ u_3(k_1,k_2,g_1,g_2)<0\hfill \\ u_4(k_1,k_2,g_1,g_2)<0\hfill \end{array}\right.\hfill \end{array},$$

(13)

Equation (13) represents a minimax optimization problem with constraints. We solve it using the augmented Lagrangian method [21]. The augmented Lagrangian function is as follows:

$$\begin{array}{cc}\hfill & \mathcal{L}(z,k_1,k_2,g_1,g_2,{\lambda }_1,{\lambda }_2,{\lambda }_3,{\lambda }_4)={\displaystyle \underset{z}{min}}\left\{\max \left[G\left(z\right)\right]\right\}+{\displaystyle \sum _{s\in R}}{\lambda }_{1,s}^{\left(i\right)}(u_1-{{\displaystyle \tilde{u}}}_1)+{\displaystyle \frac{\rho }{2}}{\displaystyle \sum _{s\in R}}\Vert u_1-{\tilde{u}}_1{\Vert }^2\hfill \\ \hfill & +{\displaystyle \sum _{i\in R}}{\lambda }_{2,s}^{\left(i\right)}(u_2-{\tilde{u}}_2)+{\displaystyle \frac{\rho }{2}}{\displaystyle \sum _{i\in R}}\Vert u_2-{\tilde{u}}_2{\Vert }^2\hfill \\ \hfill & +{\displaystyle \sum _{i\in R}}{\lambda }_{3,s}^{\left(i\right)}(u_3-{\tilde{u}}_3)+{\displaystyle \frac{\rho }{2}}{\displaystyle \sum _{i\in R}}\Vert u_3-{\tilde{u}}_3{\Vert }^2\hfill \\ \hfill & +{\displaystyle \sum _{i\in R}}{\lambda }_{4,s}^{\left(i\right)}(u_4-{\tilde{u}}_4)+{\displaystyle \frac{\rho }{2}}{{\displaystyle \sum _{i\in R}}\Vert u_4-{\tilde{u}}_4\Vert }^2\hfill \end{array},$$

(14)

where $\rho$ is the penalty parameter, ${\lambda }_1^{\left(i\right)}$, ${\lambda }_2^{\left(i\right)}$, ${\lambda }_3^{\left(i\right)}$, and ${\lambda }_4^{\left(i\right)}$ are Lagrangian multipliers, and ${\tilde{u}}_1$, ${\tilde{u}}_2$, ${\tilde{u}}_3$, and ${\tilde{u}}_4$ are slack variables.

The algorithm is implemented as follows:

(1)

Update $k_1^i$, $k_2^i$, $g_1^i$, and $g_2^i$, by solving Equation (14), we find the optimal value of $k_1^{i+1}$, $k_2^{i+1}$, $g_1^{i+1}$, and $g_2^{i+1}$.

Variables ${\tilde{u}}_1$, ${\tilde{u}}_2$, ${\tilde{u}}_3$, and ${\tilde{u}}_4$ appear only in the two terms of Equation (14), which is actually a convex quadratic function of each relaxation variable. We take the partial derivative of ${\tilde{u}}_i$. The unconstrained minimum of Equation (14) with respect to ${\tilde{u}}_s$ occurs when the partial derivative equals 0. If this is an unconstrained minimum, which has a lower bound less than 0, then it is convex in Equation (14). The optimal solution for ${\tilde{u}}_i$ in Equation (13) is 0. Therefore, the solution to Equation (13) is:

$${\lambda }_s^{\left(i\right)}(u_s-{\tilde{u}}_s)+{\displaystyle \frac{\rho }{2}}\sum _{i\in R}\Vert u_s-{\tilde{u}}_s{\Vert }^2=\left\{\begin{array}{cc}\hfill & {\lambda }_s^{\left(i\right)}{u}_s+{\displaystyle \frac{\rho }{2}}{u_s}^2,u_s-{\displaystyle \frac{{\lambda }_s^{\left(i\right)}}{\rho }}<0\hfill \\ \hfill & {\displaystyle \frac{{\left({\lambda }_s^{\left(i\right)}\right)}^2}{\rho }},\mathrm{otherwise}\hfill \end{array}\right.,$$

(15)

(2)

Update ${\lambda }_1^{\left(i\right)}$, ${\lambda }_2^{\left(i\right)}$, ${\lambda }_3^{\left(i\right)}$, and ${\lambda }_4^{\left(i\right)}$ by:

$${\lambda }_s^{(i+1)}={\lambda }_s^{\left(i\right)}+\rho (u_j^{(i+1)}-{\tilde{u}}_j^{(i+1)}),$$

(16)

Then, continuously repeat steps 1 and 2. Upon meeting the termination conditions, the optimal $\Sigma$-$\Delta$ modulation gain is obtained. Figure 4 shows the TIE trace of the optimal MTIE and without the use of $\Sigma$-$\Delta$ modulation.

To validate the correctness of the optimization algorithm results, we conducted Monte Carlo simulations using the values of k1, k2, g1, and g2. During the simulations, we used a performance metric: the maximum time interval error (MTIE). The goal was to determine the optimal parameter values corresponding to this metric. Figure 5 shows the Monte Carlo simulations for finding the optimal MTIE result. The optimal MTIE result of the Monte Carlo simulations is consistent with the derived results of the augmented Lagrangian method. Simulation conditions are as follows.

In Figure 6, we compare the TIE histograms with different $\Sigma$-$\Delta$ modulator gain values and without the use of $\Sigma$-$\Delta$ modulation. A TIE histogram provides a direct analysis of the various characteristics of the TIE. When the number of measurements, N, in the TIE was sufficiently large (N > 100), the TIE histogram effectively reflected its statistical characteristics. By comparing the TIE histograms, we can more directly observe and analyze the distribution and statistical properties of the TIE, which thereby enables us to evaluate the performance improvements achieved by the proposed method.

In this study, the TIE was transformed into a frequency-tracking error. Notably, the frequency-tracking error differs from the frequency-adjustment resolution. The frequency-adjustment resolution refers to the minimum resolution of the actual tuning frequency of the output from the VCO. In contrast, the frequency-tracking error is the result of the phase-value determination. According to Equation (17), under the optimal MTIE conditions, the frequency-tracking error was calculated to be 0.24 pHz.

$$d{f}_{tra}=f_0-{\displaystyle \frac{f_0·\Delta t-\sigma }{\Delta t}},$$

(17)

where $\Delta t$ is the time interval used to calculate the frequency. The time–frequency signal is often used for counting to generate a one pulse per second (1PPS) signal. Here, we take $\Delta t$ as 1 s.

2.3. Optimal LPF Design

The performance of a $\Sigma$-$\Delta$ modulator is directly affected by the phase difference filtering results of the LPF, as it serves as the input to the $\Sigma$-$\Delta$ modulator. At the same time, the LPF design is crucial for determining the dynamic and steady-state characteristics of the PLL. We empirically designed the loop bandwidth and loop update period to achieve a PLL that meets the requirements of a steady-state error, locking time, overshoot, and other factors. Equation (18) provides a formula for the loop bandwidth of a third-order PLL:

$$B_L={\displaystyle \frac{a_3{b}_3^2+a_3^2-b_3}{4\left(a_3{b}_3-1\right)}}{w}_n,$$

(18)

where $a_3$ and $b_3$ are the classical parameters of the third-order LPF and $w_n$ is the characteristic frequency of the phase-locked loop.

The equivalent noise bandwidth of a DPLL can be approximated as a function of the closed-loop system frequency response $H_{\theta }\left(e^{jw}\right)$.

$$B_{n-\mathrm{DPLL}}={\displaystyle \frac{1}{2\pi T_L}}{\int }_{-\pi }^{\pi }{\left|H_n\left(e^{jw}\right)\right|}^{2}dw\approx {\displaystyle \frac{1}{2\pi T_L}}{\int }_{-\pi }^{\pi }{\left|H_{\theta }\left(e^{jw}\right)\right|}^{2}dw,$$

(19)

Rewrite Equation (19) as follows:

$$B_{n-\mathrm{DPLL}}={\displaystyle \frac{1}{2T_L}}{I}_N,$$

(20)

where the integral of the circumference $I_N$, its integral path, is a unit circle.

$$I_N={\displaystyle \frac{1}{2\pi i}}\oint H_{\theta }\left(z\right)H_{\theta }\left(z^{-1}\right)z^{-1}dz,$$

(21)

Derive the relationship between the loop bandwidth of a third-order DPLL and the loop bandwidth of an analog PLL by combining Equations (18), (20), and (21).

$$B_{3-DPLL}={\displaystyle \frac{a_3{b}_3{\left(c_3{B}_L{T}_L\right)}^3-2(b_3{a}_3^2+a_3){\left(c_3{B}_L{T}_L\right)}^2+4(a_3{b}_3^2+a_3^2-b_3)\left(c_3{B}_L{T}_L\right)}{8(a_3{b}_3-1)-4(a_3{b}_3^2+a_3^2-b_3)\left(c_3{B}_L{T}_L\right)+2(b_3{a}_3^2+a_3){\left(c_3{B}_L{T}_L\right)}^2-a{b}_3{\left(c_3{B}_L{T}_L\right)}^3}},$$

(22)

where $a_3$, $b_3$, and $c_3$ are the classical parameters of the third-order LPF; $B_L$ is the analog third-order PLL loop bandwidth; and $T_L$ is the loop update period.

The simulation results of the optimal loop bandwidth in Figure 7 show that, when $B_L$ is 20, the locking time of the PLL is 1 s, when $B_L$ is 30, the locking time of the PLL is 1 s, and, when $B_L$ is 10, the lock time of the PLL is 1.5 s. The steady-state errors of the DPLL were equal for different loop bandwidths. Reducing the loop bandwidth of the DPLL increased the locking time; however, the phase-tracking accuracy did not improve after the PLL stabilized.

Therefore, the design concept behind the DPLL loop bandwidth and loop update period aims to maximize the loop tracking accuracy by appropriately increasing the loop bandwidth and accelerating the loop update period. This approach achieves a high level of precision and fast loop locking.

3. Simulation

In this section, we use simulation software to conduct DCS simulation verification based on the system block diagram and the designed $\Sigma$-$\Delta$ modulator and the optimal loop bandwidth. Our aim is to achieve a high-precision and rapid response. Algorithm 1 shows the pseudocode of system simulation.

Table 1. Simulation parameter setting.

Parameter	Value
Sampling rate	10 MHz
Bit width of DDS accumulator	48 bit
DDS output frequency	230 KHz
Resolution of DAC	3.81 × ${10}^{-6}$ V
Clock frequency tunable range	−5–5 Hz
PLL update period	1 ms
k1, k2, g1, g2	0.9, 0.8, 0.9, 0.4
${\mathit{B}}_L$	20

lists the parameters used in the simulations. These simulation parameters were selected based on the actual hardware parameters to ensure the accuracy and reliability of the verification results.

Algorithm 1: System simulation

Input: Phase adjustment, Frequency adjustment Output: TIE   1: Initialization simulation parameters   2: Configure DDS   3: for each PLL update period do   4:    Costas loop PD calculating TIE   5:    Digital loop filtering   6:    if Digital frequency adjustment < Resolution of DAC then   7:      Discrete $\Sigma$-$\Delta$ modulation   8:    end if   9: end for 10: Adjust the frequency and phase of the frequency source 11: return Adjusted time–frequency signal

The simulation results indicate that the loop-lock time achieved is 1 s. When the method proposed in this study was not used, the phase-tracking error was measured to be 0.9 ps, and the frequency-tracking error was 0.9 pHz. However, by designing the optimal loop bandwidth and $\Sigma$-$\Delta$ modulator gain as suggested, significant improvements are observed. The phase tracking error is reduced to 0.24 ps, and the frequency tracking error is reduced to 0.24 pHz. These findings highlight the effectiveness of the proposed method in achieving superior performance in terms of reducing the tracking errors. It is important to note that k1, k2, g1, and g2 are not constant values. They need to be determined based on different systems using the methods provided in this paper (Figure 8).

In practice, phase adjustment in DCS can be achieved by compensating for the phase-difference signal from the PD. The accuracy of this adjustment process is determined by the number of bits in the phase-difference signal and the tracking error. In a DPLL, the number of bits in the phase-difference signal is typically high, and inherent errors can be considered negligible. Therefore, the phase and frequency adjustment accuracies were primarily limited by the tracking errors with higher weights. With a phase tracking error of 0.24 ps, the phase adjustment accuracy reached the subpicosecond level, which is comparable to the precision of phase measurements in GNSS time–frequency reference systems. Similarly, the frequency adjustment accuracy was equal to a frequency-tracking error of 0.24 pHz. Through simulation results, the correctness of the theoretical derivations and the effectiveness of the DCS method based on discrete $\Sigma$-$\Delta$ modulation have been effectively demonstrated.

4. Experiments

To assess the effectiveness of the DCS method based on discrete $\Sigma$-$\Delta$ modulation in a practical setting, we established a simulated GNSS time–frequency reference system experimental platform following the system block diagram and theoretical analysis. This section presents the design of the experimental process, including the details of the hardware parameters and instrument settings. The errors were analyzed and treated; this was followed by the execution of the experiment. The resulting experimental data are presented, analyzed, and discussed to enable the evaluation of the obtained results.

Two experiments were conducted to evaluate the effectiveness of the proposed method from different perspectives. The experimental flow diagram depicted in Figure 9 shows the design of the two physical experiments: an instrument measurement experiment and an ILA sampling analysis experiment. The integrated logic analyzer (ILA) is an IP core provided by the Vivado software package. It enables the in-system debugging of the FPGA device and enables the real-time capture of waveform data from digital signals within the FPGA using one or more probes. The ILA serves as a valuable tool for performing detailed analysis of the captured data.

Figure 10 illustrates the design of an integrated time–frequency reference unit based on an FPGA. It consists of two oven-controlled crystal oscillators (OCXOs), an FPGA, a DAC, and various input–output interfaces. OCXO1 simulates ATS production, whereas OCXO2 serves as a highly stable crystal oscillator for precise clock steering. Figure 11 shows the experimental platform of the constructed simulated GNSS time–frequency reference system.

4.1. Instrumental Measurement Experiment

Compared with the simulation experiment, the experimental platform of the time–frequency reference system introduces additional sources of errors that exhibit higher levels. These factors are challenging to precisely model and analyze in a simulated environment. First, we thoroughly examined the experimental environment and identified the various sources of noise.

Table 2. Sources of noise and characteristics.

Sources of Noise	Characteristics
Frequency source	White frequency noise, random walk frequency noise, random run frequency noise
DC power supply	Ripple noise
FPGA timing jitter	White Gaussian noise
Frequency–time counter	Internal frequency source introduces noise

lists the sources of noise and characteristics. These include internal noise originating from the frequency source, noise associated with the DC power supply, noise introduced through the FPGA timing jitter, and the internal noise of the frequency–time counter. Notably, the short-term stability of the OCXO employed in the experiment was only 1 ×${10}^{-12}$. Additionally, the OCXO is susceptible to variations in the temperature and power supply voltage.

Table 3. Key electrical performance technical indicators of OCXO.

Parameter	Specification
Nominal Frequency	10 MHz
Frequency Stability
Operating temperature	<±1 ppb
Supply voltage variation	<±0.1 ppb at VCC ±5%
Load variation	<±0.1 ppb for 5% change from 15 pF
Short-term stability	<1 × ${10}^{-12}$
Frequency Adjustment
Frequency adjustment range	±0.5 ppm
Control voltage range	0 5 V
Voltage control linearity	<10%

lists the key electrical performance indicators of the OCXO. The power supply noise can affect the OCXO power supply voltage, resulting in frequency changes. Furthermore, it can affect the reference voltage of the DAC, thereby reducing the accuracy of the voltage control signal.

Table 4. Main device and instrument parameters.

Instrument/Type	Main Parameter
Frequency–time counter/KEYSIGHT 53230A	20 ps time interval resolution
High-speed oscilloscope/KEYSIGHT DSO93004L	80 GSa/s sampling rate
DC power supply/GAATTEN APS3003S-3D	5 V/3 A
FPGA/xc7z100iffg900-2L	78,480 logic cells
DAC/AD5781	18 bit
OCXO/JKOC36LN SERIES	10 MHz
Rubidium atomic clock/Stanford	10 MHz

lists the parameters of the devices and instruments used in the experiments.

We carried out comprehensive testing of each instrument device used in the experimental setup. First, we assessed the capabilities of the DAC by outputting the maximum and minimum voltages. We then monitored the corresponding adjustable range of the OCXO frequency. The test results indicate that the OCXO frequency can be adjusted within a maximum range of [−10 Hz, 10 Hz], which consequently affects the resolution of the frequency adjustments. Subsequently, a high-speed oscilloscope was used to measure the edge steepness of the FPGA. This measurement is critical because it directly affects the accuracy of the time interval measurement between the 1PPS signals obtained by counting the output signal of the OCXO.

The accuracy of the frequency–time counter is of crucial importance because it determines the precision with which we can detect time intervals. We used two same-source 1PPS signals generated by a rubidium clock as inputs into the frequency–time counter. Theoretically, the time interval between these identical 1PPS signals should be 0. We utilized the rubidium clock count to generate two same-source 1PPS signals. These signals were then input into the frequency–time counter for measurement while continuously sampling for a duration of 20,000 s at a rate of 1 Hz. Figure 12 show that the peak-to-peak width of the TIE for the two same-source 1PPS signals is 120 ps, which falls short of meeting the requirements of our detection simulation results. To address this, we calculated the mean of the TIE every 2000 s. The mean peak-to-peak width of TIE is 5 ps, which originates from measuring errors of the instrument.

Similar to a rubidium atomic clock, we utilized the reference OCXO count from the integrated time–frequency reference generation unit to generate two same-source 1PPS signals. The peak-to-peak width of the TIE for the two same-source 1PPS signals is 120 ps, and the mean peak-to-peak width of the TIE is 5 ps.

Based on the results of the error analysis, the verification scheme for the proposed method was designed as follows. In this experiment, we introduced a reference OCXO and steering OCXO. After precise adjustments to their phase and frequency, these two OCXOs independently output 1PPS signals that were then transported into a locked state. The maximum mean TIE was detected by comparing the edges of these signals.

To evaluate the clock steering performance of the proposed method, we employed a 53230A frequency–time counter to measure the time interval between the edges of two non-same-source 1PPS signals. The TIE was then calculated as the mean over 2000 s. By comparing this TIE with the corresponding value obtained from the same-source 1PPS signals, we can verify whether the TIE reaches a similar level. The experimental results shown in Figure 13 and summarized in

Table 5. Comparison of the measurement of the TIE track in the same-source, $\Sigma$-$\Delta$ modulation, and no $\Sigma$-$\Delta$ modulation cases.

Time(s)	2000	4000	6000	8000	10,000	12,000	14,000	16,000	18,000	20,000
Same-source(ps)	−2.88	−1.32	−1.15	0.19	−2.1	0.86	−0.06	−0.13	0.59	−0.74
$\Sigma$-$\Delta$ Modulation(ps)	−4.49	−0.14	1.80	0.56	−1.28	−0.33	3.93	−2.35	0.05	1.45
No $\Sigma$-$\Delta$ Modulation(ps)	15.30	14.28	−3.19	−17.84	−1.60	21.28	−10.34	−35.60	2.45	25.02

highlight the performance of the proposed method and provide a quantitative evaluation of its effectiveness in achieving precise clock steering.

Equation (17) can be used to convert the TIE deviation into a frequency-tracking error. Notably, when we do not employ discrete $\Sigma$-$\Delta$ modulation, this results in a frequency tracking error of 40 pHz. However, if we were to utilize discrete $\Sigma$-$\Delta$ modulation, the frequency tracking error would be further reduced to less than 5 pHz. This highlights the advantages and improved precision of using discrete $\Sigma$-$\Delta$ modulation in our methodology.

The experimental results indicate that continuous sampling was conducted for 20,000 s at a sampling rate of 1 Hz. The phase adjustment accuracy is limited to 40 ps, and the frequency adjustment accuracy is 40 pHz when discrete $\Sigma$-$\Delta$ modulation is not used. However, when discrete $\Sigma$-$\Delta$ modulation is used, the phase adjustment accuracy is improved to a level comparable with that of the same-source TIE and achieves an accuracy better than 5 ps. In addition, the frequency adjustment accuracy is enhanced, reaching a level better than 5 pHz.

4.2. ILA Sampling Analysis Experiment

While we are unable to quantitatively measure the exact improvement in accuracy achieved by the DCS method based on discrete $\Sigma$-$\Delta$ modulation using the frequency–time counter, we can utilize the ILA debugging tool provided by the Vivado software package to capture the phase detection value. This value represents the phase difference between two 230 KHz sine wave signals generated by the DDS. Our designed phase detector uses a 32-bit signal. To collect the phase detection values, we continuously sample for a duration of 1000 ms; the OCXO output signal duration for one cycle is $1\times {10}^{-7}$ s. By analyzing and plotting these phase detection values, we can create a phase-tracking error diagram that captures the performance of our system.

Figure 14 clearly illustrates that the phase adjustment accuracy of the DCS method, based on discrete $\Sigma$-$\Delta$ modulation, is 0.48 ps. These results effective demonstrate that the phase adjustment accuracy of DCS reaches the subpicosecond level. Furthermore, by applying Equation (17) to calculate the frequency adjustment accuracy, we show it is 0.48 pHz.

4.3. Discussion of Experimental Results

Considering the limitations imposed by the experimental environment and the noise present in the experimental instruments during Experiment 1, we can only conclude that the phase adjustment accuracy is better than 5 ps and the frequency adjustment accuracy is better than 5 pHz. In Experiment 2, where measurements were obtained via the use of the Vivado ILA debugging tool, the phase adjustment accuracy was determined to be 0.48 ps, with the frequency adjustment accuracy surpassing 0.48 pHz. The proposed approach offers a more effective solution to the challenge of quantization noise, thereby improving the overall accuracy of clock steering.

In fact, a functioning GNSS system, despite facing more complex thermal and electromagnetic noise compared with ground laboratories, is often designed with careful consideration. The internal electronic components are well protected, so the conclusions drawn by the laboratory are not significantly different from the actual situation. Moreover, our experimental design follows the actual payload ground verification standards. Finally, the performance of the atomic clock chosen for the GNSS time–frequency reference system is better than the frequency source selected in this paper. If the findings of this paper are applied to GNSS in the future, the accuracy of frequency and phase adjustments will be even higher.

5. Conclusions

In this study, we present a DCS method based on discrete $\Sigma$-$\Delta$ modulation to address the issue of quantization noise caused by the low resolution of the DAC. The DCS model is provided, and the error theory is analyzed. The main error component is the quantization noise stemming from the low resolution of the DAC. We present a discrete $\Sigma$-$\Delta$ modulation model and design the optimal $\Sigma$-$\Delta$ modulator using an augmented Lagrangian method, achieving high-precision clock steering. Furthermore, we provide a strategy for designing the optimal loop bandwidth accordingly. Simulation results demonstrate that, without using the $\Sigma$-$\Delta$ modulation circuit, the frequency and phase adjustment accuracy are 0.9 pHz and 0.9 ps, respectively. However, by using the method proposed in this study, the phase adjustment accuracy improves to 0.24 ps, and the frequency adjustment accuracy improves to 0.24 pHz. The experimental results confirm that this method yields a phase adjustment accuracy of 0.48 ps and a frequency adjustment accuracy better than 0.48 pHz. Remarkably, this represents an improvement of two orders of magnitude compared with the accuracy of existing GNSS time–frequency reference systems. The experimental findings strongly validate the effectiveness of the DCS method based on discrete $\Sigma$-$\Delta$ modulation, thereby confirming its capacity to enhance both frequency and phase adjustment accuracy.

The proposed method holds significant importance for enhancing the accuracy of GNSS time–frequency reference applications. Moreover, high-precision DCS offers a low-cost, lightweight, high-precision, and efficient means of achieving time–frequency synchronization in various fields, such as distributed communication, UAV collaboration, and basic scientific research.