Intelligent Hybrid Caching for Sustainable Big Data Processing: Leveraging NVM to Enable Green Digital Transformation
Abstract
1. Introduction
- (1)
- How can DAG dependency analysis (reuse distance and frequency) be effectively combined with GC behavior monitoring to predict data access patterns and guide cache placement decisions in Apache Spark?
- (2)
- What cost–benefit model can quantitatively evaluate the trade-offs between data migration overhead and cache performance gains to enable dynamic optimization of DRAM-NVM data placement?
- (3)
- How does the proposed IHCMF strategy perform across diverse workloads and varying DRAM-NVM capacity ratios compared to default Spark caching mechanisms, and what are the resulting implications for energy-efficient computing?
2. Related Work
2.1. Classical Caching Strategies
2.2. DAG-Based Caching Strategies
2.3. Hybrid Memory Management
2.4. Machine Learning-Based Approaches
2.5. Edge Computing and IoT Data Processing
2.6. Research Gaps and Contributions
3. Methods
3.1. Hybrid Cache Management System Design
- Design Objectives: NVM technology offers high storage capacity, persistence, and cost efficiency, complementing DRAM’s low latency and high bandwidth [45]. As illustrated in Figure 1, hybrid integration enables the utilization of their respective strengths, substantially improving cache performance and system efficiency.
- Key Components: The architecture design of the hybrid caching system comprises several key components. The Hybrid Cache Manager oversees cache operations. The DRAM Cache provides rapid access to frequently used data, while the NVM Cache stores less frequently accessed data and ensures persistence. The Memory Manager handles resource allocation, whereas the Data Migration Module performs dynamic data relocation based on access frequency patterns and system states. Additionally, the Consistency Module maintains data coherence across DRAM and NVM during migration and access operations, ensuring data correctness and reliability.
- Data Placement and Migration Strategies: The hybrid caching system adopts a two-phase strategy for data placement and migration. Initially, data blocks are allocated to DRAM or NVM based on access frequency patterns, with frequently accessed data prioritized for DRAM and less frequently accessed or persistent data stored in NVM. The dynamic mechanism subsequently adjusts data block locations between DRAM and NVM in response to changing access patterns and system conditions to sustain optimal performance. Furthermore, the system conducts a cost–benefit analysis that evaluates the trade-offs between migration costs, including transmission latency and energy consumption, and performance gains, such as reduced latency and increased cache hit rates. This ensures that data migration occurs only when the performance improvement outweighs the overhead.
- Cache Coherence: In a hybrid caching system that integrates DRAM and NVM, maintaining cache coherence is essential for ensuring data correctness and integrity during inter-media migration. The system implements multiple cache consistency mechanisms to achieve this objective. The Write-Back strategy initially updates data in cache and writes back to persistent storage upon eviction, thereby minimizing write amplification while requiring mechanisms for data loss prevention. Conversely, the Write-Through strategy updates both cache and persistent storage simultaneously, ensuring consistency despite increased write operations. Additionally, a Version Control mechanism monitors data block versions to identify and resolve inconsistencies through synchronization when necessary. Collectively, these mechanisms ensure reliable, consistent, and fault-tolerant data management in the hybrid caching system.
3.2. Intelligent Hybrid Caching Management Framework (IHCMF)
3.3. Cache Management Process
3.3.1. Cache Management Strategy Based on DAG Dependencies
3.3.2. Hybrid Memory Management Strategy Based on Garbage Collection
3.3.3. Cache Management Strategy
3.3.4. Class Architecture
3.4. Optimization Strategy
3.4.1. Cache Block Placement Strategy Based on DAG
- (1)
- Predict access patterns: Analyze the DAG to forecast data blocks expected to undergo frequent access in future computational operations.
- (2)
- Intelligent placement: Allocate data blocks with predicted high access frequencies to fast storage media (e.g., DRAM) to reduce latency and improve efficiency.
- (3)
- Fusion of LRU and LFU strategies:
- (1)
- Reuse distance: This metric is selected due to its direct correlation with the temporal proximity of future accesses. A smaller reuse distance indicates that a data block will likely be accessed sooner, making it an optimal candidate for placement in DRAM to minimize access latency.
- (2)
- Reuse frequency: This metric reflects the significance of a data block in overall computation. A higher reuse frequency demonstrates that the data block is repeatedly utilized across multiple stages, thereby justifying its placement in DRAM to improve cache hit rates and overall performance.
3.4.2. Cache Management Based on GC Behavior
3.4.3. Data Placement and Migration Strategy
- (1)
- Initial placement based on access patterns: The system initially allocates data blocks according to their observed access frequencies. Frequently accessed data blocks are prioritized for placement in DRAM to minimize access latency and improve computational throughput. Conversely, data blocks with low access frequency and long-term retention requirements are allocated to NVM, leveraging its higher capacity and persistence.
- (2)
- Based on prediction: The system utilizes DAG dependency analysis and GC behavior analysis results to predict future data block access patterns. Data blocks predicted to exhibit high reuse frequency or short reuse distances are preferentially placed in DRAM to maximize cache hit rates. In contrast, blocks anticipated to have low access frequency are stored in NVM, ensuring balanced utilization of heterogeneous memory resources.
- (3)
- Cost–benefit analysis: Data block placement considers storage media cost-effectiveness. High-value data blocks (those associated with significant computing and recovery costs) are prioritized for DRAM placement to reduce recomputation overheads. Meanwhile, low-value data blocks are allocated to NVM, optimizing overall system cost-efficiency without compromising performance.
- Migration trigger conditions:
- 2.
- Migration cost assessment:
- 3.
- Migration Decision Model:
3.4.4. Parameter Configuration
4. Experiment
Experimental Environment
5. Result and Discussion
5.1. The Overall Performance of Different Caching Systems
5.2. Cache Hit Performance of Different Cache Systems
5.3. Performance of Mixed Cache with Different Proportions of DRAM and NVM
6. Conclusions and Future Work
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Abbreviations
| IoT | Internet of Things |
| DAG | Directed Acyclic Graph |
| GC | Garbage Collection |
| NVM | Non-Volatile Memory |
| LRU | Least Recently Used |
| LFU | Least Frequently Used |
| DRAM | Dynamic Random-Access Memory |
| RDDs | Resilient Distributed Datasets |
| LRC | Least Reference Counting |
| RDE | Reuse Distance Estimation |
| IHCMF | Intelligent Hybrid Caching Management Framework |
| JVM | Java Virtual Machine |
References
- Sergio, R.-G.; Mourino-Talin, H.; Martinez-Rego, D.; Bolon-Canedo, V.; Benitez, J.M.; Alonso-Betanzos, A.; Herrera, F. An Information Theory-Based Feature Selection Framework for Big Data Under Apache Spark. IEEE Trans. Syst. Man Cybern. 2018, 48, 1441–1453. [Google Scholar] [CrossRef]
- Shehabi, A.; Smith, S.; Sartor, D.; Brown, R.; Herrlin, M.; Koomey, J.; Masanet, E.; Horner, N.; Azevedo, I.; Lintner, W. 2024 United States Data Center Energy Usage Report (Report No. LBNL-2001637); Lawrence Berkeley National Laboratory: Berkeley, CA, USA, 2024. [CrossRef]
- Agency, I.E. “Energy and AI,” International Energy Agency. 2025. Available online: https://www.iea.org/reports/energy-and-ai/executive-summary (accessed on 10 April 2025).
- Patil, O.; Ionkov, L.; Lee, J.; Mueller, F.; Lang, M. NVM-based Energy and Cost Efficient HPC Clusters. In Proceedings of the International Symposium on Memory Systems, Washington, DC, USA; Association for Computing Machinery: New York, NY, USA, 2021; p. 18. Available online: https://arcb.csc.ncsu.edu/~mueller/ftp/pub/mueller/papers/memsys21-1.pdf (accessed on 5 November 2025).
- Bashir, N.; Priya, D.; Cuff, J.; Sydney, S.; Marija, I.; Sze, V.; Christina, D.; Elsa, O. The Climate and Sustainability Implications of Generative AI. In An MIT Exploration of Generative AI; MIT: Cambridge, MA, USA, 2024. [Google Scholar] [CrossRef]
- Park, S.; Jeong, M.; Han, H. CCA: Cost-Capacity-Aware Caching for In-Memory Data Analytics Frameworks. Sensors 2021, 21, 2321. [Google Scholar] [CrossRef]
- Kawsar, H.; Somayyeh, T.; Maziar, G.; Siamak, M. Infrastructure Aware Heterogeneous-Workloads Scheduling for Data Center Energy Cost Minimization. IEEE Trans. Cloud Comput. 2022, 10, 972–983. [Google Scholar] [CrossRef]
- Ioannis, K.; Iraklis, A.; Alexandros, B.; Dimitrios, S. Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory. IEEE Embed. Syst. Lett. 2016, 8, 57–60. [Google Scholar] [CrossRef]
- Yu, Y.; Wang, W.; Zhang, J.; Ben Letaief, K. LRC: Dependency-Aware Cache Management for Data Analytics Clusters. arXiv 2017. [Google Scholar] [CrossRef]
- Muhib, K.; Mahtab, A.M.; Asoke, N.; Yu, W. Exploration of memory hybridization for RDD caching in Spark. In 2019 ACM SIGPLAN International Symposium on Memory Management Phoenix AZ USA; Association for Computing Machinery: New York, NY, USA, 2019. [Google Scholar]
- Chen, L.; Zhao, J.; Wang, C.; Cao, T.; Zigman, J.; Volos, H.; Mutlu, O.; Lv, F.; Feng, X.; Xu, G.H.; et al. Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories. ACM Trans. Comput. Syst. 2021, 39, 1–38. [Google Scholar] [CrossRef]
- Cheng, Y.; Xiang, Y.; Chen, W.; Hassan, H.; Alelaiwi, A. Efficient cache resource aggregation using adaptive multi-level exclusive caching policies. Future Gener. Comput. Syst. 2018, 86, 964–974. [Google Scholar] [CrossRef]
- Hedayati, S.S.; Neda, M.; Tobias, O.; Fredrik, A.; Mahdi, S.; Kamal, B. MapReduce scheduling algorithms in Hadoop: A systematic study. J. Cloud Comput. 2023, 12, 143. [Google Scholar] [CrossRef]
- Luiz, F.B.; Alfredo, G.; Mauro, M.E.R.; Nelson, L.S.D.F.; Rizos, S. Scheduling in distributed systems: A cloud computing perspective. Comput. Sci. Rev. 2018, 30, 31–54. [Google Scholar] [CrossRef]
- Kesavan, M.V.; Josephine, P.; Manimegalai, A. Survey on MapReduce Scheduler Algorithms in Hadoop Framework. Int. J. Innov. Res. Inf. Secur. 2024, 10, 314–319. [Google Scholar] [CrossRef]
- Zhang, J.; Zhang, R.; Alfarraj, O.; Tolba, A.; Kim, G.J. A Memory-Aware Spark Cache Replacement Strategy. J. Internet Technol. 2022, 23, 1185–1190. [Google Scholar] [CrossRef]
- Yu, Y.; Zhang, C.; Wang, W.; Zhang, J.; Letaief, K.B. Towards Dependency-Aware Cache Management for Data Analytics Applications. IEEE Trans. Cloud Comput. 2022, 10, 706–723. [Google Scholar] [CrossRef]
- Zhao, Y.; Dong, J.; Liu, H.; Wu, J.; Liu, Y. Performance Improvement of DAG-Aware Task Scheduling Algorithms with Efficient Cache Management in Spark. Electronics 2021, 10, 1874. [Google Scholar] [CrossRef]
- Maha, D.; Sherif, M.S.; Sameh, A.S.; Saad, E.M.; Hesham, E. Memory Management Approaches in Apache Spark: A Review. In Advances in Intelligent Systems and Computing; Springer: Cham, Switzerland, 2020; pp. 394–403. [Google Scholar] [CrossRef]
- Perez, T.B.; Zhou, X.; Cheng, D. Reference-distance Eviction and Prefetching for Cache Management in Spark. In Proceedings of the 47th International Conference on Parallel Processing, USA; Association for Computing Machinery: New York, NY, USA, 2018. [Google Scholar]
- Das, S.D. Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy. IEEE MICRO 2022, 43, 99–109. [Google Scholar] [CrossRef]
- Lee, K.; Kim, S.; Lee, J.; Moon, D.; Kim, R.; Kim, H.; Ji, H.; Mun, Y.; Joo, Y. Improving key-value cache performance with heterogeneous memory tiering: A case study of CXL-based memory expansion. IEEE MICRO 2024, 45, 102–113. [Google Scholar] [CrossRef]
- Wu, M.; Mao, L.; Lin, Y.; Jin, Y.; Li, Z.; Lyu, H.; Tang, L.; Liu, X.; Tang, H.; Dong, D.; et al. Jade: A High-throughput Concurrent Copying Garbage Collector. In Proceedings of the Nineteenth European Conference on Computer Systems; Association for Computing Machinery: New York, NY, USA, 2024. [Google Scholar]
- Chen, Y.; Peng, I.B.; Peng, Z.; Liu, X.; Ren, B. ATMem: Adaptive data placement in graph applications on heterogeneous memories. In Proceedings of the 18th ACM/IEEE International Symposium on Code Generation and Optimization; Association for Computing Machinery: New York, NY, USA, 2020. [Google Scholar]
- Wang, C.; Cui, H.; Cao, T.; Zigman, J.; Volos, H.; Mutlu, O.; Lv, F.; Feng, X.; Xu, G. Panthera: Holistic memory management for big data processing over hybrid memories. In Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, New York; Association for Computing Machinery: New York, NY, USA, 2019. [Google Scholar]
- Vidal, R.L.A.; Eugene, G.; Ricardo, B. Page placement in hybrid memory systems. In Proceedings of the International Conference on Supercomputing; Association for Computing Machinery: New York, NY, USA, 2011. [Google Scholar]
- Xu, L.; Chen, G.; Li, D.; Luo, H. PM-Migration: A Page Placement Mechanism for Real-Time Systems with Hybrid Memory Architecture; Lecture Notes in Computer Science; Springer Nature: Singapore, 2024; pp. 313–324. [Google Scholar] [CrossRef]
- Dimitra, D.T.; Sergey, B.; Abhinav, V.; Sudhanva, G.; Ada, G. Kleio: A hybrid memory page scheduler with machine intelligence. In Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing, New York; Association for Computing Machinery: New York, NY, USA, 2019. [Google Scholar]
- Dimitra, D.T.; Ada, G. Toward Computer Vision-based Machine Intelligent Hybrid Memory Management. In Proceedings of the International Symposium on Memory Systems, New York; Association for Computing Machinery: New York, NY, USA, 2021. [Google Scholar]
- Dimitra, D.T.; Ada, G. Cronus: Computer Vision-based Machine Intelligent Hybrid Memory Management. In Proceedings of the 2022 International Symposium on Memory Systems, New York; Association for Computing Machinery: New York, NY, USA, 2022. [Google Scholar]
- Zhou, Y.; Wang, F.; Shi, Z.; Feng, D. An Efficient Deep Reinforcement Learning-Based Automatic Cache Replacement Policy in Cloud Block Storage Systems. IEEE Trans. Comput. 2023, 73, 164–177. [Google Scholar] [CrossRef]
- Sun, C.; Li, X.; Wen, J.; Wang, X.; Han, Z.; Leung, V.C. Federated Deep Reinforcement Learning for Recommendation-Enabled Edge Caching in Mobile Edge-Cloud Computing Networks. IEEE J. Sel. Areas Commun. 2023, 41, 690–705. [Google Scholar] [CrossRef]
- Mohammad, G.; Marimuthu, P.; Rajkumar, B. Scheduling IoT Applications in Edge and Fog Computing Environments: A Taxonomy and Future Directions. Acm Comput. Surv. 2022, 55, 1–41. [Google Scholar] [CrossRef]
- Tu, J.; Yang, L.; Cao, J. Distributed Machine Learning in Edge Computing: Challenges, Solutions and Future Directions. Acm Comput. Surv. 2024, 57, 1–37. [Google Scholar] [CrossRef]
- Wang, X.; Tang, Z.; Guo, J.; Meng, T.; Wang, C.; Wang, T.; Jia, W. Empowering Edge Intelligence: A Comprehensive Survey on On-Device AI Models. Acm Comput. Surv. 2025, 57, 1–39. [Google Scholar] [CrossRef]
- Sodiya, E.O.; Umoga, U.J.; Obaigbena, A.; Jacks, B.S.; Ugwuanyi, E.D.; Daraojimba, A.I.; Lottu, O.A. Current state and prospects of edge computing within the Internet of Things (IoT) ecosystem. Int. J. Sci. Res. Arch. 2024, 11, 1863–1873. [Google Scholar] [CrossRef]
- Yang, Q.; Deng, H.; Wang, L. A Lightweight Caching Decision Strategy Based on Node Edge-Degree for Information Centric Networking. IEEE Access 2020, 13, 124389–124401. [Google Scholar] [CrossRef]
- Sandeep, K. Real-Time Processing in Autonomous Vehicle Networks: A Distributed Edge-Cloud Architecture for Enhanced Autonomous Vehicle Performance. Int. J. Res. Comput. Appl. Inf. Technol. 2024, 7, 2828–2841. [Google Scholar] [CrossRef]
- Li, W.; Shen, Z.; Liu, X.; Ding, C.; Shen, J. Fed-OGD: Mitigating Straggler Effects in Federated Learning via Orthogonal Gradient Descent. IEEE Trans. Comput. 2025, 74, 3018–3031. [Google Scholar] [CrossRef]
- Lee, S.; Bahn, H.; Noh, S.H. CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures. IEEE Trans. Comput. 2013, 63, 2187–2200. [Google Scholar] [CrossRef]
- Tanmay, J.; Avaneesh, V.; Rajeev, S.R. Latency-Memory Optimized Splitting of Convolution Neural Networks for Resource Constrained Edge Devices. In 2022 14th International Conference on COMmunication Systems & NETworkS (COMSNETS); IEEE: Bangalore, India, 2022. [Google Scholar]
- Huang, M.; Lin, J.-J.; Peng, Y.; Xie, X. Design a batched information retrieval system based on a concept-lattice-like structure. Knowl.-Based Syst. 2018, 150, 74–84. [Google Scholar] [CrossRef]
- Wang, C.; Cao, T.; Zigman, J.; Lv, F.; Zhang, Y.; Feng, X. Efficient Management for Hybrid Memory in Managed Language Runtime; Lecture Notes in Computer Science; Springer: Cham, Switzerland, 2016; pp. 29–42. [Google Scholar] [CrossRef]
- Khanh, N.; Fang, L.; Xu, G.; Demsky, B.; Lu, S.; Alamian, A.; Mutlu, O. Yak: A high-performance big-data-friendly garbage collector. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis; USENIX: Berkeley, CA, USA, 2016. [Google Scholar]
- Kim, M.; Kim, B.S.; Lee, E.; Lee, S. A Case Study of a DRAM-NVM Hybrid Memory Allocator for Key-Value Stores. IEEE Comput. Archit. Lett. 2022, 21, 81–84. [Google Scholar] [CrossRef]
- Tong, Y.; Liu, J.; Wang, H.; He, M.; Zhou, K.; He, R.; Zhang, Q.; Wang, C. DAG-aware harmonizing job scheduling and data caching for disaggregated analytics frameworks. Future Gener. Comput. Syst. 2024, 156, 116–129. [Google Scholar] [CrossRef]







| No. | Test Case | Description |
|---|---|---|
| 1 | PageRank | The dataset employed for evaluating the performance of graph computing typically comprises web page links and the implementation of ranking algorithms. |
| 2 | K-Means | The dataset used for clustering algorithms is employed to test the performance of the machine learning library. |
| 3 | SQL Queries | A set of SQL queries used to test the performance of the Spark SQL module. |
| 4 | Streaming | Stream processing test cases, used to evaluate the performance of real-time data processing. |
Disclaimer/Publisher’s Note: The statements, opinions and data contained in all publications are solely those of the individual author(s) and contributor(s) and not of MDPI and/or the editor(s). MDPI and/or the editor(s) disclaim responsibility for any injury to people or property resulting from any ideas, methods, instructions or products referred to in the content. |
© 2026 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license.
Share and Cite
Tong, L.; Shen, Q.; Xie, Z. Intelligent Hybrid Caching for Sustainable Big Data Processing: Leveraging NVM to Enable Green Digital Transformation. Sustainability 2026, 18, 2601. https://doi.org/10.3390/su18052601
Tong L, Shen Q, Xie Z. Intelligent Hybrid Caching for Sustainable Big Data Processing: Leveraging NVM to Enable Green Digital Transformation. Sustainability. 2026; 18(5):2601. https://doi.org/10.3390/su18052601
Chicago/Turabian StyleTong, Lei, Qing Shen, and Zhenqiang Xie. 2026. "Intelligent Hybrid Caching for Sustainable Big Data Processing: Leveraging NVM to Enable Green Digital Transformation" Sustainability 18, no. 5: 2601. https://doi.org/10.3390/su18052601
APA StyleTong, L., Shen, Q., & Xie, Z. (2026). Intelligent Hybrid Caching for Sustainable Big Data Processing: Leveraging NVM to Enable Green Digital Transformation. Sustainability, 18(5), 2601. https://doi.org/10.3390/su18052601

