An Asymmetrical Step-Up Multilevel Inverter Based on Switched-Capacitor Network

Abstract

This paper presents a transformerless step-up multilevel inverter based on a switched-capacitor structure. One of the main contributions of the proposed topology is replacing the separated DC voltage source with capacitors which are charged at predetermined time intervals. Therefore, a high-level staircase voltage waveform can be achieved by discharging some of these capacitors on the load. The other contribution of the proposed structure is to eliminate the magnetic elements which traditionally boost the input DC voltage. In addition, asymmetrical or unequal amounts of capacitor voltages create more voltage levels, which enable voltage level increments without increasing the number of semiconductor devices. This paper introduces a self-balanced boost Switched-Capacitors Multilevel Inverter (SCMLI) which is able to create a nearly sinusoidal voltage waveform with a maximum voltage of up to 45 times that of the input voltage DC source. Higher level output voltage levels are also achievable by extending the circuit topology. After determination of the switching angles and selecting the proper switching states for each level, an offline NLC method is used for modulation, which eases the control implementation. Analysis, simulation and experiments are carried out for a 91-level inverter (45 levels for positive and negative voltages and one for zero voltage) are presented.

1. Introduction

Multilevel inverters (MLIs) are widely used in high voltage high power applications such as renewable energy resources, HVDC systems, power industry, high power motor drives, and energy transmission systems [1]. The term “multi-level” was started with the three-level converter in 1981 by Nabae [2], and gradually expanded to higher levels. These converters include arrays of power semiconductors, capacitors and DC sources which generate a staircase voltage waveform through a proper pulse pattern. Neutral point clamped (NPC) and flying capacitor (FC) [3] are among the famous topologies of MLIs, which utilize different capacitors and switches to generate a staircase voltage waveform. Cascaded H-Bridge (CHB) topology is introduced for systems with multiple separate DC sources such as solar cell farms [4] and a single DC source [5].

Increasing the voltage levels improves output voltage quality but leads to an increment of switching devices and other components. This consequently causes complexity in the control and maintenance of such systems. Multilevel converters with asymmetrical or unequal DC sources are introduced to achieve higher voltage levels without increasing the number of circuit components [6,7]. In order to achieve higher voltage levels at the output, [8,9,10] new structures with fewer components and DC sources have been proposed. Different topologies for symmetric and asymmetric multilevel inverters are shown in [11], which summarizes recent improved topologies. For both symmetrical and asymmetrical topologies, multiple DC sources are required, which may not be available in all conditions [12]. Capacitors can be used in these structures but they also need additional circuits for voltage balancing. Therefore, a converter with the lowest possible number of DC sources and self-balanced capacitors is essential in order to achieve higher voltage levels with a reduced number of components [13]. On the other hand, low voltage DC input sources are used in many applications such as photovoltaic farms [14], electric vehicles [15] and battery applications [16]. Step-up DC-AC Power converters are required to generate voltage for AC loads or grid connection purposes. Traditionally, multi-stage power conversion is required to achieve the required voltage. A transformerless converter is required to convert low voltage DC to high output AC voltage at a single stage.

The authors of [17] presented a single source self-balanced SCMLI topology which uses two switches, two diodes and a capacitor to generate each voltage level. A bipolar MLI based on CHB structure is presented at [18] which consist of full bridge modules. These two topologies suffer from a large number of switching components and high voltage stress on switches. To overcome this limitation, [19] presented a modular SCMLI structure which consists of modules with three powers switches. The number of semiconductors decreased in [20,21] by improving this topology by replacing a diode instead of a switch, which causes a reduction of the number of required drivers as well. The structure proposed in [22] reduces the number of switches to one in each module, which leads to reducing drivers and ease of control in comparison with other topologies. However, the voltage stress on each of the switches increases by voltage level increment as well as increasing the number of series diodes. The authors of [23] presented another SCMLI to reduce voltage stress on the switches based on cascading different modules together. The main problem of this structure is the requirement of additional circuits for balancing purposes.

In this paper, the proposed topology solves the main issues of the mentioned topologies which are (i) the number of switching devices, and (ii) voltage stress on different components during level increment. Moreover, the proposed structure has the ability to boost the input voltage without using any magnetic elements, and can convert a low DC voltage to a high voltage AC output by using single DC source. The challenge of the number of components necessitates the presentation of a step up DC-AC MLI converter based on SC network with reduced number of circuit elements such as capacitors and power semiconductors. Charging the capacitors (up to multiples of input voltage) and smart discharging of several capacitors at predetermined periods enables the proposed topology to increase the number of voltage level steps and boost ratio of the converter. As the input voltage of the converter is low, the rating of components is kept within an acceptable range.

The next section of the paper explains the circuit topology and its modules. Topology operation such as switching states, mathematical analysis, modulation strategy, charging and discharging of capacitors are analyzed at Section 3. A circuit extension and a comparative study is carried out in Section 4. The analyses are validated by a simulation and experimental results in Section 5. A conclusion is presented in Section 6.

2. Proposed Topology

Figure 1a shows circuit topology of the multi-stage converter presented by F. Z. Peng et al. [24] where the capacitors of previous stages charge the capacitors of the next stages and then, the capacitors of the last stage generate multilevel AC voltage through a specific pulse pattern. Half-bridge building block modules (see Figure 1b) are used to connect the capacitors together. This module includes two two-quadrant switches (S₁ and S₂) which enable bidirectional current flow but can only block positive off-stage voltage. As the capacitors of the last stage are involved in output voltage generation and all capacitors are charged to Vin, the number of circuit components increases in order to achieve higher output voltages. This is because of the limitation of the building blocks to control the currents from different ports of the module. Charging capacitors to multiples of input voltage leads to decrement of circuit components. For this purpose, building blocks are required to control the current flow from three ports of the module. Two other switches (S′₁ and S′₂) are added to the module in order to control the current flow from different sides of the module. Figure 2a shows the configuration of the proposed converter where modified modules are used. Owing to the modified module (see Figure 2b), a number of capacitors are combined with power semiconductors to form a multi-stage switched-capacitor network. Special charging and discharging algorithms have to be considered to achieve multilevel output voltage through special arrangement of switches and capacitors. The main difference between the proposed topology and that shown in Figure 1 is the contribution of all the capacitors in multilevel voltage generation as well as charging the capacitors to multiples of Vin. As shown in Figure 2, S′₁ and S′₂ can be selected as unidirectional (two-quadrant switches that are shown in circle or square inclusion depending on the requirement for controlling current flow from one side) or bidirectional (four-quadrant switches that are shown in rectangular inclusion) switches.

3. Operating Principle of the Proposed Topology

Figure 3 shows a three-stage proposed converter where 9 modules and 42 switches (38 for SCMLI and 4 for H-bridge) are used. Note that the modules of the last stage can be simplified, and some of the switches can be eliminated. S_mn is nth switch of m^th module and C_Mi is the capacitor of i^th module. A Switching state of (S_M1, S_M2, …, S_M9) can be defined for this converter where S_Mi (i = 1, 2, …, 9) is the switching state for each module.

4. Asymmetrical Charging of the Capacitors

As mentioned, the main concept of this inverter is to charge the capacitors to multiples of the input voltage through switches. Figure 4 shows charging some states of different capacitors. As shown in Figure 4a, V_CM1 reaches to V_in through the switches of modules 1 and 2. Voltage of C_M3 reaches to 3V_in via C_M1, C_M2 and input DC source (see Figure 4b). C_M6 and C_M9 charges to 3V_in in parallel with C_M3 and C_M5 respectively (see Figure 4c). C_M8 is charged to 14V_in via specified paths, which are shown in Figure 4d.

Some selected capacitor charging paths are indicated in Figure 4. According to this figure, by modeling each path, the equation of each capacitor voltage during charging can be achieved. The same scenario can be carried out for discharging paths to find equations of capacitors voltages during discharging intervals.

Figure 5 shows the model of charging circuit for C_M1. In this model, the following non-idealities are considered for diodes, switches and capacitors:

• V_Dij: Diode on-state voltage of i^th module and j^th diode
• R_Dij: Diode on-state resistant of i^th module and j^th diode
• r_cn: ESR of nth capacitor
• V_Sij: Switch on-state voltage of i^th module and j^th switch
• R_Sij: R_Dij: Switch on-state resistant of i^th module and j^th switch

In the case of calculating capacitor voltage, there is a basic equation which compromised both power switches and diode voltage, which for the n^th module during charge can be calculated as:

$$V_{C_{Mn}}^{ch}(t)=(V_{i{n}_{Mn}}-(k{V}_{SW,on}+m{V}_{D,on}))(1-e^{-\frac{t}{{\tau }_{C_{Mn}}}})$$

(1)

There are different switches and diodes in each charging and discharging states and in the above equation, k and m are the number of switches and diodes in the charging paths respectively. C_Mn, $V_{d{c}_{Mn}}$ and ${\tau }_{C_{Mn}}$ are capacitance value, input voltage and time constant of nth module. Time constant of C_Mn during charging can be calculated: (note that, on-resistance of the switches and diodes are considered as the same.)

$${\tau }_{C_{Mn}}=\left(k{R}_{sw}+m{R}_D+r_{cn}\right)·C_{Mn}$$

(2)

According to different modules in the proposed asymmetric multilevel inverter (see Figure 4) the input voltage of module 1 is $V_{dc}-\left(3V_{sw,on}+3V_{D,on}\right)$ and its time constant is $\left(3R_{sw}+3R_D+r_c\right)·C_{M1}$. Therefore, $V_{C_{M1}}$ can be shown as:

$$V_{C_{M1}}(t)=(V_{dc}-(3V_{SW,on}+3V_{D,on}))(1-e^{-\frac{t}{\left(3R_{sw}+3R_D+r_c\right)·C_{M1}}})$$

(3)

The same procedure has to be carried out to calculate all of the capacitor voltages during charging.

Table 1. Different parameters for different capacitors.

n	${\mathit{V}}_{\mathit{i}{\mathit{n}}_{\mathit{M}\mathit{n}}}$	k	m
2	$V_{dc}$	3	3
3	$V_{dc}+V_{C_{M1}}(t)+V_{C_{M2}}(t)$	6	6
4	$V_{dc}+V_{C_{M1}}(t)+V_{C_{M2}}(t)+V_{C_{M3}}(t)+V_{C_{M5}}(t)$	12	8
5	$V_{dc}+V_{C_{M1}}(t)+V_{C_{M2}}(t)$	6	6
6	$V_{C_{M3}}(t)$	3	3
7	$V_{dc}+V_{C_{M1}}(t)+V_{C_{M3}}(t)+V_{C_{M4}}(t)$	10	6
8	$V_{dc}+V_{C_{M2}}(t)+V_{C_{M4}}(t)+V_{C_{M5}}(t)$	10	6
9	$V_{C_{M5}}(t)$	3	3

shows different parameters for the calculation of all other capacitor voltages based on Equation (1), which also illustrates the number of switches and diodes in each path.

5. Multilevel Output Voltage Generation

Output voltage generation is carried out according to

Table 2. possible switching states for each module and voltage state of each capacitor (Charge: ▲, Discharge: ▼, No Change: -).

	VCM1	VCM2	VCM3	VCM4	VCM5	VCM6	VCM7	VCM8	VCM9
0(0000)	0 (-)	0 (-)	0 (-)	0 (-)	0 (-)	0 (-)	0 (-)	0 (-)	3Vin (▼)
2(0010)	⨯	⨯	⨯	⨯	⨯	3Vin (▼)	14Vin(▼,▲)	14Vin (▼,▲)	⨯
3 (0011)	0 (-)	0 (-)	0 (-)	0 (-)	0 (-)	⨯	⨯	⨯	⨯
4(0100)	⨯	⨯	⨯	⨯	⨯	3Vin (▼)	14Vin (▼)	14Vin (▼)	0 (-, ▲)
5(0101)	−1Vin (▲)	1Vin (▼)	−3Vin (▲)	9Vin (▼) −9Vin (▼)	3Vin (▼)	⨯	⨯	⨯	⨯
6(0110)	⨯	⨯	⨯	⨯	⨯	0 (-)	0 (-)	0 (-)	_
8(1000)	⨯	⨯	⨯	⨯	⨯	0 (-)	0 (-)	0 (-)	3Vin(▼)
9(1001)	1Vin(▼)	1Vin(▼)	3Vin(▼)	9Vin (▲▼) −9Vin(▼)	3Vin(▼)	⨯	⨯	⨯	⨯
A(1010)	1Vin(▼)	−1Vin(▲)	3Vin(▼)	9Vin (▼) −9Vin (▼)	−3Vin (▲)	3Vin (▲)	14Vin (▼)	14Vin (▼)	⨯
B(1011)	1Vin (▼)	1Vin (▲)	3Vin (▼)	⨯	3Vin (▲)	⨯	⨯	⨯	⨯
C(1100)	0 (-)	0 (-)	0 (-)	⨯	0 (-)	⨯	⨯	⨯	⨯
D(1101)	1Vin (▲)	1Vin (▼)	3Vin (▲)	⨯	3Vin (▼)	⨯	⨯	⨯

, i.e., the information provided about specific voltage generation for each module related to their possible switching states. To achieve a self-balanced system, charging and discharging states for the capacitors of each module should be available by switching pattern. To generate different levels, the ability of modules to keep the voltage within an acceptable range has to be analyzed. Therefore, Table 2 shows possible switching states for each module to generate mentioned output voltages. For each module, capacitor voltage is shown for the available switching states along with its charging or discharging mode. Note that “⨯” implies that mentioned switching state is not used at that specific module. Charging, discharging and no change mode of the module are shown with “▲”, “▼” and “–” respectively.

Having redundant states is an important issue in the generation of output voltage levels for multilevel inverters. According to Table 2, various alternatives are available for each module, which can be selected in order to balance the capacitors voltages. For instance, Module 1 is charged by switching state 5 and will be discharged by A, B and 9. States 0, 3 and C bypass C_M1. State D also will charge this capacitor via input DC source. As shown in this table, whether the application of some switching states may lead to charging or discharging the capacitor depends on the switching state of the previous module.

With the same procedure as that used in the previous part, the voltage of each capacitor during discharging intervals can be calculated as:

$$V_{C_{Mn}}^{Disch}(t)=(V_{C_{Mn}}^p(t)-(k{V}_{SW,on}+m{V}_{D,on}))(e^{-\frac{t}{{\tau }_{C_{Mn}}}})$$

(4)

where, $V_{C_{Mn}}^{Disch}(t)$ is the discharge voltage of C_Mn and $V_{C_{Mn}}^p(t)$ is the initial voltage of the capacitor before discharging. Other parameters (m and k) are the same as Table 1.

Choosing a proper switching pattern is the main challenge of this converter. Discharging the combination of capacitors across the load (to form different levels of output AC voltage) may lead to decrements in capacitor voltages. Therefore, to avoid capacitors voltage imbalance, switching states have to be used which are able to charge one or more capacitors during discharging time of other capacitors. This means that the charging time of all the capacitors should be distributed in the discharging intervals.

Table 3. Different switching states of proposed converter.

Level	Switching States (CM1, CM2, CM3, CM4, CM5, CM6, CM7, CM8, CM9)
0VIN	5C0000000(↑− − − − − − − −) 3A0000000(−↑− − − − − − −) A550C0680(↓↓↑− − − − − −) A530A0680(↓↓− −↑− − − −) A5A956868 (↓↓↓↑↓− − − −) 00909A864(− −↓−↓↑− −↑) ACA506280(↓−↓↓− −↑− −) 350A50628(−↓−↓↓− −↑ −)
1VIN	C3D0BA864(− −↓−↓↑− −↑)
2VIN	BBD0BA864(↓↑↓−↓↑− −↑) DDD0BA864(↑↓↓−↓↑− −↑)
3VIN	A5D0BA864(↓↓↓−↓↑− −↑)
4VIN	5D9CBA864(↑↓↓−↓↑− −↑) 3B9CBA864(↓↑↓−↓↑− −↑) BAD39A864(↓↑↓−↓↑− −↑) DCD39A864(↑↓↓−↓↑− −↑)
5VIN	BBB0BA864(↓↑↓−↓↑− −↑) DDB0BA864(↑↓↓−↓↑− −↑) BBD0DA864(↓↑↓−↓↑− −↑ DDD0DA864(↑↓↓−↓↑− −↑)
6VIN	A5D0D8684(↓↓↑−↓− − − −) A5B0B8684(↓↓↓−↑− − − −) 5C9098684(↑−↓−↓− − − −) 3A9098684(−↑↓−↓− − − −) A5B0BA864(↓↓↓−↓↑− −↑) A5D0DA864(↓↓↓−↓↑− −↑)
7VIN	BAD39A804(↓↑↓−↓↑− −↑) DCD39A804(↑↓↓−↓↑− −↑) 5D9CDA864(↑↓↓−↓↑− −↑) 3B9CDA864(↓↑↓−↓↑− −↑)
8VIN	DDB0DA864(↑↓↓−↓↑− −↑) BBB0DA864(↓↑↓−↓↑− −↑)
9VIN	A5B0DA864(↓↓↓−↓↑− −↑) A5B0B8688(↓↓↓−↑− − −↓) A5D0D8688(↓↓↑−↓− − −↓) 5C9094684(↑−↓−↓↓− − −)3A9094684(−↑↓−↓↓− − −)
10VIN	BAB39A808(↓↑↓−↓↑− −) DCB39A808(↑↓↓−↓↑− −↓) 5D9CD4064(↑↓↓−↓↓− −↑) 3B9CD4064(↓↑↓−↓↓− −↑)
11VIN	DDA0D4064(↑↓↓−↓↓− −↑) BBA0D4064(↓↑↓−↓↓− −↑) DDB05A808(↑↓↓−↓↑− −↓) BBB05A808(↓↑↓−↓↑− −↓)
12VIN	5C9094688(↑−↓−↓↓− −↓) 3A9094688(−↑↓−↓↓− −↓) A5D0D4688(↓↓↑−↓↓− −↓) A5B0B4688(↓↓↓−↑↓− −↓) A5B05A808(↓↓↓−↓↑− −↓) A5A0D4064(↓↓↓−↓↓− −↑)
13VIN	5D9ABA864(↑↓↓↓↓↑− −↑) 3B9ABAA864(↓↑↓↓↓↑− −↑) BAD59A864(↓↑↓↓↓↑− −↑) DCD59A864(↑↓↓↓↓↑− −↑)
14VIN	359ABA864(−↓↓↓↓↑− −↑) ACD59A864(↓−↓↓↓↑− −↑)
15VIN	A5A956868(↓↓↓↑↓↓− −↓) 5C999A864(↑−↓↓↓↑− −↑) 3A999A864(−↑↓↓↓↑− −↑)
16VIN	5D9ADA864(↑↓↓↓↓↑− −↑) BAB59A864(↓↑↓↓↓↑− −↑)
17VIN	359ADA864(−↓↓↓↓↑− −↑)
18VIN	5C999A808(↑−↓↓↓↑− −↓) 5C9994064(↑−↓↓↓↓− −↑) 3A999A808(−↑↓↓↓↑− −↓) 3A9994064(−↑↓↓↓↓− −↑)
19VIN	DD30B2464(↑↓− −↓↓↓−↑) DDD0CA8A0(↑↓↓− −↑−↓↓) BB30B2464(↓↑− −↓↓↓−↑) BBD0CA8A0(↓↑↓− −↑−↓↓)
20VIN	ACA596284(↓−↓↓↓↓↑− −) A550D2684(↓↓↑−↓↓↓− −) 359A58628(−↓↓↓↓− −↑↓) A530B2684(↓↓− −↑↓↓− −) 5C9008620(↑−↓− − − −↓↓) 3A9008620(−↑↓− − − −↓↓)
21VIN	5C9994008(↑−↓↓↓↓− −↓) 3A9994008(−↑↓↓↓↓− −↓)
22VIN	DD30D2464(↑↓− −↓↓↓−↑) BB30D2464(↓↑− −↓↓↓−↑) DDD0CA8A0(↑↓↓− −↑−↓↓) BBD0CA8A0(↓↑↓− −↑−↓↓)
23VIN	ACA596288(↓−↓↓↓↓↑−↓) 359A54628(−↓↓↓↓↓−↑↓) A5D0C46A0(↓↓↑− −↓−↓↓) A550D2688(↓↓↑−↓↓↓−↓) A5B0A46A0(↓↓↓−↑↓−↓↓) A530B2688(↓↓− −↑↓↓−↓)
24VIN	5D0C52408(↑↓− −↓↓↓−↓) 3B0C52408(↓↑− −↓↓↓−↓) BAA3040A0(↓↑↓− −↓−↓↓) DCA3040A0(↑↓↓− −↓−↓↓)
25VIN	DD3052408(↑↓− −↓↓↓−↓) BB3052408(↓↑− −↓↓↓−↓) DDA0C40A0(↑↓↓− −↓−↓↓) BBA0C40A0(↓↑↓− −↓−↓↓)
26VIN	5C9094A88(↑−↓−↓↓↓−↓) 3A9094A88(−↑↓−↓↓↓−↓) 5C9094648(↑−↓−↓↓−↓↓) 3A9094648(−↑↓−↓↓−↓↓)
27VIN	5D0AB2464(↑↓−↓↓↓↓−↑) BAD50A8A0(↓↑↓↓−↑−↓↓)
28VIN	ACD50A8A0(↓−↓↓−↑−↓↓) 350AB2464(−↓−↓↓↓↓−↑)
29VIN	5C0992404(↑− −↓↓↓↓− −) 3A0992404(−↑−↓↓↓↓− −) 5C99080A0(↑−↓↓− − −↓↓) 3A99080A0(−↑↓↓− − −↓↓)
30VIN	5D0AD2464(↑↓−↓↓↓↓−↑) 3B0AD2464(−↑−↓↓↓↓−↑)
31VIN	350AD2464(−↓−↓↓↓↓−↑) ACD50A8A0(↓−↓↓−↑−↓↓)
32VIN	5C0992408(↑−−↓↓↓↓−↓) 3A0992408(−↑−↓↓↓↓−↓) 5C99040A0(↑−↓↓−↓−↓↓) 3A99040A0(−↑↓↓−↓−↓↓)
33VIN	35933AA44(−↓↓− −↑↓↓−) ACCC98A64(↓− − −↓−↓↓↑) 5D0A52408(↑↓−↓↓↓↓−↓) BAA5040A0(↓↑↓↓−↓−↓↓)
34VIN	ACA5062A0(↓−↓↓−↓↑↓↓) 350A52628(−↓−↓↓↓↓↑↓) A550C26A0(↓↓↑− −↓↓↓↓) A530A26A0(↓↓− −↑↓↓↓↓) 5C0002220(↑− − − −↓↓↓↓) 3A0002220(−↑ − − −↓↓↓↓)
35VIN	5D933AA48(↑↓↓− −↑↓↓↓) BACC94A64(↓↑− −↓↓↓↓↑)
36VIN	35933AA48(−↓↓− −↑↓↓↓) ACCC94A64(↓− − −↓↓↓↓↑) DD30C24A0(↑↓− − −↓↓↓↓) BB30C24A0(↓↑− − −↓↓↓↓)
37VIN	5C9094A64(↑−↓−↓↓↓↓↑) 3A9094A64(−↑↓−↓↓↓↓↑)
38VIN	BBCC94A48(↓↑− −↓↓↓↓↓) 5D9334A48(↑↓↓− −↓↓↓↓)
39VIN	ACCC94A48(↓− − −↓↓↓↓↓)
40VIN	5C9094A48(↑−↓−↓↓↓↓↓) 3A9094A48(−↑↓−↓↓↓↓↓)
41VIN	099352248(−↓↓−↓↓↓↓↓)
42VIN	359352248(−↓↓−↓↓↓↓↓)
43VIN	5C09024A0(↑− −↓−↓↓↓↓) 3A09024A0(−↑−↓−↓↓↓↓)
44VIN	5D0AC24A0(↑↓−↓−↓↓↓↓) BA35024A0(↓↑−↓−↓↓↓↓)
45VIN	AC35024A0(↓− −↓−↓↓↓↓)

shows the different switching states of the proposed converter to generate different levels. Note that proposed converter has hundreds of switching states, but only the switching states are mentioned in this table, which is crucial for capacitor voltage balancing. As shown in this table, at least one capacitor has the chance to be charged during the discharging of other capacitors (except 39V_in, 41V_in, 42V_in and 45V_in). Figure 6 shows the paths of charging and discharging for the four selected switching states.

6. Capacitor Calculation for Self-Balancing Purpose

Generally, the maximum discharge amount of each capacitor C_Mn during the longest discharging period [t₁, t₂] can be calculated as [25]:

$$Q_{C_{Mn}}={\displaystyle \underset{t_1}{\overset{t_2}{\int }}{I}_{out}\sin \left(2\pi f_{s}t-\varphi \right)}dt$$

(5)

where f_s is fundamental frequency, I_out is the amplitude of output current and $\varphi$ is the phase difference between output current and voltage [19]. Considering Q_M1 and Q_M2 less than 10% maximum charge of C_M1 and C_M2 respectively, these capacitors can be achieved as:

$$C_{M1}>\frac{Q_{c_{M1}}}{0.1V_{in}}$$

(6)

$$C_{M2}>\frac{Q_{c_{M2}}}{0.1V_{in}}$$

(7)

As C_M3 and C_M5 are charged via DC source and series combination of C_M1 and C_M2, $V_{C_{M3}}$ and $V_{C_{M5}}$ are as follows:

$$V_{C_{M3}}=V_{in}+\frac{\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}}{\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}+C_{M3}}\times \left(V_{C_{M1}}+V_{C_{M2}}\right)$$

(8)

$$V_{C_{M5}}=V_{in}+\frac{\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}}{\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}+C_{M5}}\times \left(V_{C_{M1}}+V_{C_{M2}}\right)$$

(9)

Therefore, C_M3 and C_M5 are obtained as:

$$C_{M3}=\frac{\left[\left(\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}\right)\times \left(V_{C_{M1}}+V_{C_{M2}}\right)\right]+V_{in}}{V_{C_{M3}}}-\left(\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}\right)$$

(10)

$$C_{M5}=\frac{\left[\left(\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}\right)\times \left(V_{C_{M1}}+V_{C_{M2}}\right)\right]+V_{in}}{V_{C_{M5}}}-\left(\frac{C_{M1}·C_{M2}}{C_{M1}+C_{M2}}\right)$$

(11)

With the same procedure, other capacitors and their voltages can be calculated as:

$$V_{C_{M4}}=V_{in}+\left(\frac{\left(\frac{1}{C_{M1}}+\frac{1}{C_{M2}}+\frac{1}{C_{M3}}+\frac{1}{C_{M5}}\right)}{\left(\frac{1}{C_{M1}}+\frac{1}{C_{M2}}+\frac{1}{C_{M3}}+\frac{1}{C_{M5}}\right)+C_{M4}}\right)\times \left(V_{C_{M1}}+V_{C_{M2}}+V_{C_{M3}}+V_{C_{M5}}\right)$$

(12)

$$V_{C_{M6}}=\frac{C_{M3}}{C_{M3}+C_{M6}}\times \left(V_{C_{M3}}\right)$$

(13)

$$C_{M6}=\frac{\left(C_{M3}\times V_{C_{M3}}\right)+V_{in}}{V_{C_{M6}}}-C_{M3}$$

(14)

$$V_{C_{M9}}=\frac{C_{M5}}{C_{M5}+C_{M9}}\times \left(V_{C_{M5}}\right)$$

(15)

$$C_{M9}=\frac{\left(C_{M5}\times V_{C_{M5}}\right)+V_{in}}{V_{C_{M9}}}-C_{M5}$$

(16)

$$V_{C_{M7}}=V_{in}+\left(\frac{\left(\frac{1}{C_{M1}}+\frac{1}{C_{M3}}+\frac{1}{C_{M4}}\right)}{\left(\frac{1}{C_{M1}}+\frac{1}{C_{M3}}+\frac{1}{C_{M4}}\right)+C_{M7}}\right)\times \left(V_{C_{M1}}+V_{C_{M3}}+V_{C_{M4}}\right)$$

(17)

7. Modulation Strategy and Switching States Selection

This is an important factor in capacitor voltage balancing due to the definition of charging and discharging intervals which are required for voltage calculations for capacitors. In this study, a predetermined offline PWM strategy was considered to define the switching angles (the angles in which the levels change). Figure 7a shows a sampled staircase multilevel voltage waveform and a reference voltage in a Nearest Level Control (NLC) modulation technique. Figure 7b shows the schematic block diagram of this strategy. The nearest output voltage level V_n can be determined with [26]:

$$V_n=\frac{1}{V_c}round(V_{ref})$$

(18)

After determination of each voltage level and its time duration, a precise switching selection has to be carried out according to Table 3. The selection of one state for each level defines the charging or discharging states of each capacitor, which is an important task to keep the voltages within an acceptable range.

8. Comparison with Other Topologies

A comparative study is carried with other famous topologies which are presented at [13,15,16,17,18,19].

Table 4. Comparison of the proposed topology with conventional and advanced structures.

Topology	Number of Active Switches	Number of Series Diodes	Number of Drivers	Number of Capacitors	Balance Circuit
Proposed	$(2n_{stage}·(n_{stage}+4))$	0	$(2n_{stage}·(n_{stage}+3))+2$	$\frac{\left(n_{stage}+2\right)·\left(n_{stage}+1\right)}{2}-1$	No Need
NPC	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	$N_L-1$	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	$\begin{array}{c}\left(N_L-1\right)/2\end{array}$	Need
FC	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	0	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	$\left(N_L-2\right)$	Need
CHB	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	0	$\begin{array}{c}2\left(N_L-1\right)\end{array}$	$\begin{array}{c}\left(N_L-1\right)/2\end{array}$	Need
[13]	$\begin{array}{l}2\left(N_L+1\right)+4\hfill \end{array}$	$2N_L$	$2N_L+6$	$(\begin{array}{l}{N}_L-1\hfill \end{array})/2$	No Need
[15]	$\begin{array}{l}3N_L+4\hfill \end{array}$	0	$\begin{array}{l}3N_L+4\hfill \end{array}$	$(\begin{array}{l}{N}_L-1\hfill \end{array})/2$	No Need
[16]	$2N_L+4$	$\begin{array}{l}{N}_L\hfill \end{array}$	$2N_L+4$	$(\begin{array}{l}{N}_L-1\hfill \end{array})/2$	No Need
[17]	$3N_L-1$	$\begin{array}{l}{N}_L\hfill \end{array}$	$3N_L-1$	$(\begin{array}{l}{N}_L-1\hfill \end{array})/2$	No Need
[18]	$\begin{array}{l}{N}_L+5\hfill \end{array}$	$\begin{array}{l}2N_L\hfill \end{array}$	$\begin{array}{l}{N}_L+5\hfill \end{array}$	$(\begin{array}{l}{N}_L-1\hfill \end{array})/2$	No Need
[19]	$\begin{array}{l}2\left(N_L+1\right)+4\hfill \end{array}$	0	$\begin{array}{l}2\left(N_L+1\right)+4\hfill \end{array}$	$(N_L/2)$	Need

shows the number of switching devices (Active switches, series diode), drivers for the switches and capacitors versus number of levels (N_L) and number of stages for the proposed inverter (n_stage). Note that, as shown in Figure 8, the relation between the number of stages and the number of levels in the proposed converter is:

$$n_{stage}=\{\begin{array}{l}10\le N_L\le 19\\ 219\le N_L\le 91\\ 391\le N_L\le 253\end{array}$$

(19)

Figure 8 presents the number of capacitors and semiconductors (active switches + series diodes) for 0 to 100 levels output. This comparison shows that the proposed converter provides better performance in terms of the number of components. As the converter is for low voltage input voltage sources, multiples of this low voltage amount are still within the acceptable standard range of components.

9. The Simulation Results

A MATLAB simulation is conducted to achieve a 91-level output voltage with a maximum of 45 times of input DC voltage. The parameters given in

Table 5. Simulation parameters.

Parameter	Value
Input Voltage	50 Volts
Number of Output Voltage levels	91
Output Frequency	50 Hz
CM1, CM2	20,000 μF
CM3, CM5	1000 μF
CM4, CM6, CM7, CM8, CM9	100 μF
Resistive Load (R)	100 Ω
Inductive-Resistive Load (R-L)	100 Ω, 318.4 mH

are used for the analysis.

Figure 9a,b show the output voltage and current at 50 Hz for two types of resistive and resistive-inductive loads. As shown in these figures, a high level staircase output voltage is achieved. Discharging currents of the last stage capacitors are shown in Figure 9c,d. The converter and its control strategy are able to balance capacitor voltages within acceptable ranges with considered tolerances (see Figure 10a–c). FFT analysis of the output voltage is shown in Figure 11, which indicates good performance of the proposed topology because of its low harmonic distortion.

10. Experimental Results

To validate our simulation and analysis, an experimental test setup was built with an input voltage of 10 volts, as shown in Figure 12a; other components are shown at

Table 6. Experimental Parameters.

Input Voltage	10 v
Number of Output Voltage levels	91
Output Frequency	50 HZ
CM1, CM2	20,000 μF
CM3, CM5	1000 μF
CM4, CM6, CM7, CM8, CM9	100 μF
Load	570 Ω
Diode	MUR860
IGBT	12n60a4
Driver	HCPL 3120
Processor	DSP TMS320F28335

. Figure 12b shows the output voltage and current for a pure inductive load, which confirms the application of the proposed structure and its mentioned control strategy under different operating conditions.

Figure 13a–d shows the voltages and currents of selected capacitors (C_M1, C_M2, C_M3, C_M7) over a 2.5 ms period. It is clear that the number of charges and discharges for the capacitors in the first stage is much higher than that in last stages.

11. Conclusions

An asymmetrical step-up multilevel inverter is presented in this paper with a single DC source. Bidirectional modules are designed in order to create different paths for the capacitors to be charged or discharged, based on a predetermined pattern. A comprehensive mathematical analysis is conducted to achieve capacitance values and the voltage of each capacitor during the different states. Investigation of a three-stage proposed converter showed that 45 levels can be achieved using different switching states. The application of a full bridge single phase inverter at the end of the proposed converter gives 91 voltage levels (45 positive, 45 negative and one zero level). According to a detailed comparison with other classical and state-of-the-art topologies, the number of different components was reduced to a great extent. A comprehensive simulation study and experimental results are presented to verify the analysis.