# A Space Vector Based Zero Common-Mode Voltage Modulation Method for a Modular Multilevel Converter

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

_{dc}/3N in normal and asymmetric operation of the grid-connected MMC by adjusting the pulse duration to alternate consecutive inputs of sub-modules. The paper [15] uses a chaotic carrier phase-shifting strategy to reduce EMI by dispersing the harmonic energy at the switching frequency and its multiples over a wider frequency range, and the author proposes a pulse compliance adjustment method to make the output pulse continuous and keep the CMV always zero [16]. In the paper [17], it is based on the NLM and combined with the space vector method. When the CMV is not 0, it can be maintained at 0 by calculating the positions of the eight alternative proximity vectors and using the switching state of the nearest vector to replace the original switching state. However, due to the characteristics of NLM applications of the NLM, it is only applicable in the case of number of SMs. To solve CMV problems, this paper proposes a method for MMC under five-level SVPWM by selecting the fundamental voltage vector that does not generate CMV as the synthesized vector. The method can theoretically eliminate the common-mode voltage completely, and the method is experimentally studied and analyzed on the RT-LAB-based rapid prototyping platform to verify the feasibility and effectiveness.

## 2. MMC Mathematical Model and Control Strategy

#### 2.1. MMC Topology

_{m}. The three phases of the MMC are connected in parallel to the DC bus V

_{dc}as the input, and the AC output of each phase is drawn from the midpoint between the upper and lower bridge arm inductors. v

_{xp}and v

_{xn}denote the upper and lower bridge arm voltages of phase x (x = a, b, c), respectively; i

_{xp}and i

_{xn}denote the upper and lower bridge arm currents of phase x, respectively; v

_{cxp,ni}denotes the capacitance voltage value of the ith SM of the upper and lower bridge arms of phase x; N and O denote the MMC load-side and DC-side neutral points.

_{1}and T

_{2}, with capacitor C as the voltage storage element of the SM, connected in parallel with the two IGBTs. D

_{1}and D

_{2}are the anti-parallel diodes of IGBTs, respectively, which ensure uninterrupted current when the current is reversed. The output terminals of SM are connected to the external circuit, and it can output two voltages, including 0 or v

_{c}. The HBSM has three operating states: input, removal, and blocking, and it often stands in the operating states of input or removal under normal operating conditions. The blocking state is applied to adjust the system’s operation only when the MMC is in fault conditions such as over-current, over-voltage, or specific control methods. As shown in Figure 1, specify the bridge arm current i

_{xp,n}in the positive direction. Table 1 shows the operating state of the SM, “0” means the IGBT is turned off, and “1” means the IGBT is turned on. The output voltage is the capacitance voltage v

_{c}of SM when it is in the input state. When the arm current is going in a positive direction, the capacitor of the SM is in a charging state, and when it is going in the opposite direction, the capacitor of the SM is in a discharging state. During the MMC operation, each arm can input 0–4 SMs, corresponding to the arm voltage output from 0 to 4v

_{c}with 5 levels.

#### 2.2. MMC Mathematical Model

_{c}and a controllable switch S

_{i}, where S

_{i}= 1 means that the ith SM of the arm is in the input state and S

_{i}= 0 means that the ith SM of the arm is in the removal state. Without considering the effect of circuit equivalent resistance, the Kirchhoff‘s voltage law equation and the Kirchhoff’s current law equation of phase a are listed:

#### 2.3. CMV Mathematical Model

_{cmv}between the neutral point of the DC side and the neutral point of the load side, which is equal to the sum of the three phase output phase voltages.

_{cmv}is proportional to the difference between the sum of the number of input-SMs of the three-phase upper and lower bridges, denoted as N

_{diff}. It is determined by the switching state generated by the modulation algorithm, which varies at a three times higher frequency than the single-phase switching frequency. When the number of SMs is low, the coefficient V

_{dc}/6N in Equation (11) will account for a large proportion of the phase voltage, so an excessive v

_{cmv}will increase the insulation requirements of the system and increase the system design cost. When the number of SMs N is high, the CMV of high-frequency jumping will have an influence on the equivalent conductance of the device to ground, and the larger common-mode current will affect the system life.

## 3. Suppression Strategy of CMV Based on Zero CMV Vector Selection

#### 3.1. Analysis of Conventional Five-Level SVPWM CMV

_{p}and SVPWM

_{n}with two reference vector angles that differ from each other by π. The MMC three-phase bridge arm voltage reference wave is as follows:

_{0}is the initial phase angle, ω

_{0}is the fundamental electric angular velocity, and m is the modulation index.

_{max}is the equivalent output phase voltage amplitude and V

_{dc}is the DC side voltage amplitude. The SVPWM linear modulation region is 0 ≤ m ≤ 3/2.

_{diff}has thirteen levels: 0, ±2, ±4, ±6, ±8, ±10, and ±12. If all input states are involved in SVPWM, there are 13 amplitude levels of CMV, where the minimum is 0 and the maximum is V

_{dc}/2. The number of CMV amplitudes is shown in Table 2.

#### 3.2. Conventional Five-Level SVPWM

**V**

_{a},

**V**

_{b},

**V**

_{c}) in the three-phase stationary coordinate system are converted to the α-β coordinate system by Park transformation to obtain the coordinates (

**V**

_{α},

**V**

_{β}). The transformation from α-β to g-h coordinate system is then performed, as shown in Figure 4. Equation (13) gives the transformation equation from the a-b-c coordinate system to the g-h coordinate system.

**V**

_{α},

**V**

_{β}) transformed by Equation (12) are normalized. The vector of the longest edge in the regular hexagon of SVPWM in the a-b-c coordinate system is (1, −0.5, −0.5), and the modulus of this vector, |V

_{max}|

_{(abc)}is 1.5. The coordinates of this vector in the g-h coordinate system are (3$\sqrt{2}$/2$\sqrt{3}$,0), and the modulus of this vector in the g-h coordinate system, |V

_{max}|

_{(g-h)}is 3$\sqrt{2}$/2$\sqrt{3}$. Since the hexagonal vector with five levels has four layers, so that the maximum coordinate is 4, the scalar transformation Equation (14) is obtained in order to make the maximum vector lengths equal in the a-b-c and g-h coordinate systems:

_{diff}in the redundant vector is selected as the synthesis vector. The input state of the synthesis vector is marked in red in Figure 3. It is firstly judged that the small sector in which the reference voltage vector

**V**

_{ref}is converted to sector I is in every sampling period T

_{s}. The synthesis vector of this small sector is used to synthesize based on the volt-second balance principle. Then the time of action of each synthetic vector is calculated according to Equation (16):

**V**

_{x},

**V**

_{y}, and

**V**

_{z}are the synthesis vectors corresponding to the small sectors, and T

_{x}, T

_{y}, and T

_{z}are the action times of each vector. In order to reduce the switching frequency of SVPWM, a five-segment allocation of the synthesis vector’s action time in each control period T

_{s}is adopted. The number of input SMs should be changed only in one phase when the input state is switched. The order of the synthesis vector action in sector I is shown in Figure 6.

#### 3.3. Zero Common Mode Voltage SVPWM (0CMV-SVPWM)

_{on,n}= N

_{on,p}= 6. Figure 5 depicts a proposed 0CMV-SVPWM vector synthesis strategy that employs 19 input states of zero CMV for reference vector synthesis (marked with blue). Sector I is redivided as shown in Figure 7, and the switching state coordinates and g-h coordinate system coordinates of the seven zero CMV voltage vectors are marked in the figure. The large sector is divided into six small sectors ①~⑥. The small sectors ①~④ and large sectors ⑤ and ⑥ have the same size and shape, respectively. The newly divided small sector range is larger than the traditional small sector range. The number of variations per phase input SMs for three synthetic vectors within a small sector is one. When the synthesis vector changes, the two phases of the SMs input-state change. With the purpose of minimizing the number of switches during SMs input state transitions, the switch state at the end of the previous control period is the same as the switch state at the beginning of the new control period. The three synthesis vectors of the small sector in which

**V**

_{ref}is located are

**V**

_{x},

**V**

_{y}, and

**V**

_{z}, and the five-segment switching sequence is used for reference voltage vector synthesis. The order of action of each fundamental voltage vector is

**V**

_{x}→

**V**

_{y}→

**V**

_{z}→

**V**

_{z}→

**V**

_{y}→

**V**

_{x}. The order of action of the synthesis vectors is shown in Table 3. The action time of the synthesis vector of 0CMV-SVPWM is calculated by Equation (14) and the calculated times are shown in Table 4. As shown in Figure 8, the five-segment synthetic time allocation is adopted for sector ②, and the total number of input-SMs of the bridge arm at any time during a control period is six.

_{dc}/2. For the conventional SVPWM strategy, the longest edge of the vector hexagon has the value of 2V

_{dc}/3. Additionally, the maximum value of the linear modulation region is Vdc/3 in this case, with a DC voltage utilization of about 1.15. The linear modulation area of 0CMV-SVPWM is reduced because only 19 fundamental vectors are used for synthesis. In this situation, the maximum value of the linear modulation region is V

_{dc}/2, thus the DC voltage utilization is one, which is reduced by 13%. The 0CMV-SVPWM strategy sacrifices a certain amount of DC voltage utilization for the elimination of the CMV.

#### 3.4. The Algorithm of MMC Capacitor Voltage Balancing

_{onp,nx}for each bridge arm of the three phases through SVPWM modulation of two bridge arms. The different input times of the SMs cause imbalances in charging and discharging. It is necessary to adopt the appropriate capacitance voltage balancing algorithm so that the SM’s capacitance voltage is kept near the rated value of V

_{dc}/4 during the operation of the MMC. Currently, the two most widely used balancing algorithms are the closed-loop capacitor voltage balancing algorithm based on PWM and the capacitor voltage sorting balancing algorithm. Because the sorting algorithm has easy implementation, good flexibility, and adaptability in the modulation strategy, it is adopted in this paper as the capacitor voltage balancing algorithm. At every control period T

_{s}, the capacitance voltage values of each sub-module are sampled and sorted. First, if the bridge arm current direction is positive, the SM with the lower capacitance voltage is selected in sequence and put into priority to charge it and increase the capacitance voltage value. Second, if the bridge arm current direction is opposite, the SM with the larger capacitance voltage is selected in sequence and put into priority to discharge it and decrease the capacitance voltage value. The sorting algorithm is shown in Figure 9. To reduce the times of switches, if the number of input-SMs at sampling period T

_{s}is identical to the last sampling period, the state of input-SMs from the previous control period is maintained.

## 4. Experimental Verification and Analysis

^{®}is used as the control circuit, and the PEH2015 of Imperix

^{®}Switzerland is used as the SM to construct a five-level MMC experimental system so as to verify the effectiveness and feasibility of the 0CMV-SVPWM proposed in this paper. Table 5 shows the experimental parameters. In this paper, the modulation index is defined as the ratio of the three-phase synthesis vector to the maximum value of the vector hexagon (3V

_{dc}/2). The modulation index is set to 0.3~0.85 for the following reasons. On the one hand, when the modulation index is less than 0.5, the N = 4 MMC output has only three levels, with 0 and ±V

_{dc}/4 for each phase, which is a three-level output state. In order to better analyze the output characteristics and CMV over a wide range of modulation indices in the experimental verification, experimental data were recorded every 0.5 modulation index from m = 0.3 to 0.85. On the other hand, for the conventional SVPWM strategy, the modulation index m < 0.866 is the linear modulation region. When the modulation index is higher than the value, it is in the over-modulation region, and the quality of the output waveform will be degraded because the complete voltage vector circle cannot be synthesized. Therefore, the maximum value of the modulation index is set to 0.85 in the experiment.

_{a}, phase current i

_{a}, SM capacitance voltage v

_{c}, and CMV of under the conventional SVPWM and 0CMV-SVPWM with the modulation system m = 0.4, 0.6, and 0.8, respectively.

#### 4.1. Analysis of Common Mode Voltage

_{dead}set for the experimental system to prevent the two IGBTs of the SM from operating at the same time. The dead time is shown in Figure 13 for delayed turn-on and normal turn-off. In essence, the dead time increases by 4 μs of blocking state duration, causing failure to strictly satisfy MMC operating conditions, and it is an inevitable hardware problem. In order to better compare the effect of dead time on the experimental system, as shown in Figure 14, the waveforms of the CMV for the modulation index m = 0.4, 0.6, and 0.8, are shown where the dead time of the system is ignored and the simulation parameters are identical to the experimental parameters. As can be seen from the figure, the CMV is significantly reduced by about 90% with 0CMV-SVPWM, without generating CMV spikes. Therefore, under the ideal condition without considering the dead time, 0CMV-SVPWM can suppress the CMV of MMC to basically zero. If the CMV spike voltage is ignored in the experiment, the CMV amplitudes of 0CMV-SVPWM are approximately 2.95 V, 3.24 V, and 3.46 V, respectively. Compared with traditional SVPWM, it reduces about 82%, so the CMV suppression strategy is effective.

#### 4.2. Analysis of SM’s Capacitor Voltage

_{dc}/4, so that the CMV can theoretically be completely suppressed when six SMs are put into operation in the upper and lower bridge arms of all three phases. However, the fluctuation of the capacitor voltage still exists after taking the use of the sorting algorithm into account, causing a fluctuation value of about 3 V in the CMV.

#### 4.3. Output Quality and Operational State Analysis

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

- Marquardt, R. A new modular voltage source inverter topology. In Proceedings of the European Power Electronics Conference, Toulous, Frarance, 2–4 September 2003. [Google Scholar]
- Martinez-Rodrigo, F.; Ramirez, D.; Rey-Boue, A.B.; De Pablo, S.; Herrero-de Lucas, L.C. Modular Multilevel Converters: Control and Applications. Energies
**2017**, 10, 1709. [Google Scholar] [CrossRef] [Green Version] - Wang, J.; Xu, X.; Pan, W.; Xu, S. Impedance Modeling and Analysis of Series-Connected Modular Multilevel Converter (MMC) and its Comparative Study With Conventional MMC for HVDC Applications. IEEE Trans. Power Deliv.
**2022**, 37, 3270–3281. [Google Scholar] [CrossRef] - Teng, J.X.; Sun, X.F.; Zhang, Y.R. Two Types of Common-Mode Voltage Suppression in Medium Voltage Motor Speed Regulation System Based on Solid State Transformer With Dual DC Bus. IEEE Trans. Power Electron.
**2022**, 37, 7082–7099. [Google Scholar] [CrossRef] - Seo, I.K.; Belaynehn, N.B.; Park, C.H. A study of common mode voltage generation according to modulation methods and reduction strategies on MMC system. IEEE Energy Convers. Congr. Expo.
**2018**, 23, 3988–3995. [Google Scholar] - Sun, T.; Pei, X.; Shan, Y. Submodule Switching-State Based EMI Modeling and Mixed-Mode EMI Phenomenon in MMC. IEEE Trans. Power Electron.
**2022**, 38, 1831–1843. [Google Scholar] [CrossRef] - Liang, G. Predictive Analysis for Radiated Electromagnetic Disturbance in MMC-HVDC Valve Hall. CPSS Trans. Power Electron. Appl.
**2020**, 5, 126–134. [Google Scholar] [CrossRef] - Ji, S.; Palmer, J.; Huang, X. Impact of submodule voltage sensor noise in 10 kV SiC MOSFET modular multilevel converters (MMCs) under high dv/dt environment. In Proceedings of the IEEE Applied Power Electronics Conference and Exposition, New Orleans, LA, USA, 15–19 March 2020; pp. 1089–1093. [Google Scholar]
- Gryzlov, A.A.; Grigor’Ev, M.A. Improving the Reliability of Relay-Protection and Automatic Systems of Electric-Power Stations and Substations. Russ. Electr. Eng.
**2018**, 89, 245–248. [Google Scholar] [CrossRef] - Zhou, Y.; Nian, H. Current Zero-Crossing Duration Reduction of a Semicontrolled Open-Winding PMSG System Based on Third Harmonic Current Injection. IEEE Trans. Ind. Electron.
**2016**, 63, 750–760. [Google Scholar] [CrossRef] - Karampuri, R.; Jain, S.; Somasekhar, V.T. Sample-averaged zero-sequence current elimination PWM technique for five-phase induction motor with opened stator windings. IEEE J. Emerg. Sel. Top. Power Electron.
**2017**, 6, 864–873. [Google Scholar] [CrossRef] - Hota, A.; Jain, S.; Agarwal, V. A Modified T-Structured Three-Level Inverter Configuration Optimized With Respect to PWM Strategy Used for Common-Mode Voltage Elimination. IEEE Trans. Ind. Appl.
**2017**, 53, 4779–4787. [Google Scholar] [CrossRef] - Li, X.; Xing, X.; Zhang, C. Simultaneous common-mode resonance circulating current and leakage current suppression for transformerless three-level T-type PV inverter system. IEEE Trans. Ind. Electron.
**2018**, 66, 4457–4467. [Google Scholar] [CrossRef] - Du, S.; Wu, B.; Zargari, N. Common-mode voltage minimization for grid-tied modular multilevel converter. IEEE Trans. Ind. Electron.
**2018**, 66, 7480–7487. [Google Scholar] [CrossRef] - Wang, J.; Li, H.; Yang, Z. Common-Mode Voltage Reduction of Modular Multilevel Converter Based on Chaotic Carrier Phase Shifted Sinusoidal Pulse Width Modulation. In Proceedings of the IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity, Reno, NV, USA, 28 July–28 August 2020; pp. 626–631. [Google Scholar]
- Wang, J.; Li, H.; Wang, Z. A Novel Common-Mode Voltage Reduction Method of MMC: Pulse Sequential Connection Carrier Phase-Shifted SPWM. In Proceedings of the IEEE International Joint EMC/SI/PI and EMC Europe Symposium, Raleigh, NC, USA, 26 July–13 August 2021; pp. 89–93. [Google Scholar]
- Chen, J.; Jiang, D.; Sun, W.; Pei, X. Common-Mode Voltage Reduction Scheme for MMC With Low Switching Frequency in AC–DC Power Conversion System. IEEE Trans. Ind. Inform.
**2022**, 18, 278–287. [Google Scholar] [CrossRef]

**Figure 15.**Output characteristics under different modulation index: (

**a**) THD of output current (

**b**) Output efficiency.

State | T_{1} | T_{2} | Arm Current Direction | Output Voltage | Capacitance State |
---|---|---|---|---|---|

input | 1 | 0 | + | v_{c} | charge |

1 | 0 | − | v_{c} | discharge | |

removal | 0 | 1 | + | 0 | bypass |

0 | 1 | − | 0 | bypass | |

blocking | 0 | 0 | + | 0 | charge |

0 | 0 | − | 0 | bypass |

v_{cmv} | Number |
---|---|

0 | 19 |

±V_{dc}/12 | 36 |

±2V_{dc}/12 | 30 |

±3V_{dc}/12 | 20 |

±4V_{dc}/12 | 12 |

±5V_{dc}/12 | 6 |

±6V_{dc}/12 | 2 |

Sector | The Action Order of Synthetic Vector |
---|---|

① | 321-222-231-231-222-321 |

② | 321-222-312-312-222-321 |

③ | 321-312-411-411-312-321 |

④ | 321-231-330-330-231-321 |

⑤ | 321-411-420-420-411-321 |

⑥ | 321-330-420-420-330-321 |

n | T_{x} | T_{y} | T_{z} |
---|---|---|---|

① | (1/3V_{g}^{*} + 2/3V_{h}^{*})·T_{s} | (1 − 2/3V_{g}^{*} − 1/3V_{h}^{*})·T_{s} | (1/3V_{g}^{*} − 1/3V_{h}^{*})·T_{s} |

② | (2/3V_{g}^{*} + 1/3V_{h}^{*})·T_{s} | (1 − 1/3V_{g}^{*} − 2/3V_{h}^{*})·T_{s} | (−1/3V_{g}^{*} + 1/3V_{h}^{*})·T_{s} |

③ | (1 − 1/3V_{g}^{*} + 1/3V_{h}^{*})·T_{s} | (−1/3V_{g}^{*} − 2/3V_{h}^{*} + 1)·T_{s} | (2/3V_{g}^{*} + 1/3V_{h}^{*} − 1)·T_{s} |

④ | (1 + 1/3V_{g}^{*} − 1/3V_{h}^{*})·T_{s} | (−2/3V_{g}^{*} − 1/3V_{h}^{*} − 1)·T_{s} | (1/3V_{g}^{*} + 2/3V_{h}^{*} − 1)·T_{s} |

⑤ | (2 − 2/3V_{g}^{*} − 1/3V_{h}^{*})·T_{s} | (1/3V_{g}^{*} − 1/3V_{h}^{*})·T_{s} | (2/3V_{g}^{*} + 2/3V_{h}^{*} − 1)·T_{s} |

⑥ | (2 − 1/3V_{g}^{*} − 2/3V_{h}^{*})·T_{s} | (1/3V_{g}^{*} + 1/3V_{h}^{*})·T_{s} | (2/3V_{g}^{*} + 1/3V_{h}^{*} − 1)·T_{s} |

Parameters | Value |
---|---|

DC voltage/V_{dc} | 200 V |

Number of SMs/N | 4 |

SM’s capacitance/C | 5.04 mF |

Arm inductors/L_{m} | 5 mH |

Control period/T_{s} | 0.5 ms |

Fundamental frequency/f | 50 Hz |

Modulation index/m | 0.3~0.85 |

Load resistance/R | 5 Ω |

Load inductance/L | 9.45 mH |

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**MDPI and ACS Style**

Zhang, G.; Wang, S.; Li, C.; Li, X.; Gu, X.
A Space Vector Based Zero Common-Mode Voltage Modulation Method for a Modular Multilevel Converter. *World Electr. Veh. J.* **2023**, *14*, 53.
https://doi.org/10.3390/wevj14020053

**AMA Style**

Zhang G, Wang S, Li C, Li X, Gu X.
A Space Vector Based Zero Common-Mode Voltage Modulation Method for a Modular Multilevel Converter. *World Electric Vehicle Journal*. 2023; 14(2):53.
https://doi.org/10.3390/wevj14020053

**Chicago/Turabian Style**

Zhang, Guozheng, Shuo Wang, Chen Li, Xinmin Li, and Xin Gu.
2023. "A Space Vector Based Zero Common-Mode Voltage Modulation Method for a Modular Multilevel Converter" *World Electric Vehicle Journal* 14, no. 2: 53.
https://doi.org/10.3390/wevj14020053