Finite Control Set-Model Predictive Control (FCS-MPC) of a Modified 17-Level Flying-Capacitor Converter

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The paper presents a Finite Control Set Model Predictive Control strategy (FCS-MPC) for a modified eight-level flying-capacitor DC/AC converter intended for grid-connected operation. The proposed controller simultaneously addresses grid current tracking and flying-capacitor voltage balancing through a unified cost function. The authors also include a switching-frequency reduction term and a delay compensation strategy, which are relevant practical aspects for the digital implementation of FCS-MPC in multilevel converters. The study is validated through PSIM simulations and real-time HIL implementation using an FPGA-based platform, which strengthens the practical interest of the work. In my opinion, the topic is relevant for Algorithms, especially from the viewpoint of predictive control, optimization-based switching selection, and real-time implementation.

 The manuscript is technically interesting and generally well structured. The converter topology is described, the FCS-MPC formulation is presented, and the results show promising dynamic response, current tracking, capacitor voltage balancing, reactive power capability, and harmonic compensation potential. However after a careful reading I have some questions and comments to improve the scientific quality of the paper.

1. Please could you clarify more explicitly the main novelty of the paper compared with previous FCS-MPC approaches applied to flying-capacitor and multilevel converters?
   The manuscript states that the method reduces the evaluated switching states to 27 relevant states, integrates capacitor voltage balancing, adds a switching-frequency reduction term, and includes delay compensation. These are all useful features, but each of them has been addressed in different forms in the FCS-MPC literature. The authors should clearly explain what is really new in their formulation: the converter topology, the reduced switching-state selection, the specific cost function, the FPGA/HIL implementation, or the combination of these elements.

 

2. How have you selected the weighting factors ki​, kv ​, and λl, and how sensitive is the system performance to these values?
   The manuscript mentions that k_i​ and k_v ​ are initially set to unity, while λ_l is selected heuristically. Since these parameters directly affect current tracking, capacitor voltage balancing, switching frequency, and transient response, a sensitivity analysis would significantly strengthen the paper. The authors should show how performance changes when these parameters are varied.

 

3. Can the authors provide quantitative results for the average switching frequency with and without the switching-frequency reduction term?
   The switching penalty term is an important contribution of the paper, but the manuscript does not clearly quantify the actual reduction obtained. It would be useful to report the average switching frequency, switching transitions per cycle, or semiconductor switching events for different values of λl. This would make the practical benefit of the penalty term much clearer.

 

4. The authors should provide more details about the computational burden of the proposed FCS-MPC algorithm on the FPGA-based platform?
   The manuscript claims low computational burden and high sampling-frequency capability, but it would be helpful to report the actual execution time, resource utilization, number of evaluated states per sampling period, and available timing margin with respect to the sampling time of 11.25 µs. These details are especially important because real-time feasibility is one of the key points of the work.

 

5. How robust is the proposed controller under grid disturbances and parameter variations?
   The presented results are promising, but the tests appear to focus mainly on startup, load/current reference change, non-sinusoidal current tracking, and phase-shifted current operation. The authors should evaluate or at least discuss the behavior of the controller under grid voltage sag, frequency deviation, distorted grid voltage, filter inductance uncertainty, capacitor tolerance, and measurement noise.

 

6. Could the authors better justify the use of the Euler discretization method for the predictive model?
   The manuscript explains that Euler discretization is selected because of its simplicity and low computational cost, while acknowledging its stability and convergence limitations. Since prediction accuracy is critical in FCS-MPC, the authors should discuss whether the selected sampling time is sufficiently small to avoid significant discretization error, and whether a comparison with a higher-order method was considered.

 

7. Please clarify the practical impact of the delay compensation strategy?
   The manuscript includes delay compensation and indicates that it improves prediction accuracy, but its benefit is not isolated in the results. A comparison between FCS-MPC with and without delay compensation would be useful to show its effect on current tracking error, capacitor voltage ripple, and transient response.

 

8. The paper reports THD values below 4% for the injected current and below 14% for the converter output voltage. Could the authors provide a more complete harmonic analysis?
   The authors should specify how THD was calculated, over which time interval, and under which operating conditions. It would also be useful to include harmonic spectra for the grid current and output voltage, especially for the sinusoidal, reactive power, and non-sinusoidal reference cases.

 

9. You should compare the proposed FCS-MPC method with at least one conventional control approach, such as PI/PR control with PWM or a classical FCS-MPC without switching penalty?
   The current results show that the proposed method works, but they do not clearly demonstrate how much it improves over existing alternatives. A comparative study would help quantify the benefits in terms of current THD, capacitor voltage ripple, switching frequency, dynamic response, and computational cost.

 

10. Could the authors better distinguish between HIL validation and experimental validation using a physical converter prototype?
    The HIL results using two National Instruments cRIO-9067 systems are valuable, but they do not fully replace validation on a real power converter, where non-idealities such as dead time, semiconductor voltage drops, sensor noise, parasitic inductances, thermal effects, and switching delays become important. The paper should clearly state the current validation level and avoid overstating the experimental maturity of the approach.
11. Some notation is inconsistent or slightly confusing. For example, the grid current is sometimes written as i_G​, i_g​ (line 252), while the grid voltage appears as v_G, v_g (line 265). There are also minor language issues, such as “y” instead of “and” (line 145) in the explanation of the discretized equations. A careful proofreading would improve readability and professionalism. Could the authors carefully revise the notation and language consistency throughout the manuscript?

 

12. You should improve the presentation quality of some figures, tables, and captions
    Figures 6–12 are important because they support the main claims of the paper, but some axis labels, legends, and waveform descriptions are difficult to read. Figure 2 would also benefit from clearer labeling of the eight voltage levels. In Table 2, the notation should be checked carefully, particularly the reference to “Table II” (line 238)  while the table is numbered “Table 2.” Improving figure resolution, caption detail, and cross-reference consistency would make the manuscript much easier to follow.

Comments on the Quality of English Language

The English language is generally understandable, but it should be improved to make the manuscript clearer and more professional. Some sentences are awkward or too long, and there are several minor grammatical and notation inconsistencies. For example, some technical terms and variables are not used consistently throughout the manuscript, and a few sentences would benefit from clearer wording. I recommend a careful proofreading by a fluent English speaker or professional editing service before publication.

Author Response

The paper presents a Finite Control Set Model Predictive Control strategy (FCS-MPC) for a modified eight-level flying-capacitor DC/AC converter intended for grid-connected operation. The proposed controller simultaneously addresses grid current tracking and flying-capacitor voltage balancing through a unified cost function. The authors also include a switching-frequency reduction term and a delay compensation strategy, which are relevant practical aspects for the digital implementation of FCS-MPC in multilevel converters. The study is validated through PSIM simulations and real-time HIL implementation using an FPGA-based platform, which strengthens the practical interest of the work. In my opinion, the topic is relevant for Algorithms, especially from the viewpoint of predictive control, optimization-based switching selection, and real-time implementation.

 The manuscript is technically interesting and generally well structured. The converter topology is described, the FCS-MPC formulation is presented, and the results show promising dynamic response, current tracking, capacitor voltage balancing, reactive power capability, and harmonic compensation potential. However after a careful reading I have some questions and comments to improve the scientific quality of the paper.

1. Please could you clarify more explicitly the main novelty of the paper compared with previous FCS-MPC approaches applied to flying-capacitor and multilevel converters?
   The manuscript states that the method reduces the evaluated switching states to 27 relevant states, integrates capacitor voltage balancing, adds a switching-frequency reduction term, and includes delay compensation. These are all useful features, but each of them has been addressed in different forms in the FCS-MPC literature. The authors should clearly explain what is really new in their formulation: the converter topology, the reduced switching-state selection, the specific cost function, the FPGA/HIL implementation, or the combination of these elements.

Response:

Thank you for this valuable comment. We agree that several of the individual elements included in the proposed FCS-MPC strategy, such as capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA/HIL validation, have been previously reported in the literature.

The main novelty of this work does not lie in any of these elements considered separately. Instead, the contribution is the development and validation of an integrated FCS-MPC framework specifically tailored for the proposed modified eight-level DFCM flying-capacitor

“While capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA implementation have been individually reported in previous FCS-MPC studies, the novelty of this work lies in their integration into a unified predictive control framework specifically designed for a modified eight-level DFCM flying-capacitor converter. This integrated approach enables simultaneous current regulation, capacitor balancing, reduced computational burden, and real-time implementation feasibility.”

This information can be found in the abstract, lines 76, 93, and 211 of the new manuscript.

1. How have you selected the weighting factors ki​, kv ​, and λl, and how sensitive is the system performance to these values?
   The manuscript mentions that k_i​ and k_v ​ are initially set to unity, while λ_l is selected heuristically. Since these parameters directly affect current tracking, capacitor voltage balancing, switching frequency, and transient response, a sensitivity analysis would significantly strengthen the paper. The authors should show how performance changes when these parameters are varied.

Response:

Thank you for this valuable comment. λl does not directly influence error calculation as ki and kv do. When the mode of operation of the inverter is selected, the current state of the switches is analyzed to determine which combination of switches for the desired output requires the least changes to apply. Hence the fact that the value of λl is heuristically selected.

On the other hand, ki and kv directly influence the calculation of the error, but during the simulation phase it was observed that with the unit value the system works well.

Now, in the new manuscript you can see in Figures 6,12 & 13 and lines 254 to 285, 336 to 356 some analyses carried out varying these values and their influence.

1. Can the authors provide quantitative results for the average switching frequency with and without the switching-frequency reduction term?
   The switching penalty term is an important contribution of the paper, but the manuscript does not clearly quantify the actual reduction obtained. It would be useful to report the average switching frequency, switching transitions per cycle, or semiconductor switching events for different values of λl. This would make the practical benefit of the penalty term much clearer.

Response:

The authors thank the reviewer for this valuable comment. Simulation tests were carried out with a duration of 1 second in order to validate the correct functioning of the commutation reduction term implemented in the control scheme. This window of time allowed for the evaluation of transient and stationary system behavior, ensuring that switching strategies were not only effective at short intervals, but also sustained over a longer period of operation.

See Table 3, Figure 12 and line 329 of the new manuscript.

1. The authors should provide more details about the computational burden of the proposed FCS-MPC algorithm on the FPGA-based platform?
   The manuscript claims low computational burden and high sampling-frequency capability, but it would be helpful to report the actual execution time, resource utilization, number of evaluated states per sampling period, and available timing margin with respect to the sampling time of 11.25 µs. These details are especially important because real-time feasibility is one of the key points of the work.

Response:

The authors thank the reviewer for this valuable suggestion. In the revised manuscript, a paragraph in section 4.2 has been added, you can see line 398 and Table 5.

1. How robust is the proposed controller under grid disturbances and parameter variations?
   The presented results are promising, but the tests appear to focus mainly on startup, load/current reference change, non-sinusoidal current tracking, and phase-shifted current operation. The authors should evaluate or at least discuss the behavior of the controller under grid voltage sag, frequency deviation, distorted grid voltage, filter inductance uncertainty, capacitor tolerance, and measurement noise.

Response:

The authors thank the reviewer for this valuable suggestion. The system was subjected to different operating conditions in order to evaluate and validate its robustness against variations in its working environment and possible disturbances. These tests included changes in the current references, changes in the network voltage, modifications in the load conditions and the introduction of failure scenarios representative of critical situations such as internal imbalances in the energy storage elements.

In line 346 and Figures 14-16 of the new manuscript present the response of the control system to an extreme operating condition.

6. Could the authors better justify the use of the Euler discretization method for the predictive model?
   The manuscript explains that Euler discretization is selected because of its simplicity and low computational cost, while acknowledging its stability and convergence limitations. Since prediction accuracy is critical in FCS-MPC, the authors should discuss whether the selected sampling time is sufficiently small to avoid significant discretization error, and whether a comparison with a higher-order method was considered.

Response:

The authors thank the reviewer for this valuable suggestion. In the revised manuscript, a paragraph was added in Section 2 in line 138 to justify the selection of the Euler discretization method. The choice is based on the fact that the filter time constant, defined as Li/Ri, is significantly larger than the sampling period Ts. Under this condition, the discretization error introduced by Euler’s approximation remains negligible, provided that a sufficiently small sampling step is used. Furthermore, while higher-order methods such as the fourth-order Runge–Kutta could in principle reduce the local error, their implementation on FPGA platforms requires considerably more computational resources. Therefore, the Euler method offers an adequate balance between numerical accuracy and hardware efficiency for the predictive model considered.

1. Please clarify the practical impact of the delay compensation strategy?
   The manuscript includes delay compensation and indicates that it improves prediction accuracy, but its benefit is not isolated in the results. A comparison between FCS-MPC with and without delay compensation would be useful to show its effect on current tracking error, capacitor voltage ripple, and transient response.

Response:

Thank you for this valuable comment. Currently, the work is in the construction stage of the experimental prototype, so there are still no experimental data available to quantify the effect of delay compensation on the control system.

1. The paper reports THD values below 4% for the injected current and below 14% for the converter output voltage. Could the authors provide a more complete harmonic analysis?
   The authors should specify how THD was calculated, over which time interval, and under which operating conditions. It would also be useful to include harmonic spectra for the grid current and output voltage, especially for the sinusoidal, reactive power, and non-sinusoidal reference cases.

Response:

The authors thank the reviewer for this valuable suggestion. The PSIM software provides several tools for signal analysis in power electronics systems, including total harmonic distortion (THD) assessment. This functionality allows quantifying the harmonic content present in an electrical signal, comparing the magnitude of the harmonics with respect to the fundamental component. In the new manuscript, more information was added in section 4, line 346, Figures 13-16, about the tests of the system under different operating conditions and that the current is so affected by these changes.

 

1. You should compare the proposed FCS-MPC method with at least one conventional control approach, such as PI/PR control with PWM or a classical FCS-MPC without switching penalty?
   The current results show that the proposed method works, but they do not clearly demonstrate how much it improves over existing alternatives. A comparative study would help quantify the benefits in terms of current THD, capacitor voltage ripple, switching frequency, dynamic response, and computational cost.

 Response:

The authors thank the reviewer for this valuable suggestion. Because the converter topology used in this work is not widely distributed and does not correspond to more conventional structures within the specialized literature, there is no extensive set of previous studies or experimental results that directly compare their performance under different control strategies. This limits the availability of references that assess the system’s performance against alternative control methodologies under equivalent conditions.

For this reason, it proposes as a future work the implementation of other control strategies, with the aim of establishing a quantitative and qualitative comparison between different approaches. This comparison will allow a more complete evaluation of the current controller’s advantages and limitations, as well as identify possible improvements in the overall performance of the converter

1. Could the authors better distinguish between HIL validation and experimental validation using a physical converter prototype?
   The HIL results using two National Instruments cRIO-9067 systems are valuable, but they do not fully replace validation on a real power converter, where non-idealities such as dead time, semiconductor voltage drops, sensor noise, parasitic inductances, thermal effects, and switching delays become important. The paper should clearly state the current validation level and avoid overstating the experimental maturity of the approach.

Response:

Thank you for this valuable comment. Currently, the work is in the construction stage of the experimental prototype, so there are still no experimental data available.

1. Some notation is inconsistent or slightly confusing. For example, the grid current is sometimes written as i_G​, i_g​ (line 252), while the grid voltage appears as v_G, v_g (line 265). There are also minor language issues, such as “y” instead of “and” (line 145) in the explanation of the discretized equations. A careful proofreading would improve readability and professionalism. Could the authors carefully revise the notation and language consistency throughout the manuscript?

Response:

Thank you for this valuable comment.  Corrections were made.

1. You should improve the presentation quality of some figures, tables, and captions
   Figures 6–12 are important because they support the main claims of the paper, but some axis labels, legends, and waveform descriptions are difficult to read. Figure 2 would also benefit from clearer labeling of the eight voltage levels. In Table 2, the notation should be checked carefully, particularly the reference to “Table II” (line 238)  while the table is numbered “Table 2.” Improving figure resolution, caption detail, and cross-reference consistency would make the manuscript much easier to follow.

Response:

Thank you for this valuable comment.  Corrections were made.

 

Author Response File: Author Response.docx

Reviewer 2 Report

Comments and Suggestions for Authors

Please find the attached file with the associated comments and suggestions for consideration.

Comments for author File: Comments.pdf

Author Response

Reviewer 2

1. What is the primary novelty of this work: the proposed converter topology or the control strategy? This aspect should be clearly stated throughout the manuscript.

Response:

Thank you for this valuable comment. We agree that several of the individual elements included in the proposed FCS-MPC strategy, such as capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA/HIL validation, have been previously reported in the literature.

The main novelty of this work does not lie in any of these elements considered separately. Instead, the contribution is the development and validation of an integrated FCS-MPC framework specifically tailored for the proposed modified eight-level DFCM flying-capacitor

“While capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA implementation have been individually reported in previous FCS-MPC studies, the novelty of this work lies in their integration into a unified predictive control framework specifically designed for a modified eight-level DFCM flying-capacitor converter. This integrated approach enables simultaneous current regulation, capacitor balancing, reduced computational burden, and real-time implementation feasibility.”

This information can be found in the abstract, lines 76, 93 and 211 of the new manuscript.

2. In Lines 70–71, the manuscript states that an FCS-MPC strategy is developed. However, FCS-MPC is an established control technique and does not appear to constitute a novel contribution. Please clarify the actual novelty and contribution of the control method.

Response:

Thank you for this valuable comment. The answer is provided in question 1.

3. The discussion in Lines 70–90 requires substantial revision. Several points listed as contributions appear to describe the research methodology or implementation process rather than the actual scientific contributions of the work. The authors must modify it.

Response:

The authors thank the reviewer for this valuable suggestion. It is true that we put a list as a way to describe the control, but emphasizing the answer of question 1, everything is included in the addition to the manuscript in line 93.

“While capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA implementation have been individually reported in previous FCS-MPC studies, the novelty of this work lies in their integration into a unified predictive control framework specifically designed for a modified eight-level DFCM flying-capacitor converter. This integrated approach enables simultaneous current regulation, capacitor balancing, reduced computational burden, and real-time implementation feasibility.”

4. In Line 47, the manuscript claims a reduced number of passive components. However, the proposed topology appears to employ a relatively high number of passive components. This claim isn’t justified.

Response:

The authors thank the reviewer for this valuable suggestion. This explanation refers specifically to the topology proposed in this work. As has been clarified in the abstract and in line 76 of the new version of the manuscript, the developed converter possesses the inherent ability to increase the output voltage level without requiring additional DC-DC conversion stages. This feature is achieved by the voltage-raising states integrated into the converter structure itself, which allow for higher voltage levels than those provided by the input source.

For this reason, when the reduction of components is mentioned, it refers to the elimination of external elevator converters as well as power and control elements associated with these stages.

 

5. There is an inconsistency regarding the number of output voltage levels. The manuscript refers to an 8-level topology (in title), whereas Figure 2 appears to show 9 levels and Figure 9 presents 11 levels. Please clarify and ensure consistency throughout the paper.

Response:

Thank you for the comment. When we refer to an 8-level output associated with the inverter, we refer to the topology’s ability to generate eight different voltage levels in the positive semicycle and eight different voltage levels in the negative semicycle, in addition to the zero level. Thus, considering the entire output waveform, the inverter is able to produce a total of 17 different voltage levels.

However, it is important to note that the availability of these levels does not necessarily imply that all of them are used simultaneously or continuously during the operation. The control algorithm selects the most appropriate switching states based on instantaneous operating conditions, regulatory objectives and constraints imposed to maintain system stability. As a consequence, some levels may be employed less frequently or even not used at certain time intervals, which explains why in some waveforms the 17 theoretical steps are not always clearly observed.

In order to clarify this aspect and avoid possible confusion, we have modified Figure 2 of the new manuscript version. The current figure presents a wider and more detailed display of the output signal, allowing for a clearer appreciation of the complete waveform and the topology’s ability to generate all 17 available voltage levels.

6. Lines 302–303 claim that the proposed converter possesses voltage-boosting capability. However, this feature has not been sufficiently demonstrated or quantified in the manuscript.

Response:

The authors thank the reviewer for this valuable suggestion. As noted in the previous commentary, one of the main advantages of the proposed topology is its ability to generate output voltage levels above the power supply value without requiring an additional DC-DC conversion step. This characteristic is achieved by exploiting the voltage-raising states inherent in the converter structure, which allows us to combine the contribution of the main source with the energy stored in the capacitors.

As shown in Figure 2, the output voltage of the inverter can reach values equivalent to the sum of the input voltage and the voltages present in the floating capacitors. In this way, the topology is able to provide a voltage raising effect using only the elements that are part of the converter’s own structure, thereby reducing the number of required components and avoiding additional losses associated with intermediate conversion stages.

For the operating conditions considered in simulations performed on PSIM and in Hardware-in-the-Loop (HIL) tests, capacitors are adjusted to specific voltage levels that allow a maximum output amplitude of approximately 320 V and a minimum output amplitude of 320 V. These values are higher than the input source voltage, which confirms the tensile-lifting capacity of the proposed topology.

7. The manuscript lacks adequate references related to Finite Control Set Model Predictive Control (FCS-MPC). Relevant and recent literature should be incorporated to strengthen the background and the selected control strategy.

Response:

Thank you for this valuable comment.  Corrections were made.

8. Is it appropriate to classify the proposed topology as a Flying Capacitor Converter (FCC)? Based on its circuit configuration, the topology appears to be more closely related to a single-DC-source cascaded H-bridge (CHB) or hybrid cascaded H-bridge inverter incorporating two floating capacitor cells. Explain how the proposed converter fundamentally differs from conventional flying-capacitor-based topologies. If the operating mechanism aligns more closely with a CHB or hybrid CHB structure, the converter classification and terminology should be revised accordingly.

Response:

Thank you for this valuable comment. It is correct that the proposed topology presents a visual structure similar to that of a cascade bridge-H inverter. However, the fundamental difference lies in the nature of the energy storage elements used. In conventional H-cascade bridge topologies (CHB, Cascaded H-Bridge), each cell requires an independent voltage source connected directly to its terminals, which allows multiple levels of voltage to be generated by adding those sources.

On the other hand, in the proposed topology there are no multiple independent sources. Instead, float capacitors are used, which by definition are capacitors whose terminals are not directly connected to a fixed reference point, such as earth or the negative terminal of a power supply. Instead, both terminals are connected to nodes whose potential can dynamically vary during the operation of the converter.

Because of this feature, the capacitors store energy and their voltage is regulated by the different switching states of the inverter, allowing to generate additional levels of voltage without requiring additional isolated sources. Therefore, although the physical arrangement of power devices may resemble a cascading H-bridge structure, the operating principle and nature of the energy elements employed correspond to a topology based on float capacitors.

Consequently, the classification of the proposed topology within the family of multi-level converters with float capacitors is appropriate, since the generation of additional voltage levels depends on the balance and utilization of the stored voltages in the float capacitors and not multiple independent voltage sources, as occurs in traditional cascade H-bridge inverters.

Optional suggestions for the authors to further strengthen the technical presentation of the control strategy (these may be incorporated)

1. The equivalent converter model presented in Equations (2) and (3) does not appear to incorporate switching-state considerations. A proper switching-function-based model or switching-state representation can be included to accurately describe the converter operation.
2. The design and formulation of the cost function can be better explained by providing the cost-function equation used for the proposed topology.

For suggestions A and B, the authors may refer to paper [A] as a useful reference for model development and cost-function formulation. However, these additions are optional and may be included at the author’s discretion.

Response:

The authors appreciate the suggestions and comments made.

Author Response File: Author Response.docx

Reviewer 3 Report

Comments and Suggestions for Authors

I have some major questions and suggestions prior to consider it.

1. Experimental validation on a physical prototype is necessary to verify capacitor-voltage balancing and current quality under non-ideal switching conditions beyond HIL results. I suggest to perform. 
2. What is the worst-case computation latency of the proposed FCS-MPC, and how much timing margin exists between controller execution and the sampling interval?
3. How sensitive is the predictive controller to parameter mismatches in flying-capacitor values, grid inductance, and DC-link voltage, and has robustness been quantitatively assessed? discuss in the manuscript as its most important for this study.
4. Can controller performance be demonstrated under severe grid disturbances (voltage sag, phase jump, frequency deviation, and harmonic pollution) while maintaining grid-code compliance?
5. Since switching-state reduction is employed, what is the quantitative impact on optimality, current THD, capacitor-voltage ripple, and transient response compared with full-state evaluation?
6. How does the proposed FCS-MPC compare with PWM-based MPC and conventional PI-based control in terms of current THD, settling time, switching frequency, and FPGA resource utilization? Discuss it elaborately. 
7. Has the stability and convergence behavior of the multi-objective cost function been analyzed under rapid active/reactive power reference variations and capacitor-voltage imbalance conditions?
8. I suggest to add key findings of the study in the abstract. Hence re-write.
9. Add future scope of the study. 

     

Author Response

Reviewer 3

I have some major questions and suggestions prior to consider it.

1. Experimental validation on a physical prototype is necessary to verify capacitor-voltage balancing and current quality under non-ideal switching conditions beyond HIL results. I suggest to perform. 

Response:

Thank you for this valuable comment. Currently, the work is in the construction stage of the experimental prototype, so there are still no experimental data available.

1. What is the worst-case computation latency of the proposed FCS-MPC, and how much timing margin exists between controller execution and the sampling interval?

Response:

The authors thank the reviewer for this valuable suggestion. The measured worst-case execution time for the evaluation of the 27 candidate states was 10.52 μs, which is well below the selected sampling period of 11.25 μs. This provides an available timing margin of approximately 7%, confirming the real-time feasibility of the implementation. For more information you can see section 4.2 in line 401 of new manuscript.

1. How sensitive is the predictive controller to parameter mismatches in flying-capacitor values, grid inductance, and DC-link voltage, and has robustness been quantitatively assessed? discuss in the manuscript as its most important for this study.

Response:

The authors thank the reviewer for this valuable suggestion. The system was subjected to different operating conditions in order to evaluate and validate its robustness against variations in its working environment and possible disturbances. These tests included changes in the current references, changes in the network voltage, modifications in the load conditions and the introduction of failure scenarios representative of critical situations such as internal imbalances in the energy storage elements.

In the line 346 and Figures 14-16 of the new manuscript present the response of the control system to an extreme operating condition.

1. Can controller performance be demonstrated under severe grid disturbances (voltage sag, phase jump, frequency deviation, and harmonic pollution) while maintaining grid-code compliance?

Response:

The authors thank the reviewer for this valuable suggestion. Adding to the answer of the previous question, it is necessary to ensure that the system always remains synchronized with the AC network. To achieve this, a second-order generalized integrator (SOGI) is employed. Figure 5 was redrawn.

1. Since switching-state reduction is employed, what is the quantitative impact on optimality, current THD, capacitor-voltage ripple, and transient response compared with full-state evaluation?

Response:

Thank you for this valuable comment. λl does not directly influence error calculation as ki and kv do. When the mode of operation of the inverter is selected, the current state of the switches is analyzed to determine which combination of switches for the desired output requires the least changes to apply. Hence the fact that the value of λ l is heuristically selected.

On the other hand, ki and kv directly influence the calculation of the error, but during the simulation phase it was observed that with the unit value the system works well.

Now, in the new manuscript you can see in Figures 6,12 & 13 and lines 254 to 285, 336 to 356 some analyses carried out varying these values and their influence.

1. How does the proposed FCS-MPC compare with PWM-based MPC and conventional PI-based control in terms of current THD, settling time, switching frequency, and FPGA resource utilization? Discuss it elaborately. 

Response:

The authors thank the reviewer for this valuable suggestion. Because the converter topology used in this work is not widely distributed and does not correspond to more conventional structures within the specialized literature. There is no extensive set of previous studies or experimental results that directly compare their performance under different control strategies. This limits the availability of references that assess the system’s performance against alternative control methodologies under equivalent conditions.

For this reason, it proposes as a future work the implementation of other control strategies, with the aim of establishing a quantitative and qualitative comparison between different approaches. This comparison will allow a more complete evaluation of the current controller’s advantages and limitations, as well as identifying possible improvements in the overall performance of the converter

1. Has the stability and convergence behavior of the multi-objective cost function been analyzed under rapid active/reactive power reference variations and capacitor-voltage imbalance conditions?

Response:

Thank you for this valuable comment. The answer is provided in question 3.

1. I suggest to add key findings of the study in the abstract. Hence re-write.

Response:

Thank you for this valuable comment.  Corrections were made.

1. Add future scope of the study. 

Response:

Thank you for this valuable comment.  Corrections were made.

 

Author Response File: Author Response.docx

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The authors have made a considerable effort to address the comments raised during the previous review round, and the manuscript has been substantially improved. The revised version now provides a clearer explanation of the main contribution of the work, additional analyses regarding the influence of the weighting factors, quantitative information on switching transitions, a better justification of the Euler discretization approach, and further details concerning the FPGA implementation and computational requirements.

The topic remains relevant and interesting, particularly for researchers working on predictive control, multilevel power converters, and real-time digital implementation. The proposed FCS-MPC strategy integrates several practical features, including current tracking, capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA-based implementation within a unified control framework. The simulation and HIL results generally demonstrate satisfactory dynamic performance and good current quality.

Despite these improvements, several aspects could still be strengthened before publication.

1. Although the novelty statement has been clarified, the manuscript would benefit from a more explicit discussion highlighting the practical advantages of the proposed approach compared with existing FCS-MPC implementations for flying-capacitor converters.

2. The sensitivity analysis of the weighting factors is a valuable addition. However, the manuscript would be stronger if a systematic tuning methodology were proposed instead of relying mainly on heuristic selection.

3. The switching reduction strategy is now quantified through commutation counts. Nevertheless, reporting the equivalent average switching frequency would provide a more direct assessment of the practical benefits for semiconductor devices.

4. The FPGA implementation details have been improved. It would still be useful to discuss scalability when the number of voltage levels or switching states increases.

5. Additional robustness tests have been incorporated. However, the manuscript still lacks an evaluation under parameter uncertainties, measurement noise, and distorted grid voltage conditions, which are common in practical applications.

6. The justification for using Euler discretization is now clearer and technically reasonable. Nevertheless, a brief quantitative estimate of the discretization error would further strengthen this discussion.

7. The delay compensation strategy remains insufficiently validated. Since it is presented as an important component of the controller, a comparison between operation with and without delay compensation would be valuable, even if performed only in simulation.

8. The harmonic analysis has been expanded through additional THD results. Including representative harmonic spectra of the grid current and converter output voltage would provide a more complete picture of the converter performance.

9. One of the main remaining weaknesses is the absence of a comparison with a baseline controller, such as a conventional FCS-MPC implementation or a PR/PI-based solution. Such a comparison would help quantify the actual benefits of the proposed strategy.

10. The manuscript should clearly distinguish between HIL validation and experimental validation using a physical converter prototype. Some statements could otherwise give the impression that full experimental validation has already been completed.

11. Several minor notation inconsistencies and grammatical issues have been corrected. However, a final careful proofreading by a fluent English speaker is still recommended.

12. The quality of most figures has improved. Nevertheless, some graphical elements and axis labels could still be enlarged to improve readability in the final published version.

Overall, the manuscript has significantly improved compared with the original submission and addresses most of the major concerns raised during the first review round. The remaining issues mainly concern additional validation and clarification rather than fundamental technical flaws. I therefore believe that the paper can be considered for publication after minor revision.

Comments on the Quality of English Language

The English language is generally understandable, but it should be improved to make the manuscript clearer and more professional. Some sentences are awkward or too long, and there are several minor grammatical and notation inconsistencies. For example, some technical terms and variables are not used consistently throughout the manuscript, and a few sentences would benefit from clearer wording. I recommend a careful proofreading by a fluent English speaker or professional editing service before publication.

Author Response

Reviewer 1

The authors have made a considerable effort to address the comments raised during the previous review round, and the manuscript has been substantially improved. The revised version now provides a clearer explanation of the main contribution of the work, additional analyses regarding the influence of the weighting factors, quantitative information on switching transitions, a better justification of the Euler discretization approach, and further details concerning the FPGA implementation and computational requirements.

The topic remains relevant and interesting, particularly for researchers working on predictive control, multilevel power converters, and real-time digital implementation. The proposed FCS-MPC strategy integrates several practical features, including current tracking, capacitor voltage balancing, switching-frequency reduction, delay compensation, and FPGA-based implementation within a unified control framework. The simulation and HIL results generally demonstrate satisfactory dynamic performance and good current quality.

Despite these improvements, several aspects could still be strengthened before publication.

1. Although the novelty statement has been clarified, the manuscript would benefit from a more explicit discussion highlighting the practical advantages of the proposed approach compared with existing FCS-MPC implementations for flying-capacitor converters.

Response:

The authors appreciate the observation. In Table 8 we present a small comparison between the original DFCM circuit controlled by predictive control, our proposal simulated by predictive control with complete response, and the final proposal using the FCS-MPC through Euler.

1. The sensitivity analysis of the weighting factors is a valuable addition. However, the manuscript would be stronger if a systematic tuning methodology were proposed instead of relying mainly on heuristic selection.

Response:

We appreciate your comment. As future work, it is proposed to incorporate optimization algorithms for their application to the proposed system, with the aim of improving the selection of parameters and the overall performance of control. You can see line 489 for more information.

1. The switching reduction strategy is now quantified through commutation counts. Nevertheless, reporting the equivalent average switching frequency would provide a more direct assessment of the practical benefits for semiconductor devices.

Response:

The authors thank you for your valuable comment. In Table 3, the corresponding switching frequency was added for each case analyzed. Considering a sampling time of 11.25 μs, the theoretical maximum switching frequency is 44.44 kHz (half of 88.88 kHz). Since a complete switching cycle requires two switch state changes (on and off).

Two additional columns were added showing the average frequency of switch switching, both for the conventional case and for the strategy that considers redundant states.

From the results obtained, it can be observed that the incorporation of the reduction of commutations not only decreases the total number of state changes, but also contributes to a more uniform distribution of the commutations between the different switches.

1. The FPGA implementation details have been improved. It would still be useful to discuss scalability when the number of voltage levels or switching states increases.

Response:

Thank you for your comment. The behavior of the system under different configurations of the number of voltage levels generated by the converter was evaluated. The objective was to analyze how this variation influences the computational load and, consequently, the execution time of the control algorithm. You can see this information in line 438 and table 7.

1. Additional robustness tests have been incorporated. However, the manuscript still lacks an evaluation under parameter uncertainties, measurement noise, and distorted grid voltage conditions, which are common in practical applications.

Response:

We appreciate your comment. In table 4, in addition to the evidence reported in figures 14,15 and 16, a new proof was added, when there is distortion present in the network, which can be seen in figure 17. As we currently lack a prototype, we do not have noise data in the measurement and its consequences.

1. The justification for using Euler discretization is now clearer and technically reasonable. Nevertheless, a brief quantitative estimate of the discretization error would further strengthen this discussion.

Response:

Thank you for your comment. As discussed in line 137, the Euler method was selected because it is one of the discretization methods that requires the lowest computational load for implementation, feature especially important in real-time predictive control applications and platforms with limited resources. Also, its mathematical simplicity allows reducing the calculation time associated with predicting system states, favoring execution within required sampling periods.

If a more detailed explanation is considered necessary, the reference [20] of the manuscript presents a comparison of different numerical methods used in HIL implementations. In this work, an analysis of both accuracy and computational cost is carried out, concluding that the Euler method offers the best relationship between performance and implementation complexity for this type of applications, which is why it was adopted in the proposal presented.

1. The delay compensation strategy remains insufficiently validated. Since it is presented as an important component of the controller, a comparison between operation with and without delay compensation would be valuable, even if performed only in simulation.

Response:

The authors appreciate your comment. It is understandable that favorable results are desired regarding this term, but given the nature of the behavior of the System in PSIM simulations and in the same HIL System, no appreciable difference is really seen, which can be reported, Once a prototype is available, the influence of this strategy must be validated.

1. The harmonic analysis has been expanded through additional THD results. Including representative harmonic spectra of the grid current and converter output voltage would provide a more complete picture of the converter performance.

Response:

The authors appreciate your comment. In response to his suggestion, Figures 17-21 and Table 5 were incorporated, which present the harmonic spectrum of the system for the different operating conditions described in Table 4.

1. One of the main remaining weaknesses is the absence of a comparison with a baseline controller, such as a conventional FCS-MPC implementation or a PR/PI-based solution. Such a comparison would help quantify the actual benefits of the proposed strategy.

Response:

The authors thank him for his observation. Although no results reports were found under other control strategies for this specific topology, we did have a small simulation comparison of the system by full response predictive control.  These comparisons make it possible to show more clearly the contribution of each modification in indicators such as monitoring error, switching frequency and computational load. You can see the information in tables 3 and 8, and line 438 of the new manuscript.

1. The manuscript should clearly distinguish between HIL validation and experimental validation using a physical converter prototype. Some statements could otherwise give the impression that full experimental validation has already been completed.

Response:

We appreciate your comment and regret the confusion caused. However, as indicated in the abstract and in Section 4 of the manuscript, the work presents only results obtained by simulation in PSIM software and HIL simulation. The objective of these tests is to evaluate and demonstrate the performance of the proposed control strategy applied to the converter under study. Experimental results with a physical prototype were not included, as the scope of this contribution focuses on validation using simulation and HIL environments.

1. Several minor notation inconsistencies and grammatical issues have been corrected. However, a final careful proofreading by a fluent English speaker is still recommended.

Response:

Thank you for your comment. It was reviewed as carefully as posible.

1. The quality of most figures has improved. Nevertheless, some graphical elements and axis labels could still be enlarged to improve readability in the final published version.

Response:

The authors thank you for your comment. The requested adjustments have been made.

Overall, the manuscript has significantly improved compared with the original submission and addresses most of the major concerns raised during the first review round. The remaining issues mainly concern additional validation and clarification rather than fundamental technical flaws. I therefore believe that the paper can be considered for publication after minor revision.

Response:

The authors hope that the answers to your interesting questions and comments have been satisfactorily addressed.

 

Reviewer 2 Report

Comments and Suggestions for Authors

1. The inverter level should not be named based only on the levels generated in a semi-cycle, as this is not the standard convention. The number of levels should be determined over one complete output cycle, including the zero-voltage level. Therefore, based on the authors’ own justification, the proposed inverter should be identified as a 17-level inverter and not an 8-level inverter. It is strongly recommended that the terminology be revised accordingly throughout the manuscript or justify your consideration.

Author Response

Reviewer 2

1. The inverter level should not be named based only on the levels generated in a semi-cycle, as this is not the standard convention. The number of levels should be determined over one complete output cycle, including the zero-voltage level. Therefore, based on the authors’ own justification, the proposed inverter should be identified as a 17-level inverter and not an 8-level inverter. It is strongly recommended that the terminology be revised accordingly throughout the manuscript or justify your consideration.

Response:

The authors thank you for your comment. The requested change have been made.

 

Reviewer 3 Report

Comments and Suggestions for Authors

I am satisfied with the responses provided, as all of my queries have been addressed appropriately.

Author Response

Reviewer 3

I am satisfied with the responses provided, as all of my queries have been addressed appropriately.

Response:

The authors thank you for your comment.

Round 3

Reviewer 2 Report

Comments and Suggestions for Authors

The captions for Tables 7 and 8 are the same. Please correct it.

Author Response

Comments to the authors:

The captions for Tables 7 and 8 are the same. Please correct it.

Response:

We appreciate the observation. The captions for Tables 7 and 8 have been revised to ensure they are distinct and accurately reflect the content of each table. Thank you for pointing this out.