Optimization of Electricity Consumption by Information Technology Devices in Accordance with Environmental, Social, Governance and Sustainable Development Principles
Abstract
1. Introduction
2. Materials and Methods
2.1. Sources and Search Strategy
(“energy consumption” OR “power management” OR “energy efficiency” OR “low-power” OR “sleep mode” OR “DVFS” OR “virtualization” OR “cooling”) AND (“IT devices” OR “computer” OR “data center” OR “IoT” OR “embedded systems” OR “smart city”) AND (“ESG” OR “sustainable development” OR “carbon footprint” OR “green IT”).
2.2. Eligibility Criteria and Analytical Boundaries
2.3. Data Extraction and Taxonomy Development
2.4. Illustrative Quantitative Analysis
2.5. Inclusion/Exclusion Criteria and Screening
2.6. Data Extraction and Synthesis
2.7. Evidence Synthesis and ESG Interpretation
2.8. Methodological Limitations
3. Literature Review
3.1. ESG Framework and Sustainability Drivers ESG Consists of Three Elements
3.2. Digital Infrastructure Energy Drivers: IT Expansion and Data Centers
3.3. IoT and AI in Smart City Energy Optimization
3.4. Measurement Tools and Monitoring Systems for Electricity Consumption in IT Devices
- Analog watt meters, so-called panel devices due to the fact that the measurement result is displayed on a black scale on a white board;
- Digital watt meters, a more modern type of meter characterized by better readability of readings thanks to LCD screens.
3.5. Methods for Measuring Energy Consumption by IT Devices
4. Results and Discussion
4.1. Digitization of Energy Consumption Management and Analytics-Driven Optimization
- Identifying anomalies and responding to them;
- Well-thought-out strategies for replacing equipment;
- Adjusting activity times;
- Using hardware and programmable techniques for reducing power consumption.
4.2. Methods for Reducing Energy Consumption in IT Devices in Accordance with ESG and Sustainable Development Principles
- The first concerns methods of development during the design of integrated circuits—methods at this stage primarily include the selection of hardware and architecture as well as design strategies.
- The second concerns techniques implemented during system operation.
4.3. Low-Energy Techniques at Design Time and During Operation
- Innovative power-limited modes:
- -
- These are operational modes in a chip or microcontroller that limit power consumption depending on activity.Examples:
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- Sleep Mode/Deep Sleep: Most parts of the chip are turned off; only essential circuits stay active;
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- Standby/Idle Mode: CPU is paused, but peripherals or memory may still operate.
- Intelligent analog peripherals:
- -
- Analog peripherals (like ADCs, DACs, comparators, etc.) can consume significant power if always active.
- -
- Intelligent design allows them to:
- ○
- Turn on/off automatically based on need.
- ○
- Operate in low-power sampling modes.
- ○
- Process signals efficiently without requiring the main CPU to run continuously.
- Clock gating:
- -
- Disabling the clock signal to sections of a digital circuit when they are not in use.
- -
- How it helps:
- ○
- Digital circuits only consume dynamic power when the clock toggles.
- ○
- If a module is idle, gating the clock stops switching, saving power.
- ○
- Example: Stop the clock to a UART module when not transmitting.
- Supply voltage scaling:
- -
- Power consumed by a digital circuit is as follows:where: C = capacitance switched per cycle; V = supply voltage; f = operating frequency.P = C⋅V2⋅f
- -
- Reducing V significantly reduces power consumption.
- -
- Combined with frequency scaling, this is called Dynamic Voltage and Frequency.Scaling (DVFS).Example:
- -
- ACPU running at lower performance can drop voltage from 1.2V to 0.9V to save energy.
4.4. Firmware- and Event-Driven Power Management in Standby-Dominated System
- Initialize GPIO ();—means initializing the port to trigger an interrupt when the voltage changes from low to high and vice versa.
- Enter Low-Power Mode();thanks to this function, the processor remains in power-saving mode and waits for an interrupt from the I/O port.
4.5. Circuit- and Architecture-Level Techniques for Reducing Dynamic Switching Power
4.6. Additional Circuit- and System-Level Techniques
4.7. Illustrative Device-Level Comparisons and Practical Implications
- Laptop off: P = 230 V × 0.024 A × 1 = 6 W.
- Laptop on during normal operation: P = 230 V × 0.150 A × 1 = 35 W.
- Anetwork of energy meters;
- SCADA/BMS systems;
- IoT data;
- An analytical platform.
4.8. Classification of Trends and Technologies for Energy Optimization
- Organizes the identification of research variables related to energy consumption;
- Supports the selection of metrics and experimental scenarios;
- Enables the unambiguous assignment of observed energy effects to specific system layers.
- PUE (Power Usage Effectiveness)—supporting infrastructure efficiency (standard);
- WUE (Water Usage Effectiveness)—water consumption in cooling processes (key from 2024);
- CUE (Carbon Usage Effectiveness)—operational carbon intensity (scope 2);
- ERE (Energy Reuse Effectiveness)—percentage of energy recovered and transferred.
5. Conclusions
6. Limitations and Future Research
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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| Instrument Class | Granularity | Metrics | Key Limitations | Smart City Use |
|---|---|---|---|---|
| Plug-in smart plugs/socket meters | 1–60 s | W, Wh/kWh; sometimes V, A, PF | Limited accuracy; may omit PF/reactive components; device-level only | Office/edge devices; pilot audits |
| Panel/DIN-rail energy meters (single/3-phase) | 1–60 s | V, A, W, Wh, PF; harmonics (optional) | Installation effort; CT placement errors; calibration needed | Building/room circuits; municipal IT rooms |
| PDU-level metering (rack) | 1–60 s | W, Wh; outlet-level (optional) | Aggregated by rack/outlet; vendor-specific APIs | Data-center racks; edge micro-DCs |
| UPS/power supply telemetry | 1–300 s | Input/output W, load %, efficiency | Reflects upstream supply; not per-device; efficiency curves | Critical loads; resilience + energy |
| Software/telemetry estimators (OS/hypervisor) | seconds–minutes | CPU/RAM utilization → W/Wh | Model uncertainty; needs calibration vs. physical meters | Fleet-scale monitoring; workload scheduling |
| Layer | Technique Category | Examples | Energy-Saving Mechanism | Trade-Offs/Constraints |
|---|---|---|---|---|
| Device/hardware | Low-power design | DVFS, clock gating, power gating, voltage islands | Reduces dynamic/leakage power when workload allows | May increase latency; design complexity |
| Firmware/OS | Power management policies | Sleep/hibernate, idle timers, device power states | Turns off subsystems during inactivity | Requires workload awareness; wake-up penalties |
| Application/runtime | Energy-aware software | Efficient algorithms, batching, reducing polling, adaptive sampling | Reduces CPU cycles and I/O activity | May reduce accuracy/quality; developer effort |
| Virtualization/cloud | Consolidation and scheduling | VM/container consolidation, right-sizing, autoscaling | Increases utilization; enables powering down servers | Risk of SLA violations; needs monitoring |
| Data-center facility | Infrastructure efficiency | Cooling optimization, airflow management, hot/cold aisles | Reduces overhead energy (cooling, power conversion) | CapEx; may constrain density |
| Network/edge | Placement and routing | Edge offload, caching, energy-aware routing | Moves compute closer to data; reduces transport/idle costs | Trade-offs in latency, security, manageability |
| Category | Indicative Impact Metric | Primary Measurement Basis | Maturity | Key Caveats |
|---|---|---|---|---|
| Facility efficiency (cooling/power chain) | PUE reduction; kWh overhead decrease | PUE, facility meters | High | Site-specific; climate and load matter |
| Workload consolidation/virtualization | Servers powered down; utilization increase | Rack/PDU meters + telemetry | High | Needs SLA-aware scheduling |
| DVFS/power gating | W reduction at given throughput | On-board sensors + external meters | Medium–High | Workload-dependent; thermal limits |
| Sleep modes/duty cycling (IoT/edge) | Wh/device/day reduction | Device meters, sampling logs | Medium | Depends on traffic patterns; wake-up cost |
| Energy-aware software | CPU time/I/O reduction W/Wh | Profiling + calibrated models | Medium | Model uncertainty; co-optimizes performance |
| ESG Dimension | KPI (Example) | Data Source | Linked Interventions |
|---|---|---|---|
| E (Environment) | Electricity saved (kWh); Scope 2 proxy (tCO2e) | Utility meter + submetering | Cooling optimization; consolidation; sleep policies |
| E (Environment) | Energy intensity (kWh/service unit) | Service telemetry + meters | Energy-aware software; autoscaling |
| S (Social) | Service availability/resilience | SLA monitoring; UPS telemetry | UPS efficiency; redundancy + load management |
| G (Governance) | Auditability of energy data | Data lineage; calibration logs | Metering architecture; verification procedures |
| G (Governance) | Payback period; capex/opex balance | Financial records + energy data | Retrofit decisions; equipment replacement |
| Technology | Potential Energy Reduction (PUE) | The Main Optimization Mechanism | Implementation Challenges | Maturity (TRL—Technology Readiness Levels) |
|---|---|---|---|---|
| Immersion Cooling (Liquid Immersion) | Very high (PUE < 1.05) | Complete elimination of fans; high heat capacity of the fluid | The need to replace physical infrastructure (racks, servers) | 8 (Implemented) |
| AI-Driven Load Orchestration | Medium/High (15–25% reduction) | Dynamic Core Sleep and Virtual Machine Consolidation Using ML | Algorithmic complexity, latency risk | 9 (Standard) |
| Waste Heat Recovery | High (ERE < 0.6) | Transferring heat to municipal heating networks or agriculture | Location of heat pumps close to heat consumers, legal barriers | 6–7 (Pilots) |
| Grid-Interactive Systems (BESS) | Low (operationally), High (economically) | Grid Stabilization (Frequency Response) Using UPS Batteries | Cell Degradation and Energy Market Regulation | 8 (Implemented) |
| Direct-to-Chip Cooling | High (PUE ~1.15) | Liquid Cooling Directly on the Processor (Cold Plates) | Risk of leakage within the server, complex piping. | 9 (Standard) |
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Miciuła, I.; Wojtaszek, H.; Mastalerz, M.; Wysocki, W.; Plecka, P.; Czaplewski, M.; Doskocz, J.; Raba-Schulze, A. Optimization of Electricity Consumption by Information Technology Devices in Accordance with Environmental, Social, Governance and Sustainable Development Principles. Energies 2026, 19, 1139. https://doi.org/10.3390/en19051139
Miciuła I, Wojtaszek H, Mastalerz M, Wysocki W, Plecka P, Czaplewski M, Doskocz J, Raba-Schulze A. Optimization of Electricity Consumption by Information Technology Devices in Accordance with Environmental, Social, Governance and Sustainable Development Principles. Energies. 2026; 19(5):1139. https://doi.org/10.3390/en19051139
Chicago/Turabian StyleMiciuła, Ireneusz, Henryk Wojtaszek, Marcin Mastalerz, Włodzimierz Wysocki, Przemysław Plecka, Maciej Czaplewski, Jacek Doskocz, and Aleksandra Raba-Schulze. 2026. "Optimization of Electricity Consumption by Information Technology Devices in Accordance with Environmental, Social, Governance and Sustainable Development Principles" Energies 19, no. 5: 1139. https://doi.org/10.3390/en19051139
APA StyleMiciuła, I., Wojtaszek, H., Mastalerz, M., Wysocki, W., Plecka, P., Czaplewski, M., Doskocz, J., & Raba-Schulze, A. (2026). Optimization of Electricity Consumption by Information Technology Devices in Accordance with Environmental, Social, Governance and Sustainable Development Principles. Energies, 19(5), 1139. https://doi.org/10.3390/en19051139

