Current-Summing Multilevel LCC Inverter for Radiated EMI Harmonic Reduction in Wireless Power Transfer

Abstract

This article proposes a parallel current-summing LCC multilevel inverter (MLI) to suppress harmonic distortion of radiated EMI for wireless power transfer. Traditionally, ZVS has been an issue for staircase voltage output multilevel inverters because a shared current output became faster than some of the voltage transitions in staircase voltage output. The other common problem was capacitor voltage imbalance and resultant output voltage distortion if a sophisticated voltage balancing function is not used. The proposed LCC MLI ensures ZVS by separating each voltage transition into multiple bridge legs. Each bridge leg outputs different phases of currents for each voltage transition. The individual output currents are summed at the matching network of wireless power transfer, generating a near-sinusoid output current to suppress harmonic distortions. In this way, each leg achieves ZVS even though the summed output current at the LCC network is faster than some of the voltage transitions. To avoid the capacitor voltage imbalance issue, the proposed MLI eliminated the flying capacitor. Instead, the four parallel legs are supplied by a shared DC input link. Therefore, the four legs can output identical voltages without using a typical DC flying capacitor. The necessity of multiple input voltage sources is, therefore, also eliminated. Measurement demonstrates that the proposed method effectively reduces radiated harmonic EMI by up to 14 dB.

1. Introduction

In inductive wireless power transfer (WPT), international regulation specifies an upper limit for the radiated magnetic field strength or electromagnetic interference (EMI). In Korean regulations, for example, the radiation of the third and fifth harmonics should be 57.78 dB and 61.24 dB below that of the fundamental 85 kHz [1]. Harmonic distortion in coil current should be reduced to suppress EMI radiation because the loosely coupled coil emits the majority of the magnetic field [2,3].

To solve this problem, many techniques have been proposed to reduce the harmonics in the squarewave inverter. Using additional filters is one of the techniques to reduce harmonics. However, the problem is the efficiency drop of 1.1% and 10% [4,5] due to the added filters. Magnetic materials like Ferrite and Nanocrystalline can shield the nearby metal casing frames from the magnetic field [6,7]. However, there still exists a significant open air gap between the TX coil and the RX coil, and this open air gap cannot be sealed by materials due to the application scenario of WPT, which requires clearance as wide as possible. While the nearby frames can be protected by Ferrite or Nanocrystalline, significant magnetic field leakage through the open air gap still radiates into the air. Adjusting and optimizing load resistance helps to suppress harmonic current [8]. However, it requires a dc/dc converter at the receiver side.

A multilevel inverter (MLI) is an attractive solution to reduce harmonic current. The multilevel inverters reduce harmonic distortion by generating a staircase output voltage that mimics an ideal sinusoid better than the squarewave output voltage [9,10,11,12,13,14,15]. While MLIs using flying capacitors (FCs) or neutral point clamped (NPC) capacitors are popular, they require voltage balancing control. Meanwhile, multiple DC source type MLIs use series-stacked bridge stages [10,11,16], where the multiple isolated DC voltage sources are not practical.

More importantly, regardless of FC, NPC, or series-stacked bridge MLI, they fail ZVS when it is used to generate staircase voltage output, which has multiple transitions within a period. This is because the same inverter current flows through different MOSFETs [9,10,11,12,13]. For example, [13] illustrates the ZVS turn-on failure issue at some rising edge transitions of the staircase output. This is because, in order to form multiple transitions of staircase outputs, the switch has to turn on at the moment when the output current has positive polarity. This will be discussed in Section 2 and Figure 1 of this paper.

Some MLIs for wireless power transfer successfully achieve ZVS in [17,18,19]. The modular multilevel topology is presented in [18,19]. They sum voltages across each flying capacitor or across series-connected submodules. The summation is performed in-phase by turning on selected submodules or MOSFETs at the same time. This can generate a squarewave voltage whose amplitude can be varied by the number of selected submodules. Therefore, although they achieve ZVS, they do not generate the staircase output voltage, which is necessary to reduce harmonic distortion EMI. The voltage balancing control for flying capacitors is also still necessary.

To address these problems, this paper proposes a parallel current-summing multilevel inverter for LCC-compensated wireless power transfer. This inverter introduces separate bridge leg outputs. Each leg generates a different phase of output voltage and current. The two currents of different phases from each leg are summed by the LCC impedance-matching inductors of wireless power transfer. The phase of voltage transition in each leg is faster than the phase of its MOSFET current, which achieves ZVS for all bridges. Other benefits are that only a single DC input source is used and that capacitor voltage balancing is not necessary.

Table 1. Comparison of multilevel inverters.

Type	Staircase Output Generation	Obviating Capacitor Voltage Balancing Control	Single DC Source Operation
FC	O	X	O
NPC	O	X	O
Series-stacked	O	O	X
Modular	X	X	O
Proposed	O	O	O

compares the characteristics of different MLI topologies.

2. Typical Staircase MLI in WPT

Figure 1a illustrates the ZVS failure issue of a typical MLI when it is generating staircase V_O. Although Figure 1 represents a schematic of an FC MLI, the output waveform is applicable to other topologies of MLIs, as in [11,13]. The series-connected MOSFETs carry the same output current I_O, and the polarity of I_O is positive at highlighted timings. Therefore, during the dead time between S₄ and S₁, the current cannot flow through the body diode of S₁. The S₁ fails ZVS turn-on, and the body diode of S₄ turns off with reverse recovery loss. ZVS failure at the V_O transition from half V_in to full V_in is also discussed in other topologies, such as [13].

This problem occurs because the same I_O flows through every MOSFET, while each MOSFET should turn on at different times to generate a staircase V_O output, which has multiple rising edges. For applications that do not generate staircase V_O output, as in [17,18,19], ZVS failure issue does not occur. However, in the proposed work, the goal is to reduce the harmonic distortion to mitigate radiated EMI, and, therefore, the staircase sinusoid-mimicking output is necessary.

Figure 1b illustrates the voltage imbalance issue. Due to the nonideal asymmetry of each transition, the DC voltage of capacitor C_fly cannot develop the precise half of V_in. This nonideality causes distortion in the V_O voltage waveform and exacerbates the EMI harmonic.

3. Proposed Multilevel Converter

3.1. Proposed MLI for Harmonic Reduction

Figure 2 is the proposed multilevel LCC inverter. The inductors L_S1 = L_S2 = L_S3 = L_S4 and C_P1 are designed to resonate at the switching frequency as in the typical LCC-matching design. Figure 3 illustrates operating waveforms. The output voltages V_d1 and V_d2 have different phases from each other. Even though V_d1 and the V_d2 do not sum in series as in a typical multilevel inverter, the output currents I_LS1 due to V_d1 and I_LS2 due to V_d2 are summed by two inductors, L_S1 and L_S2, which form I_inv = I_LS1 + I_LS2. In the bottommost pane in Figure 3, the summation (V_d1 + V_d2) in the red trace is a conceptual waveform, and it does not physically exist in the circuit. Rather, the physical output is I_inv = I_LS1 + I_LS2.

Meanwhile, each bridge leg produces its own output voltage and current at different phases. Not only the voltage, but also the current has different phases for each leg. Therefore, each leg achieves ZVS. For example, in Figure 3, at t₂, the transition of (V_d1 + V_d2) from V_in to 2V_in occurs when I_inv is positive, or when the phase of I_inv is faster than the second transition of (V_d1 + V_d2) at t₂. However, the actual transition at t₂ is determined by the turn off of M_B2. M_B2 and M_T2 achieve ZVS because they are switched with their own current I_LS2, not with I_inv. In contrast, in the conventional MLI topologies where multiple MOSFETs are series-connected as in Figure 1, there exists only one phase of output current I_O for every MOSFET, which causes ZVS failure for some MOSFETs.

The reason why the number of legs is four is that the staircase output in Figure 3 requires eight transitions, and each leg provides two transitions. Referring to Figure 3, the transitions in the red staircase coincide with the falling edge of the leg. Eight transitions require eight switches, which also need four legs. Three or five legs cannot produce the staircase output in Figure 3 because they produce six or ten transitions, respectively. Such waveforms are not symmetrical and worsen the EMI.

3.2. ZVS Switching Sequence

Figure 3 illustrates the switching sequences.

At t₁: M_B1 turns off, and this determines the rising edge of V_d1. The body diode of M_T1 (D_T1) begins to conduct before M_T1 turns on, and this allows I_LS1 to flow in the negative direction, which achieves ZVS.

At t₂: M_B2 turns off, and V_d2 rises from 0 to positive. At this moment, although the inverter current (I_inv), which is the sum of I_LS1 and I_LS2, is faster than the second transition in the staircase voltage, the leg output I_LS2 is slower than the V_d2. I_LS2 can flow in a negative direction, and the body diode of M_T2 (D_T2) starts conducting before the M_T2 channel turns on. This achieves ZVS of M_T2, even though I_inv is positive.

At t₃: M_B3 MOSFET is turned off, and this determines the rising edge of V_d3. The leg output current I_LS3 flows in the negative direction, and M_T3’s body diode (D_T3) begins to conduct before the M_T3 channel turns on. This achieves ZVS of M_T3.

At t₄: M_B4 turns off, and M_T4’s body diode (D_T4) starts conducting before the M_T4 channel turns on. V_d4 rises from 0 to a positive voltage, and I_LS4 flows in the negative direction, which achieves ZVS of M_T4.

The sequence of t₅~t₈ is similar to t₁~t₄.

Figure 3. Timing diagram of the proposed multilevel LCC inverter.

Figure 3. Timing diagram of the proposed multilevel LCC inverter.

3.3. Phase Angle to Reduce Harmonic Distortion

Typically, the third harmonic distortion is the most severe problem because its amplitude is the highest among all harmonics. The next consideration is the fifth harmonic, which usually causes the second-largest distortion. The Fourier series of the red-colored staircase waveform in Figure 3 is calculated as follows. The staircase waveform can be split into two components, as in Figure 4, such that the summation of the blue and green components produces the original staircase waveform in Figure 3. For the blue component, the Fourier series is as follows.

Figure 4. The staircase waveform is split into two parts for Fourier analysis.

Figure 4. The staircase waveform is split into two parts for Fourier analysis.

$$\begin{array}{cc}\hfill b_{n,blue}& ={\displaystyle \frac{1}{\pi }}{\displaystyle {\int }_0^{2\pi }{f}_{blue}(x)\sin nxdx}\hfill \\ & ={\displaystyle \frac{1}{\pi }}{\displaystyle {\int }_{t1}^{t4}{V}_{in}\sin nxdx}+{\displaystyle \frac{1}{\pi }}{\displaystyle {\int }_{t5}^{t8}(-V_{in})\sin nxdx}\hfill \end{array}$$

(1)

Now, due to the waveform symmetry, t₄ = π − t₁, t₅ = π + t₁, and t₈= 2π − t₁. Equation (1) becomes

$$\begin{array}{cc}\hfill b_{n,blue}& ={\displaystyle \frac{-V_{in}}{n\pi }}\left[\cos n(\pi -t_1)-\cos n{t}_1\right]+{\displaystyle \frac{V_{in}}{n\pi }}\left[\cos n(2\pi -t_1)-\cos n(\pi +t_1)\right]\hfill \\ & ={\displaystyle \frac{4V_{in}}{n\pi }}\cos n{t}_1\hfill \end{array}$$

(2)

Similarly, for the green component at t₂~t₃ and t₆~t₇, b_n,green is

$$\begin{array}{cc}\hfill b_{n,green}& ={\displaystyle \frac{1}{\pi }}{\displaystyle {\int }_{t2}^{t3}{V}_{in}\sin nxdx}+{\displaystyle \frac{1}{\pi }}{\displaystyle {\int }_{t6}^{t7}(-V_{in})\sin nxdx}\hfill \\ & ={\displaystyle \frac{4V_{in}}{n\pi }}\cos n{t}_2\hfill \end{array}$$

(3)

with the symmetry of t₃ = π − t₂, t₆ = π + t₂, and t₇= 2π − t₂. Summing (2) and (3) gives the total Fourier coefficient

$$b_n={\displaystyle \frac{4V_{in}}{n\pi }}\left(\cos n{t}_1+\cos n{t}_2\right)$$

(4)

Now, to suppress the third harmonic (n = 3), b₃ should be zero, i.e.,

$$b_3={\displaystyle \frac{4V_{in}}{3\pi }}\left(\cos 3t_1+\cos 3t_2\right)=0$$

(5)

This is achieved when

$$t_1+t_2=\pi /3$$

(6)

Meanwhile, the fifth harmonic component should also be zero, i.e.,

$$b_5={\displaystyle \frac{4V_{in}}{5\pi }}\left(\cos 5t_1+\cos 5t_2\right)=0$$

(7)

We want to suppress both the third and fifth harmonics simultaneously. Therefore, substituting (6) into (7) gives

$$\begin{array}{cc}\hfill b_5& ={\displaystyle \frac{4V_{in}}{5\pi }}\left(\cos 5t_1+\cos 5(\pi /3-t_1)\right)\hfill \\ & ={\displaystyle \frac{4V_{in}}{5\pi }}\left(1.5\cos 5t_1-0.87\sin 5t_1\right)=0\hfill \end{array}$$

(8)

Equation (8) is satisfied if t₁ = 13°. According to (6), t₂ is 47°.

Figure 5 presents the suppression of b₃ and b₅ when the angles have error deviations. Typical propagation delay variations of a few tens of nanoseconds correspond to 1~2 degrees at 85 kHz. For such typical delay variations, the degradations of suppression are not very severe.

3.4. Discussion on Volume and Harmonic Rejection Performance

Although the multiple resonant inductors (L_S1–L_S4) increase size compared to a simple basic inverter, the basic inverter should add a bandpass (inductor–capacitor) filter to remove harmonics at the same branch as in reference [4]’s Figure 14. The performance of the bandpass filter is simulated in Figure 6. The inductance of the bandpass filter for the simple inverter is set to be the same as the summation of additional resonant inductors of the proposed method. In other words, L_filt is 52.5 μH, which equals L_S2 + L_S3 + L_S4 in order to keep the inductances of the proposed and simple inverter identical to each other. The remainder of the system parameters, such as load and TX-RX coil parameters, are kept the same for the proposed and the simple inverter in

Table 2. Circuit design parameters and specifications.

Parameter	Value	Parameter	Value
LTX (set#1) LTX (set#2)	32.4 µH 32.2 µH	Coil air gap (set#1) Coil air gap (set#2)	6 cm 20~36 cm
LS1, LS2, LS3, LS4	17.5 µH	fS	85 kHz
CS1	165 nF	Vin	380 V
CP1	198 nF	Max Pout	3.4 kW
LRX (set#1)	32.5 µH	LRX (set#2)	30.6 µH

. The third harmonic rejection of I_TX output for the proposed and the simple filtering is 17.2 dB and 8.9 dB, respectively. Therefore, to achieve the same harmonic rejection performance, the inductance of the bandpass filter of the simple inverter is larger than that of the proposed method.

3.5. Difference from Prior Current-Interleaved Inverters

The purpose of a typical current-interleaved inverter is to reduce switching frequency ripple (usually 10~100 kHz) in order to produce a clean 60 Hz sinusoid output, i.e., the target sinusoid output frequency is much lower than the switching frequency. In contrast, the proposed inverter’s switching frequency (85 kHz) is equal to the desired output sinusoid because WPT applications require an 85 kHz clean sinusoid output. Most of the WPT applications use resonant inverters, of which the switching frequency (85 kHz) is close to the resonance frequency of the matching network. Hence, the switching frequency is not considered as a ripple or noise. Instead, it is the harmonics of switching frequency that needs to be suppressed.

In this regard, the phase shift for each leg is also different. The proposed inverter’s phases of 13° and 47° do not cancel the 85 kHz switching frequency itself. Instead, it is designed to cancel the harmonics of the switching frequency. On the other hand, a typical interleaved system’s phase is 0°–120°–240° or 0–180° in order to cancel the switching frequency itself. The output matching network and zero-voltage switching are also different. The proposed inverter is for an LCC resonant inverter, and zero-voltage switching (ZVS) is achieved. In contrast, typical low-frequency inverters do not employ resonant topology and ZVS.

4. Experimental Results

Figure 7 shows the measurement setup for the proposed wireless power transfer system. Two different configurations of TX-RX coils are used to verify the EMI suppression of the proposed inverter. In the first configuration, the diameter of coils is 20 cm, and the distance between the TX and RX coils is 6 cm. In the second configuration, the coil diameter is 51 cm, and the distance between TX and RX varies across 20~36 cm. This is to test the inverter with various operating scenarios. The circuit design parameters and specifications are detailed in Table 2. The proposed circuit operates with a single DC input source of 380 V_in. The switching frequency is 85 kHz, and the load output power is a maximum of 3.4 kW. The TMS320F28335 MCU generates the necessary clocks. Because the proposed inverter does not require any control algorithms, such as capacitor voltage balancing, the MCU just generates fixed clocks.

In oscilloscope captures in Figure 8, 100~200 MHz notates the sampling frequency of oscilloscope equipment, which is not related to the switching frequency of 85 kHz.

Figure 8a,b show how the hypothetical multilevel voltage output is produced. Figure 8b also shows that the proposed LCC inverter output, I_inv, becomes nearly sinusoid compared to the conventional LCC output current I_lcc,conv in Figure 8c. Figure 8c shows that the conventional LCC matching output I_lcc,conv contains significant harmonic components.

Figure 9 shows that the phase of the individual current for each leg is different, depending on the phase of each leg’s voltage. Each leg’s current is negative at the rising edge of V_{dn (n = 1,2,3,4)}, which enables ZVS for all switches. This is the advantage compared to typical voltage-summing MLIs, as discussed in Section 2. The summation of I_LS1 and I_LS2 in Figure 9 becomes the final inverter output I_inv in Figure 8b. The summation of I_LS3 and I_LS4 in Figure 9 is of opposite polarity and the same magnitude as I_inv. Figure 9 also shows the effect of coupling and load variations. For the variations of TX-RX coil distance (i.e., coupling coefficient) and load, ZVS is maintained for all bridge legs.

Figure 10 compares the measured radiated EMI harmonics between the proposed multilevel LCC inverter and the conventional LCC inverter. The schematic of conventional LCC is in Figure 8c. The EMI measurement equipment for Figure 10 are N9000B by Keysight and the HFH2-Z2E active loop antenna manufactured by Rohde & Schwarz. The measured noise floor of the N9000B and HFH2-Z2E combination was 14 dBμA/m at 255 kHz, 10 dBμA/m at 425 kHz, and 6 dBμA/m at 1 MHz, as shown in Figure 10, except for the 882 kHz peak of the AM radio broadcasting signal (Korean Broadcasting System corp.), which is not related to the device under test. The antenna is located at a distance of 3 m from the wireless power coils. Figure 7a shows the arrangements. As shown in Figure 10, the proposed multilevel LCC reduced EMI by 14 dB and 7 dB for the third (255 k) and fifth (425 k) harmonics, respectively. It is seen that the EMI suppression performance is maintained for full load conditions and no-load conditions. In contrast, the conventional LCC inverter fails to satisfy the Korea EMI regulation at the third harmonic (255 k) and cannot secure enough of a safety margin for the fifth harmonic (425 k). Additionally, the proposed MLI reduced total harmonic distortion (THD) by 12 dB.

Figure 11 shows the measured EMI harmonic levels for variations of load resistance and TX-RX coil distance. Figure 11 is measured with 51 cm diameter TX and RX coils. Tektronix MDO3024, in spectrum analyzer mode, is used along with the same HFH2-Z2E EMI sensor antenna, of which the noise floor is 5 dBμA/m. Harmonic suppression performance is maintained for load and coupling coefficient variations. Figure 11b is the same load resistance variation as Figure 11a, except that the location of the sensor antenna varies to 7 m.

Figure 12 compares the power loss. The overall efficiency is measured from the 380V DC input source to the DC output load. Although the proposed method slightly reduces the overall efficiency by 0.3%, the harmonic distortion became lower, and the Korean EMI regulation can be satisfied.

Table 3. Comparison with previous multilevel inverters for wireless power.

Topologies	[9]	[10]	[11]	[12]	[13]	[16]	[17]	[19]	Proposed
Single-Input Voltage Source	O	X	X	O	O	X	O	O	O
Staircase Output Availability	X	O	O	O	O	O	X	X	O
ZVS For Staircase Output	n/a	n/a	X	X	X	X	n/a	n/a	O
Obviating Capacitor Voltage Balancing	X	O	n/a	X	X	O	X	X	O
Output Power (W)	400	500	40 k	1 k	21 k	20 k	850	7.7 k	3.4 k
Efficiency	95.2%	85%	n/a (Simul.)	84.1%	95.96% (ac-dc)	88% (Simul.)	92%	93%	95.4%

compares prior multilevel inverters for wireless power transfer applications. The proposed method achieves high efficiency and ZVS with the low-distortion staircase output. These are obtained using a single DC input source, and capacitor voltage balancing is not necessary.

5. Conclusions

This paper proposes a multilevel LCC inverter for wireless power transfer applications in order to suppress harmonic distortions and radiated EMI. Unlike conventional multilevel inverters, the proposed method achieves ZVS while outputting a sinusoid-mimicking staircase waveform. Moreover, the method uses only a single DC input source, and capacitor voltage balancing is not necessary. The proposed inverter suppresses the third harmonic EMI by 14 dB and the fifth harmonic by 7 dB. The system is running in an open loop without feedback control. However, it is seen that ZVS and harmonic suppression are not affected by coupling and load variations.