Triple-Voltage Gain and Self-Balancing in a New Switched-Capacitor Seven-Level Inverter for Microgrid Integration

Abstract

In the context of power electronic interfaces in photovoltaic (PV), fuel cell, battery, and microgrid applications, the low output voltage of the DC source necessitates a voltage-boosting inverter. This paper proposes a single-source seven-level switched-capacitor boost inverter, particularly for low-voltage applications. The proposed inverter has the capability to produce seven different output voltage levels, i.e., intermediate boosted levels, with a total gain of three times the input voltage. The inverter has the advantage of a reduced number of power switches, diodes, and a switched-capacitor unit, which allows for single-stage operation without the need for a second DC-DC converter. The operating principle of the proposed inverter is explained in detail with a complete switching state analysis, conduction path analysis, and output voltage generation. The capacitor size is calculated using a charge balance-based equation. The self-balancing capability is validated for mismatched initial voltages with a bounded steady-state ripple. To evaluate the performance of the proposed inverter in a more realistic scenario, the effects of non-ideal device characteristics are considered, and the efficiency of the inverter is estimated using a loss model. A predictive current control technique is applied to control the output current under inductive load conditions. The simulation results obtained in MATLAB/Simulink software validate the proper seven-level operation of the inverter, the self-balancing capability of the capacitors, improved output waveform quality, and current control. The proposed inverter can be extended to grid-connected applications, where conventional output filters can be applied to meet the harmonic standards.

1. Introduction

Power electronic converters known as multilevel inverters (MLIs) are frequently used to convert DC voltage into AC voltage in numerous fields, including renewable energy systems, electric vehicles, microgrids, and power transmission and distribution systems [1]. When compared with the conventional two-level inverter, MLIs offer numerous advantages, including better voltage quality, reduced harmonic distortion, lower electromagnetic interference, and higher reliability [1,2]. However, the use of MLIs also involves some disadvantages, including the complexity of the circuit, the use of more power electronic devices, and the voltage regulation of capacitors. Despite the disadvantages of MLIs, numerous researchers are interested in the use of MLIs because they are capable of overcoming the disadvantages of conventional two-level converters.

In the family of MLIs, the use of extensible multilevel inverters has been recognized as one of the promising power electronic converters for use in power systems where the voltage level and power rating are required to be changed frequently. The use of switched-capacitor-based multilevel converters enables the voltage boosting of the DC voltage without the use of any magnetic component and the need for an additional DC-DC conversion stage [1,3]. The use of switched-capacitor-based multilevel converters allows for the generation of multiple voltage levels using a DC voltage source, with the ability to increase the voltage level using the switched-capacitor cells [4,5,6].

In switched-capacitor-based multilevel converters, capacitors are used to store energy temporarily and discharge the energy during the switching time to generate the AC voltage with multiple levels [7]. The use of capacitors allows the generation of AC voltage with multiple levels using switched-capacitor cells without the use of any magnetic component. However, the use of switched-capacitor-based multilevel converters also has some disadvantages, including the regulation of capacitor voltage, higher current stress on the capacitor during the capacitor charging time, and the efficiency of the switched-capacitor-based multilevel converters [8,9,10].

Some other boost-capable multilevel inverter topologies with reduced switch count have also been reported. For example, a seven-level boost-capable multilevel inverter based on the packed U-cell configuration was reported in [11], in which active control of the capacitor voltage was required. A nine-level hybrid multilevel inverter using the H-bridge configuration for polarity reversal was reported in [12]. The switched-capacitor-based hybrid multilevel inverter reported in [13] requires reverse-blocking switches, and the packed E-cell configuration reported in [14] is not boost-capable. A diamond-shaped hybrid multilevel inverter was also reported in [15]. The configuration reported in this paper requires a higher number of voltage levels at the expense of a higher number of capacitors, diodes, and switches. A nine-level multilevel inverter using different voltage ratings for the capacitors was reported in [16] to achieve a higher voltage gain. However, this configuration also increases the design constraints.

In addition, various single-input and dual-source multilevel inverter configurations have been reported in the literature. For example, multilevel inverters were reported in [17,18,19,20,21]. In these studies, the voltage gain and the number of voltage levels increase at the expense of a higher number of components. Dual-source switched-capacitor-based multilevel inverters were reported in [22,23,24,25,26,27]. In these studies, the voltage levels increase at the expense of a higher number of voltage sources or non-boosting sources. Additionally, the voltage stress increases as the number of components increases in the configuration reported in [26,27].

Despite the extensive research carried out on boost-capable multilevel inverters, there are certain limitations that have been identified with the existing topologies. Some of the existing topologies require a higher number of components, complex hybrid structures, and the use of different voltage-rated capacitors. Moreover, in certain topologies of switched-capacitor-based inverters, the capacitor voltage balancing is not inherently ensured. This requires additional sensing and control of the capacitor voltages. This adds additional control complexity and reduces the converter’s reliability. Certain existing topologies have also been implemented with hybrid H-bridge structures and reverse-blocking switches. This results in increased voltage stress on the switches and also increases the cost of the converter. Moreover, certain existing topologies have not clearly described all the operating modes and conduction paths of the converters for the intermediate voltage levels. This adds additional complexity to the reproduction of the converter.

Boost inverters are commonly used in photovoltaic systems. The low output voltage of the PV panel needs to be boosted to a higher level that is suitable for grid-connected inverters. Single-stage boost multilevel inverters have the potential to reduce the size and losses of the system. The multilevel output of the converter reduces the harmonic distortion of the output current. This reduces the filter requirements of the system. The converter can be designed to meet the harmonic standards of the grid with the addition of a suitable filter. Moreover, the operating principle of the switched capacitor is a conceptual step towards the adaptation of the converter for energy storage-embedded converter configurations [28].

Inspired by the above explanations, this paper presents a new configurable switched-capacitor multilevel inverter with the capability to produce seven different voltage levels with a total gain of around three, utilizing a single DC source. Compared to existing multilevel inverters, the proposed topology is unique due to the following reasons: fewer components are used; capacitor voltage balancing is achieved naturally; the maximum voltage rating of the components is fixed; and the operating modes for all seven voltage levels are clearly explained. Moreover, the proposed topology is also suitable for extending the configuration with the help of switched-capacitor blocks to obtain higher voltage gain with the same operating principle.

The rest of the paper is organized as follows: Section 2 explains the proposed topology and its operating principle. Section 3 explains the modulation and control techniques. Section 4 explains the simulation and performance analysis for different operating conditions. Section 5 explains the comparison with existing topologies. Finally, Section 6 concludes the paper with future work.

2. Proposed Topology

The suggested multilevel inverter topology is composed of one DC voltage source and a switched-capacitor component. The suggested topology is presented in Figure 1. The topology is composed of two capacitors represented as C₁ and C₂, two diodes represented as D₁ and D₂, and eight active power switches represented as S1 to S8. The left part of the topology is the switched-capacitor boosting network, while the right part is the single-phase inverter bridge.

The main purpose of the switched-capacitor network is to provide the voltage-boosting function. The capacitors C₁ and C₂ are selectively connected to the DC voltage source through different states. The capacitors can be connected individually or together in series with the DC voltage source. The generation of multiple voltage levels is achieved without the requirement of an additional DC-DC converter. The diodes D₁ and D₂ provide a unidirectional path for the current. This path is essential for proper capacitor charging.

Through the appropriate coordination of the switching states, the proposed inverter is able to produce seven different discrete output voltage levels, i.e., 0Vdc, ±Vdc, ±2Vdc, and ±3Vdc. The intermediate voltage levels are achieved by connecting one of the switched capacitors in series with the DC source, while the maximum voltage levels are achieved by connecting both capacitors in series with the DC source. The zero-voltage level is achieved through the freewheeling states of the inverter bridge, thus allowing the current to flow continuously during the supply of inductive loads.

A significant advantage of the proposed inverter topology is that the charging and discharging times of the two capacitors, i.e., C₁ and C₂, are complementary, constituting one fundamental cycle. This ensures that the capacitor voltages will converge to their rated values, thus providing the advantage of self-balancing without the need for additional voltage sensors. Moreover, the blocking voltage of the power switches is bounded by the boosted DC-link voltage, thus improving the scalability of the proposed inverter topology.

2.1. The Operating Principle of the Seven-Level Boost Inverter

Table 1. Switching configurations and resulting output voltages of the proposed topology.

S1	S2	S3	S4	S5	S6	S7	S8	C	Vector	Output
0	0	0	0	1	0	1	0	idle	V0	0
0	1	0	1	1	0	0	1	+	V1	+Vdc
0	0	1	0	1	0	0	1	-	V2	+2Vdc
1	0	1	0	1	0	0	1	-	V3	+3Vdc
0	0	0	0	0	1	0	1	idle	V4	0
0	1	0	1	0	1	1	0	+	V5	−Vdc
0	0	1	0	0	1	1	0	-	V6	−2Vdc
1	0	1	0	0	1	1	0	-	V7	−3Vdc

below shows a summary of valid switching states of the proposed SCMLI and their associated voltage levels. It is evident from Table 1 that the proposed SCMLI has the capability to generate seven different voltage levels. The seven levels comprise zero-voltage levels, positive and negative levels of the input voltage, intermediate levels of boosting, and the maximum levels of boosting. In Table 1, “+,” “−,” and “idle” refer to the state where the corresponding capacitor is in the process of charging, discharging, or neither charging nor discharging, respectively.

In order to simplify the explanation of the operating principle of the proposed SCMLI, the following assumptions are made:

(1)

The input voltage is considered to be constant.

(2)

The voltages across the capacitors in the proposed SCMLI circuit are considered to be at their normal values.

(3)

The power semiconductor devices in the SCMLI circuit are considered to be ideal.

Note that these assumptions are made for analytical purposes only.

2.1.1. Zero-Voltage Level Operation

The zero-voltage level is achieved using two different switching states that allow for bidirectional current flow in the presence of an inductive load. When the voltage level is zero, the load current flows through the freewheeling path provided by the appropriate inverter switches. During this operating mode, both capacitors are in an idle state, and no interaction with the capacitors occurs. This operating mode ensures a smooth flow of current and stable operation with an inductive load.

2.1.2. Positive Voltage Levels

The positive fundamental voltage level, +Vdc, is achieved by connecting the DC source to the load through the inverter switches, with both capacitors either in charging mode or idle state. During this operating mode, the inverter circuit operates as a conventional voltage-source inverter with one DC source connected to the load.

The intermediate voltage level, +2Vdc, is achieved by connecting one switched capacitor in series with the DC source. During this operating mode, one capacitor discharges to support the load voltage, with the other capacitor either in charging mode or an idle state. This operating mode is specifically included in Table 1 and is essential in achieving the true seven-level inverter.

The maximum boosted voltage level, +3Vdc, can be achieved by connecting both capacitors in series with the DC source. In this configuration, both capacitors will discharge and supply voltage to the load.

2.1.3. Negative Voltage Levels

Negative voltage levels are achieved by using the same operating principle but with opposite current flow in the inverter switches. The zero-voltage level in the negative half-cycle is achieved by an alternative configuration in freewheeling mode.

The −Vdc voltage level is achieved by simply connecting the DC source in series with the load, but with a reversed polarity. In this configuration, the capacitors are either in a charging mode or idle. The −2Vdc voltage level is achieved by simply combining the DC source with a discharging capacitor in series with the load. Finally, the −3Vdc voltage level is achieved by discharging both capacitors in series with the DC source.

2.1.4. Inductive Load Compatibility and Self-Balancing Behavior

For all operating modes, a closed current path is provided by the proposed inverter. Thus, inductive load compatibility is ensured by the proposed inverter. The capacitors’ charging/discharging intervals are complementary in a fundamental cycle. Thus, capacitor voltage self-balancing is inherently achieved without using additional control blocks.

The switching states corresponding to each voltage level are provided in Table 1. The conduction paths for positive and negative voltage levels are shown in Figure 2 and Figure 3.

2.2. Design of the Capacitor

The selection of an appropriate capacitance value is critical in controlling the voltage ripple across the switched-capacitor network and generating stable multilevel voltages. The voltage ripple across the capacitor can result in distortion of the multilevel voltage, increased current stress, and degradation of the inherent self-balancing characteristics. Therefore, the capacitor selection should be based on the actual charging and discharging characteristics observed during the inverter operation.

At the initial condition, the capacitor is assumed to be uncharged, which can be expressed as follows:

$$\begin{array}{c}{V}_c\left(0\right)=0\\ i_c\left(0\right)=0\end{array}\}$$

(1)

During the charging interval (as shown in the figures illustrating the charging modes of the operating principle), the capacitor is connected to the input source. In this case, the voltage of the capacitor is equal to the DC voltage of the input, and the current of the capacitor depends on the difference between the input current and the load current:

$$\begin{array}{c}{V}_c=V_{dc}\\ i_c=i_{in}-i_{load}\end{array}\}$$

(2)

During the discharging period, the capacitor contributes to the output voltage level. In this mode of operation, the capacitor voltage contributes to the generation of the output voltage, and the capacitor current is mainly equal to the load current.

$$\begin{array}{c}{V}_c=V_o-V_{dc}\\ i_c=i_{in}\end{array}\}$$

(3)

The capacitor voltage ripple is governed by the fundamental capacitor equation, which relates the voltage variation to the net transferred charge:

$${∆V}_c={\displaystyle \frac{1}{C}}{\int }_{t_1}^{t_2}{i}_c\left(t\right)dt$$

(4)

To obtain a useful design equation, the capacitor current during the worst-case charging or discharging period may be taken as its average value. The minimum capacitance value may therefore be expressed as follows:

$$C\ge {\displaystyle \frac{I_{c,avg}{T}_{eff}}{{∆V}_c}}$$

(5)

Here, $I_{c,avg}$ represents the average capacitor current during the effective charge or discharge interval, $T_{eff}$ represents the duration of the corresponding switching state within one switching period, and ${∆V}_c$ is the allowable peak-to-peak capacitor voltage ripple.

The worst-case ripple occurs in situations of high load current and in modes where intermediate levels of boosted voltage are generated. Therefore, it is important that the capacitor value is determined with consideration of the maximum load current and the longest discharge time. The equivalent series resistance of the capacitor is another factor that contributes to additional voltage ripple and power loss. Therefore, it is important that low-ESR capacitors are used, along with a design margin.

2.3. Current and Voltage Stresses

Table 2. Voltage and current stresses on power switches.

Switches	Voltage Stress	Current Stress
S1	Vdc	Load/Iin
S2	Vdc	Load/Iin
S3	Vdc	Load/Iin
S4	2Vdc	Load/Iin
S5	3Vdc	Load/Iin
S6	3Vdc	Load/Iin
S7	3Vdc	Load/Iin
S8	3Vdc	Load/Iin

presents a summary of the voltage and current stresses experienced by the power switches in the proposed seven-level boost inverter. The voltage stress experienced by each power switch in the proposed inverter depends on the location of the particular switch in the switched-capacitor network and the inverter bridge. The current stress on each power switch in the proposed inverter depends on the active conduction path for a given switching state.

In the proposed inverter, power switches S5, S6, S7, and S8 form part of the inverter bridge. As a result, these power switches are subjected to the highest voltage stress in comparison with other power switches in the proposed inverter. The voltage stress experienced by these power switches in the proposed inverter occurs during inverter operation at the highest voltage level. Consequently, these power switches are subjected to a voltage stress equal to three times the input DC voltage. The voltage stress experienced by power switches S1, S2, and S3 in the proposed inverter is due to the input DC voltage, while S4 experiences twice that voltage.

The current stress on the power switches in the proposed inverter depends on the load current through a particular active conduction path. During operation of the proposed inverter at boosted voltage levels, the power switches forming part of the series-connected capacitors are subjected to a current stress equal to the inverter DC-link current supplied to the load. Consequently, to ensure the safe operation of the proposed inverter, all power switches should be rated for a current stress equal to the inverter current.

2.4. Loss Analysis

This section aims to quantify the power losses of the proposed inverter topology by taking into consideration the major non-ideal characteristics of semiconductor devices and the switched capacitors used in the topology. The total power loss is calculated as the sum of the individual power losses due to (i) switch conduction loss, (ii) switch switching loss, (iii) diode conduction loss, and (iv) capacitor ESR loss. Since the proposed topology does not use inductors, magnetic losses are not considered.

2.4.1. Total Loss Model

The total converter loss is defined as the sum of the following: (i) total switch conduction loss, (ii) total switching loss, (iii) diode conduction loss, and (iv) capacitor ESR loss. It can be expressed as

$$\begin{array}{cccc}& P_{\mathrm{loss}}=P_{\mathrm{cond},\mathrm{sw}}+P_{\mathrm{sw}}+P_{\mathrm{d}}+P_{\mathrm{ESR}}& & \end{array}$$

(6)

The efficiency is given by

$$\begin{array}{cccc}& \eta ={\displaystyle \frac{P_{\mathrm{out}}}{P_{\mathrm{out}}+P_{\mathrm{loss}}}}.& & \end{array}$$

(7)

2.4.2. Switch Conduction Loss

For a MOSFET implementation, the conduction loss of switch $j$ is

$$\begin{array}{cccc}& P_{\mathrm{cond},j}=R_{\mathrm{ds}\left(\mathrm{on}\right),j}\hspace{0.17em}{I}_{j,\mathrm{rms}}^2,& & \end{array}$$

(8)

and thus,

$$\begin{array}{cccc}& P_{\mathrm{cond},\mathrm{sw}}={\displaystyle \sum _{j=1}^8}{P}_{\mathrm{cond},j}.& & \end{array}$$

(9)

(For an IGBT, $P_{\mathrm{cond},j}\approx V_{\mathrm{CE}\left(\mathrm{sat}\right),j}{I}_{j,\mathrm{avg}}$).

2.4.3. Switching Loss

The switching loss of switch $j$ can be estimated using datasheet switching energies:

$$\begin{array}{cccc}& P_{\mathrm{sw},j}=f_{\mathrm{sw},j}(E_{\mathrm{on},j}+E_{\mathrm{off},j}),& & \end{array}$$

(10)

and the total switching loss is

$$\begin{array}{cccc}& P_{\mathrm{sw}}={\displaystyle \sum _{j=1}^8}{P}_{\mathrm{sw},j}.& & \end{array}$$

(11)

For PD-PWM, $f_{\mathrm{sw},j}\approx f_{\mathrm{sw}}$(fixed). For FS-MPC, $f_{\mathrm{sw},j}$ is the effective switching rate extracted from the switching events per second.

2.4.4. Diode Conduction Loss

For each diode $k\in \left\{\mathrm{1,2}\right\}$,

$$\begin{array}{cccc}& P_{\mathrm{d},k}=V_{f,k}\hspace{0.17em}{I}_{d,k,\mathrm{avg}}.& & \end{array}$$

(12)

Hence,

$$\begin{array}{cccc}& P_{\mathrm{d}}={\displaystyle \sum _{k=1}^2}{P}_{\mathrm{d},k}.& & \end{array}$$

(13)

2.4.5. Capacitor ESR Loss

The ESR loss in capacitor $m\in \left\{\mathrm{1,2}\right\}$ is

$$\begin{array}{cccc}& P_{\mathrm{ESR},m}=r_{\mathrm{ESR},m}\hspace{0.17em}{I}_{c,m,\mathrm{rms}}^2,& & \end{array}$$

(14)

and thus

$$\begin{array}{cccc}& P_{\mathrm{ESR}}={\displaystyle \sum _{m=1}^2}{P}_{\mathrm{ESR},m}.& & \end{array}$$

(15)

The RMS/average currents $I_{j,\mathrm{rms}}, { I}_{d,k,\mathrm{avg}}, I_{c,m,\mathrm{rms}}$ are obtained from simulation waveforms over one fundamental cycle, ensuring that all seven voltage levels (including the intermediate levels) are included in the loss estimation. The loss model is used to estimate converter efficiency under realistic operating conditions; experimental validation is planned for future work.

3. Model Predictive Control of the Proposed Seven-Level Boost Inverter

To control the output current of the proposed seven-level boost inverter, the finite control set model predictive control strategy is used. The strategy directly exploits the inverter’s discrete switching states and predicts the future behavior of the output current for each voltage level. For the single-phase RL load connected to the output of the inverter, the continuous-time dynamic model of the load current can be articulated as follows:

$${\displaystyle \frac{d{i}_o}{dt}}={\displaystyle \frac{1}{L}}\left(v_o-{Ri}_o\right)$$

(16)

where $i_o$ is the output current, $v_o$ is the inverter output voltage, $R$ is the load resistance, and $L$ is the load inductance.

Using a forward Euler discretization with sampling interval Ts, the discrete model of the output current can be written as follows:

$$i_o\left(k+1\right)=i_o\left(k\right)+{\displaystyle \frac{T_s}{L}}\left(v_o\left(k\right)-{Ri}_o\left(k\right)\right)$$

(17)

At each sampling instant, the inverter can generate a finite set of output voltage levels corresponding to its switching states. For the proposed topology, the available voltage level is

$${\mathrm{V}}_{\mathrm{i}}\in \left\{{\mathrm{V}}_0,{\mathrm{V}}_1,\cdots ,{\mathrm{V}}_7\right\}$$

(18)

where each voltage level ${\mathrm{V}}_{\mathrm{i}}$ corresponds to a specific switching vector of the seven-level inverter.

Using the discrete-time model in (17), the future output current is predicted for each candidate voltage level ${\mathrm{V}}_{\mathrm{i}}$, yielding

$$i_o\left(k+1\right)=i_o\left(k\right)+{\displaystyle \frac{T_s}{L}}\left({\mathrm{V}}_{\mathrm{i}}-{Ri}_o\left(k\right)\right)$$

(19)

In order to find the optimal switching state, a cost function is defined to evaluate the tracking error between the predicted output current and the reference current. A basic form of the cost function is given by

$$J_i=\left|i_{ref}\left(k+1\right)-i_o^{\left(i\right)}(k+1)\right|$$

(20)

where $i_{ref}\left(k+1\right)$ is the reference current at the next sampling instant.

To improve control performance and reduce excessive voltage transitions, a weighted cost function can be employed as

$$J_i=\alpha \left|i_{ref}\left(k+1\right)-i_o^{\left(i\right)}(k+1)\right|+\beta \left|V_i\right|$$

(21)

where $\alpha$ and $\beta$ are weighting factors that balance current tracking accuracy and switching effort.

Finally, the minimized cost of choosing a vector $V_{opt}$ can be expressed as

$$V_{opt}={}_i{}^{argmin} J_i$$

(22)

The switching state related to $V_{opt}$ is subsequently applied to the inverter in the following sampling period. This predictive control technique enables a prompt dynamic response, precise current control, and direct control of the discrete voltage levels related to the proposed seven-level inverter.

4. Modulation Strategy

To show the effectiveness of the dynamic performance and tracking ability of the finite set model predictive control (FS-MPC) method, a conventional phase disposition PWM (PD-PWM) method is employed as a baseline comparison method. Multilevel inverters can be controlled using various pulse-width modulation techniques to produce stepped waveforms with reduced harmonic distortion. Various modulation techniques for multilevel inverters have been proposed in the literature, such as sinusoidal PWM, space-vector PWM, and selective harmonic elimination PWM. SVPWM is reported to produce satisfactory results for inverters with a small number of voltage levels [26]. However, the complexity of the SVPWM technique is reported to increase with the number of levels in the inverter. The SHE-PWM technique is reported to produce satisfactory results by improving the utilization of the DC link voltage and reducing the number of switching cycles. However, the use of the SHE-PWM technique is limited due to the non-linear equations involved in the modulation index calculations, as well as the parameter sensitivity of the technique. Therefore, the carrier-based sinusoidal PWM technique has been widely used for the modulation of multilevel inverters due to its simplicity and robustness.

In this work, the proposed seven-level boost inverter is modulated using the phase disposition PWM technique, which is a well-established carrier-based sinusoidal PWM technique for the modulation of multilevel inverters. In the PD-PWM technique, the carrier signals are of the same frequency and amplitude, with a phase difference of zero degrees between the carrier signals.

For the proposed seven-level inverter, six triangular carrier signals are required for the modulation of the inverter. As shown in Figure 4a, six triangular carrier signals, denoted as Vcr1-Vcr6, are compared with a sinusoidal signal denoted as Vref. The amplitude of the sinusoidal signal is denoted as Aref, while the frequency of the sinusoidal signal is denoted as fref. The modulation index is defined as the ratio of the amplitude of the sinusoidal signal to the amplitude of the carrier signal, with the modulation index set to 0.9 in this work.

The comparison between the reference signal and the six carriers produces gating signals for the generation of the seven different voltage levels. Depending on the instantaneous position of the reference signal relative to the carrier bands, the inverter output switches between the different voltage levels 0, ±Vdc, ±2Vdc, and ±3Vdc. The two intermediate voltage levels, ±2Vdc, naturally occur when the reference signal is between the two carrier thresholds. This naturally produces the seven-level inverter output.

The gating signals for the switches S1–S8 for a fundamental cycle are shown in Figure 4b. Because of the symmetry in the proposed topology, the switches S1–S4 operate synchronously to control the switched-capacitor network, and the inverter bridge switches operate in pairs, (S5, S7) and (S6, S8), to produce positive and negative voltage levels. This reduces the total gate drivers required compared to conventional multilevel inverter configurations.

The output voltage waveform is shown in Figure 4c, where all seven voltage levels can be observed. The stepped waveform follows the sinusoidal reference signal closely, verifying the effectiveness of the proposed PD-PWM strategy in generating a high-quality output voltage and fully utilizing the voltage-boosting potential of the proposed topology.

5. Simulation Results

A comprehensive simulation model of the proposed seven-level switched-capacitor boost inverter was developed using MATLAB/Simulink to verify the topology as well as the modulation and control strategies used. The parameters used in the simulation model are given in

Table 3. The simulation parameters of the proposed topology.

Parameters	Values
Input voltage	48 V
Switching Frequency	20 kHz
Modulation index	0.9
capacitor	2200 µf
Resistive, inductive load	25 Ω–20 mH

.

The simulation results are presented in Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9. Figure 5a,b show the capacitor voltage waveforms obtained with RL loading by adopting the PD-PWM and FS-MPC control methods. In both instances, it is evident that the capacitor voltage is steady and remains centered around the input DC voltage of 48 V. This is an inherent feature of the proposed topology. The peak-to-peak voltage ripple is limited and remains within the acceptable value of less than 2.7 V.

Figure 6a,b show the output voltage and load current waveforms for the PD-PWM and FS-MPC control methods, respectively. As can be observed, the output voltage has seven distinct levels: 0, ±48 V, ±96 V, and ±144 V, which are consistent with the theoretical values of 0, ±Vdc, ±2Vdc, and ±3Vdc, respectively. On the other hand, the load current has a nearly sinusoidal waveform, which is consistent with the expected performance of the inverter, especially for inductive loads. This shows that the boosted output voltage is indeed achieved by the series connection of capacitors during certain operating states, with each capacitor regulated to the input voltage.

In addition, Figure 7 shows the performance of the finite-set model predictive current control strategy in terms of the inverter output current relative to the reference current during steady-state operation. As indicated in the figure, there is a close relationship between the reference current and the inverter output current. This indicates that the FS-MPC algorithm can select the optimal state at each sampling instant based on the model. In addition, there is no significant phase difference between the reference current and the inverter output current. This indicates accurate current regulation. In addition, there is no significant overshoot in the current waveforms. This indicates that there is a fast dynamic response of the FS-MPC algorithm, which is due to the fact that FS-MPC does not use any predefined modulation pattern and is able to evaluate all possible states. This is different from carrier-based PWM techniques. This result is in agreement with the fast dynamic response of the FS-MPC algorithm, as indicated in the simulation results.

Figure 8a,b present the voltage stress across the inverter switches under PD-PWM and FS-MPC control, respectively. It can be observed that switches S5–S8 experience the highest voltage stress, equal to three times the input DC voltage, whereas switches S1–S3 are subjected only to the input voltage, while S4 is subjected only to the input voltage. This bounded voltage stress characteristic validates the analytical stress analysis and demonstrates the suitability of the proposed inverter for practical implementation with appropriately rated devices.

Figure 9a,b show the current stress on the inverter switches for purely resistive and resistive-inductive loads, respectively. It is noticed that the current stress level varies with the active switching state and load type. All the current stress levels are within the expected range. This shows the inverter’s ability to operate with different types of loads while maintaining the voltage level.

The comparison between PD-PWM and FS-MPC further indicates that, whereas the fixed switching frequency operation is ensured by PD-PWM, improved dynamic response is provided by FS-MPC through the selection of states.

6. Comparative Study

In this paper, a seven-level switched-capacitor boost inverter is proposed, which provides a balanced trade-off in terms of voltage gain, component count, and voltage stress. To compare different multilevel inverter topologies, two voltage stress indicators, the maximum blocking voltage (MBV) and the total standing voltage (TSV), are used. The MBV refers to the maximum voltage stress applied to any single power switch in the inverter, normalized with respect to the DC input voltage. It directly affects the voltage rating of the semiconductor devices used in the inverter. On the other hand, the TSV is defined as the sum of the maximum blocking voltage of all active switches in the inverter topology. It is used to measure the voltage stress applied to semiconductor devices, with a lower TSV indicating better voltage stress distribution.

As shown in

Table 4. Comparison of the proposed topology with related works.

Ref.	No. Capacitors	No. Diodes	No. Switches	No. Levels	Gain	Capacitor Charging Balance	Total Elements	MBV	TSV	THD %	η % Simulation
[29]	3	3	6	3	2	Inherent	12	2 Vdc	12V dc	2.20	97.90
[30]	2	-	10	5	2	Inherent	12	2 Vdc	14V dc	4.60	94.50
[31]	3	2	8	7	3	Inherent	13	>3 Vdc	27V dc	4.13	96.35
proposed	2	2	8	7	3	Inherent	12	3 Vdc	17V dc	3.35	98.45

, the proposed inverter configuration requires merely two capacitors, two diodes, and eight active switches. Therefore, a total of twelve components is required in this inverter configuration. By using a parallel connection for capacitor charging and a series connection for capacitor discharging, a triple-voltage gain is achieved by a single DC source. Moreover, the inherent voltage self-balancing capabilities of capacitors are maintained in this inverter configuration.

As compared with the transformerless three-level inverter configuration proposed in [29], a significant improvement in the number of voltage levels and voltage gain has been achieved in the proposed inverter configuration with a similar number of components. In comparison with an extensible SC inverter configuration proposed in [30], a higher voltage gain with improved power quality has been achieved in the proposed inverter configuration with a similar number of components. In comparison with a seven-level triple boost inverter configuration proposed in [31], a similar voltage gain with a higher number of voltage levels has been achieved in the proposed inverter configuration with a lower number of components and a lower TSV.

7. Conclusions

This paper proposes a novel seven-level switched-capacitor boost inverter topology, which is suitable for renewable energy systems and microgrid applications. The proposed topology attains seven levels of output voltage with a voltage gain of approximately three using a single DC source and a reduced number of power switches and passive components. The operation of the proposed topology was explained in detail, along with the switching states of the proposed topology. The capacitor voltage balance method was also discussed, and the self-balancing of capacitor voltages using the proposed topology was demonstrated using the simulation results.

To evaluate the performance of the proposed topology more accurately, non-ideal device characteristics were also considered, along with the efficiency of the proposed topology. The simulation results of the proposed topology with various inductive loads were obtained, which validate the proper operation of the proposed topology. The proposed topology attains seven levels of voltage with better output waveform quality using predictive current control. The reduced number of components in the proposed topology may reduce the cost of the proposed topology when compared with existing seven-level boost inverter topologies.

The grid connection of the proposed topology was also discussed, and the filtering of the output voltage of the proposed topology was considered suitable for grid-connected systems. Although the analytical modeling of the proposed topology was carried out in this study, the practical implementation of the proposed topology needs to be performed in the future to validate the efficiency of the proposed topology.