Design Optimization and Control System of a Cascaded DAB–Buck Auxiliaries Power Module for EV Powertrains

Abstract

Auxiliary power demand in battery electric vehicles continues to increase as manufacturers transition toward multi-low-voltage architectures that combine 48 V and 12 V buses to improve load distribution flexibility and overall system efficiency. This paper evaluates several auxiliary power module (APM) architectures in terms of scalability, efficiency, complexity, size, and cost for supplying two low-voltage buses (e.g., 48 V and 12 V) from the high-voltage battery. Based on this assessment, a cascaded APM configuration is adopted, consisting of an isolated dual active bridge (DAB) converter followed by a non-isolated synchronous buck converter. A multi-objective optimization framework based on the NSGA-II algorithm is developed for the DAB stage to maximize efficiency and power density while minimizing cost. The optimized 13 kW DAB stage achieves a peak efficiency of 95% and a power density of 4.1 kW/L. For the 48 V/12 V buck stage, a 2 kW commercial GaN-based converter with a mass of 0.5 kg is used as the reference design, achieving a peak efficiency of 96.5%. Dedicated PI controllers are designed for both the DAB and buck stages using their respective small-signal models to ensure tight regulation of the two LV buses. The overall system stability is verified through impedance-based analysis. Experimental validation using a DAB prototype integrated with a multi-phase buck converter confirms the accuracy of the DAB loss modeling used in the design optimization framework as well as the control design implemented for the cascaded converters.

1. Introduction

Battery electric vehicles (BEVs) rely on a high-voltage (HV) battery to supply both traction and auxiliary loads. An isolated DC–DC converter—commonly referred to as the auxiliary power module (APM)—is therefore essential for delivering power to low-voltage (LV) auxiliaries and for charging the LV battery. Standard LV bus voltages include 12 V, 24 V, and 48 V [1]. As auxiliary power demand has increased, original equipment manufacturers (OEMs) have shifted from the legacy 12 V architecture to 24 V systems in order to reduce wiring losses in large buses and trucks [2]. More recently, OEMs have begun adopting 48 V systems to further improve efficiency [3].

Some OEMs, such as Tesla, have already transitioned to a fully standardized 48 V LV architecture [4]. Other manufacturers, however, continue to employ both 12 V and 48 V buses to support a broader range of auxiliary loads. This evolution in BEV auxiliary requirements, combined with the industry’s shift toward multi-LV APM architectures, introduces a key design challenge: selecting an APM topology that can scale to one or two LV buses while maximizing efficiency and minimizing both volume and cost.

In addition, an appropriate control strategy is required to ensure stability on each LV bus and to provide reverse power flow for the limp home operation, such as boosting power from the LV battery back to the HV bus during fault ride through.

This paper presents a hardware design optimization framework, along with control design and stability analysis, for a high-power (13 kW) multi-LV (12 V and 48 V) APM architecture intended for electric truck (E-Truck) applications. Figure 1 illustrates the BEV multi-LV architecture, highlighting the electrical buses, the distribution of auxiliary loads across buses, the power–electronic subsystems, and the principal power flow paths in a modern BEVs. To place this challenge in context, the following subsections review recent HV–LV converter studies and highlight the remaining research gaps.

1.1. State-of-the-Art HV-LV APM Topologies

The ISO 6469-3 standard states that galvanic isolation is a mandatory hardware feature in the APM topology [5]. Several HV–LV-isolated DC–DC converter topologies have been investigated in the literature. The flyback converter is widely adopted in automotive APM applications due to its simple design [6,7]. In [7], the authors proposed an integrated 3.6 kw on-board charger (OBC) and 1.8 APM using a multi-winding flyback transformer interfacing AC, HV, and LV ports within a single stage. The concept enables bidirectional power flow between HV and LV buses. However, the multi-winding architecture introduces complex magnetic coupling and control issues. In addition, a key drawback of flyback-based architectures is that the duty cycle must be limited to allow full demagnetization of the transformer core; otherwise, flux accumulation can cause saturation and increase current stress [8].

Recent studies on bidirectional HV–LV APM converters have focused on the phase-shifted dual active bridge (DAB) topology and the resonant LLC topology, both of which can achieve zero-voltage switching (ZVS) to improve efficiency. In [9], a 2.4 kW, 400 V→12 V DAB-based APM was presented, and the authors reported that the converter lost ZVS under light LV bus loading. This limitation, however, can be mitigated using advanced DAB modulation techniques, as demonstrated in [10,11,12]. In [13], a triple-active-bridge (TAB) converter was proposed for BEVs as an integrated OBC and APM interfacing AC/HV/LV ports to realize a 2 kW, 500 V → 15 V APM system. However, its main drawback is its relatively large footprint and the complex design of the TAB transformer.

In [14], a cascaded TAB–buck converter was proposed to integrate the OBC and APM functions. In this design, the TAB stage steps the 320 V HV bus down to an intermediate 58 V bus. The second stage, implemented as a synchronous buck converter, further regulates the 58 V intermediate bus to the final 14 V LV bus. A 1.2 kW prototype was developed, and the system achieved a peak efficiency of 95%.

In summary, isolated bidirectional converters with multiple voltage ports generally follow two main architectural approaches. The first uses a high-frequency transformer with dual or multiple secondary windings, as implemented in TAB converters and multi-winding flyback converters. The second approach is a cascaded architecture in which an isolated DC–DC stage steps down the HV bus to an intermediate bus voltage, followed by a non-isolated DC–DC stage that supplies the additional LV port. The same two architectural principles can be applied to multi-LV APM systems requiring HV, LV1, and LV2 ports.

Figure 2 presents two representative multi-LV APM architectures from the literature. Figure 2a uses a transformer with multiple secondary windings, as in TAB or multi-winding flyback designs, while Figure 2b employs a cascaded structure combining an isolated converter (typically DAB) with a non-isolated DC/DC stage (e.g., buck).

Table 1. Performance matrix to compare multi-LV APM topologies. Green indicates a favorable characteristic, while red indicates an unfavorable characteristic for the given topology.

Metric	Cascaded Topologies Using a Single Secondary Isolated Stage Followed by a Non-isolated DC–DC Stage	Transformer-Based Topologies with Multiple Secondary Windings	Reference
Bidirectional	Yes	Yes	[1]
Control complexity	High	Medium	[13,15]
Efficiency	Medium	High	[1]
Size	Smaller footprint	Larger footprint	[16]
Cost	High	Medium	[17]
Scalability	Single or Multi-LV	Fixed design	[1]

compares both options. The cascaded approach is selected for its flexibility and scalability, despite its higher control complexity.

1.2. Research Gap

Only a limited number of studies have examined BEVs that incorporate more than one regulated LV bus. Most existing research continues to focus on single-LV bus architectures, leaving the behavior of multi-LV systems and their interaction with the HV bus largely unexplored. Moreover, cascaded converters introduce notable control challenges [15,18,19]. In particular, a robust controller must manage highly dynamic loads on both LV buses, yet detailed impedance-based stability analyses of such cascaded architectures remain scarce in the literature.

1.3. Contributions of the Paper

This work contributes to the development of an optimized APM for BEV through the following key steps:

• A multi-objective hardware design optimization framework is developed for a high-power (13 kW) HV–48 V DAB converter, enabling the systematic selection of the bill of materials (BOM) to maximize efficiency and power density while minimizing cost.
• Detailed analytical models for losses, volume, and cost of the DAB converter are formulated and integrated into the optimization framework, allowing realistic comparison of candidate designs under electrical and thermal constraints.
• An impedance-based small-signal modeling and stability analysis methodology is derived for cascaded DAB–buck converters supplying dual low-voltage buses (48 V and 12 V), addressing the dynamic interaction and stability challenges inherent to multi-LV architectures.
• A structured controller design and tuning approach based on phase margin and crossover frequency constraints is proposed to ensure the stable voltage regulation of both low-voltage buses under dynamic load conditions

1.4. Paper Organization

Section 2 presents the DAB hardware optimization tool. Section 3 develops the impedance-based stability model and designs the digital controllers for the DAB and buck stages. Section 4 provides the experimental validation. Section 5 concludes the paper and outlines future work.

2. Hardware Design Optimization

2.1. BEV Auxiliary Loads

Table 2. Typical E-Truck auxiliary loads and average power rating [20,21,22,23].

Load	Power Rating (kW)	SOTA Supply Voltage
Refrigerant compressor for HVAC and battery chiller systems	3.4	HV
HVAC Cabin Air Blower	0.1	LV
HVAC Cabin PTC Heater	2.4	HV
Battery PTC Heater	2	HV
Cooling pumps for Electric Drive and Battery	1	LV
Breaking motors	0.3	LV
Electric Power Steering (EPS)	2	LV
Anti-Lock Braking System (ABS)	0.2	LV
Wipers	0.2	LV
Power seats	0.3	LV
Heating seats	0.1	LV
lamps	0.1	LV
Horn	0.1	LV
Infotainment system	0.1	LV
GBS	0.05	LV
Speakers	0.2	LV
Advanced Driver Assistance System (ADAS)	0.6	LV
Interior lighting	0.02	LV
Total APM Power Rating	13 kW

summarizes typical BEV auxiliary loads [20,21,22,23]. The heating, ventilation and air conditioning (HVAC) system and HV battery thermal management system (TMS) are the most power-demanding, consuming up to 7.8 kW across the compressor and positive temperature coefficient (PTC) heaters. The next largest load is the electric power steering (EPS), rated at 2 kW, which is particularly critical in E-Trucks due to the higher steering force requirement.

In practice, some auxiliaries are powered directly from the HV bus, such as the HVAC system compressor and PTC Heaters [24,25], while others are supplied from the LV bus. In this work, it is assumed that all auxiliary loads are supplied from the 48 V bus, ensuring system functionality under HV battery fault condition. Under this assumption, the DAB stage is rated for the full 13 kW auxiliary load demand.

2.2. Equivalent Circuit Diagram

Figure 3 shows the detailed circuit diagram of the APM system. Several studies have addressed the hardware design optimization of the DAB converter [26,27,28,29] and the buck converter [3,30,31,32]. Reported frameworks typically target efficiency, power density, cost, and, in some cases, reliability. In this work, a dedicated optimization tool was developed for the DAB stage to maximize efficiency and power density while minimizing cost. The buck stage was not included in the optimization. Instead, a 48 V/12 V automotive rated synchronous interleaved buck converter using a Gallium Nitride (GaN)-based Field Effect Transistors (FETs), as presented in [33], was adopted as the reference design. This converter delivers 2 kW, weighs 0.5 kg, and operates at 500 kHz with a peak efficiency of 96.5%, ensuring optimal efficiency and power density for the overall cascaded converter design.

The DAB converter stage is composed of the primary H-Bridge (HB1) switching semiconductor devices ($Q_1-Q_4$), the secondary H-Bridge (HB2) switching semiconductor devices ($Q_5-Q_8$), the DAB power inductor ($L_{DAB}$), and the isolating transformer with turns ratios ($1:n$), where $n$ is the ratio of the secondary winding to the primary winding ($n=N_s/N_p$). The DAB stage also includes the input and output DC-link capacitors ($C_1,C_2$) with their equivalent series resistances (ESR) ($r_{C1},r_{C2}$). The parasitic resistance of the inductor ($r_{LDAB})$ and the winding resistances of the transformer ($r_{wp},r_{ws}$) are combined into the equivalent resistance ($r_{eq})$, which is defined as shown in Equation (1).

$$r_{eq}=r_{LDAB}{+r}_{wP}+{\displaystyle \frac{r_{swS}}{n^2}}$$

(1)

The two-phase interleaved buck–boost stage consists of switching devices ($Q_9-Q_{12}$), two identical power inductors ($L_{Buck}$) with parasitic resistances ($r_{LBuck}$), an input filter capacitor ($C_3)$ with its ESR ($r_{C3}$), and an output filter capacitor ($C_4)$ with its ESR $(r_{C4}$).

2.3. DAB Multi-Objectives Hardware Optimization Framework

Figure 4 demonstrates the hardware design optimization framework of the DAB stage. The Non-dominated Sorting Genetic Algorithm (NSGA-II) is employed to solve a multi-objective and constrained design optimization problem. NSGA-II is well-suited for discrete and nonlinear optimization problems, particularly in applications such as multi-objective optimization in power electronics [34]. The objective of the framework is to enable the design selection of the transformer, inductor, input/output filter capacitors, and the optimum switching frequency of the DAB converter.

First, HV and LV switching devices are selected based on voltage and current rating requirements. The datasheets parameters of the selected devices are included in the optimization framework database. The second step is to load a reference database of ferrite cores ($N_{core}$) for sizing the DAB transformer and inductor.

Table 3. Ferrite core material database parameters extracted from the PExprt magnetic design tool.

Type	${\mathit{f}}_{\mathit{s}\mathit{w}\hspace{0.17em}\mathit{M}\mathit{i}\mathit{n}}$ $\left[\mathbf{k}\mathbf{H}\mathbf{z}\right]$	${\mathit{f}}_{\mathit{s}\mathit{w}\hspace{0.17em}\mathit{M}\mathit{A}\mathit{x}}$ $\left[\mathbf{k}\mathbf{H}\mathbf{z}\right]$	${\mathit{B}}_{\mathit{s}\mathit{a}\mathit{t}}$ $\left[\mathbf{T}\right]$	${\mathit{\mu }}_{\mathit{r}}$	${\mathit{K}}_{\mathit{i}}$	${\mathit{K}}_{\mathit{f}\mathit{e}}$	$\mathit{\alpha }$	$\mathit{\beta }$
N87	10	500	0.39	2200	0.02	0.03	1.78	2.62
N97	10	500	0.41	2300	0.02	0.01	1.86	2.47

lists the parameters of Epcos N87 and N97 ferrites, extracted from the Ansys PExprt magnetic design tool. The ferrite materials satisfy a 10–500 kHz switching frequency range while maintaining low core losses. ${\mu }_r$ is the core material relative permeability. $\alpha , \beta , k_i$, and $k_{fe}$ are coefficients for core loss estimation using the Steinmetz equation [35]. $B_{Sat}$ is the core saturation flux density.

Figure 4 illustrates the overall structure of the proposed NSGA-II-based optimization framework, highlighting the interaction between component databases, design variables, constraints, and optimization objectives.

The final step is to load the database of DC-link filter capacitors into the design optimization tool. For the HV side, film capacitors ($N_{HV Capacitor}$) are the suitable choice due to their high voltage capability [34]. On the LV side, either aluminum electrolytic or film capacitors can be utilized ($N_{LV Capacitor}$). Both technologies differ in terms of cost, size, and ESR value for the same capacitance rating. The capacitor sizing is governed by the required peak-to-peak voltage ripple limit ($\Delta V_{pp}$), the capacitor RMS ripple current, and the switching frequency.

2.4. DAB Semiconductor Selection for the HV and LV Sides

Based on the 13 kW DAB power rating and the nominal bus voltages of 700 V (HV) and 48 V (LV), 1200 V/30 A devices were chosen for the HV side H-Bridge, and 100 V/90 A devices for the LV side H-Bridge, ensuring appropriate voltage and current margins. On the LV side, switch paralleling (e.g., four parallel devices) is employed to reduce conduction losses, enhance current sharing, and improve thermal performance.

The HV H-Bridge requires devices with high blocking voltage capability, making Silicon (Si)-based Insulated Gate Bipolar Transistors (IGBTs) and Silicon Carbide (SiC)-based Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) the most suitable candidates due to their high breakdown voltage capabilities. Conversely, the LV H-Bridge operates at much lower voltage levels, where Si MOSFETs and GaN FETs are the suitable choice with low breakdown voltage capabilities [36]. Although studies have demonstrated the use of series-connected GaN or MOSFET devices to achieve higher blocking voltages [37], this approach is beyond the scope of this paper.

According to comprehensive evaluations reported in the literature [36,38,39], wide bandgap (WBG) semiconductor technologies such as SiC MOSFET and GaN FET outperform silicon-based devices (Si IGBTs and Si MOSFETs) in terms of efficiency and achievable switching frequency. Therefore, in this work, SiC MOSFETs (E3M0075120K, 1200 V/30 A) are selected for the HV H-Bridge, while GaN FETs (EPC7018, 100 V/90 A) are selected for the LV H-Bridge.

2.5. Formulation of Objective Function and Constraints

The multi-objectives optimization problem aims to maximize efficiency ($\eta [\%]$), power density (γ[kW/L]), and minimize cost ($€$). Equation (2) formulates the three objectives, where negative signs are applied to efficiency and power density since NSGA-II minimizes objective functions. Equation (3) defines the design variables, and (4) specifies their constraints. Equation (5) introduces the penalty limits; designs with capacitor voltage ripple $\Delta V_{pp}$ exceeding LV123 (HV) or LV148 (LV) standards limits are rejected. Any core with window utilization $k_u$ bigger than 0.4, or temperature rise above 100 °C is excluded, as well as designs requiring more than ten parallel capacitors ($N_{Capacitor}$) from the database.

$$\underset{x}{\min }\left\{\begin{array}{c}obj,f\left(1\right)=-\left({\displaystyle \frac{P_{DAB}}{P_{DAB}+P_{Loss DAB}}}\right)\\ obj,f\left(2\right)=-{\displaystyle \frac{P_{DAB}}{Volume DAB}}\\ obj,f\left(3\right)={€}_{DAB}\end{array}\right.$$

(2)

$$x=[f_{sw}, id{x}_{coreTf}, id{x}_{coreInd}, id{x}_{CapHV}, id{x}_{CapLV}]$$

(3)

$$subject to: \left\{\begin{array}{c}{f}_{s{w}_{MIN}}\le f_{sw}\le f_{s{w}_{MAX}}\\ id{x}_{core TF/Ind}\le N_{Core}\\ id{x}_{CapHV}\le N_{HV Capacitor}\\ id{x}_{CapLV}\le N_{LV Capacitor}\end{array}\right.$$

(4)

$$Penalty: \left\{\begin{array}{c}\Delta V_{HV pp}>0.05\ast V_{HV}\\ \Delta V_{LV1 pp}>1 \mathrm{V}\\ k_{u Tf/Ind}>0.4\\ T_{core rise}>{100}^{ °}\mathrm{C}\\ N_{Capacitor}>10\end{array}\right.$$

(5)

The multi-objective optimization problem defined in Equations (2)–(5) is solved using the NSGA-II algorithm. Each individual in the population represents a candidate design vector $x$ as defined in Equation (3). For every candidate, the DAB steady-state waveforms are constructed, from which currents, losses, volume, and cost are computed, allowing direct evaluation of the objective functions in Equation (1). The constraints in Equation (4) are enforced using a rejection-based approach: any candidate violating voltage ripple limits, magnetic utilization limits, thermal limits, or capacitor count constraints is discarded from the feasible population. NSGA-II ranks the remaining candidates using non-dominated sorting and crowding distance, and iteratively evolves the population until convergence, resulting in a Pareto set of feasible designs.

The key design variable is the switching frequency of the DAB converter. The lower limit ($f_{s{w}_{MIN}}$) is set by the magnetic core minimum limits to avoid saturation [35]. The upper limit ($f_{s{w}_{MAX}})$ is constrained by the thermal capability of the switches. Since SiC devices exhibit higher switching energies than GaN, $f_{s{w}_{MAX}}$ is defined by the SiC limit. Equation (6) shows the maximum losses in the SiC switch to raise the junction temperature from 25 °C to the maximum junction temperature limit ($T_{jMax})$. $R_{\theta J-C}$ is the SiC switch junction-to-case thermal resistance from the datasheets. The typical losses are classified into conduction losses and switching losses. The conduction losses are governed by the load current ($I_M$) and the on-state resistance ($r_{dson}$), as shown in Equation (7). The maximum switching losses limiting the temperature increase to $T_{jMax}$ can be estimated as in Equation (8). The switching losses depend on the turn-on $\left(E_{sw,On (I_M, V_{DS},T_{jMax})}\right)$ and turn-off ${(E}_{sw,Off (I_M, V_{DS},T_{jMax})})$ energies. Both the on-state resistance and the switching energies are extracted from the device datasheet and scaled to the rated voltage, current, and operating temperature conditions. Finally, the maximum switching frequency limit can be estimated as shown in Equation (9) as function of the maximum switching losses limit and the turn on/off energies of the switch.

$$P_{M LossMax}={\displaystyle \frac{T_{jMax}-25}{R_{\theta J-C}}}$$

(6)

$$P_{M Cond Max}=I_M^2 r_{dson (I_M,T_{jMAx})}$$

(7)

$$P_{M Sw Max}=P_{M Loss Max}-P_{M Cond Max}$$

(8)

$$f_{sw Max}={\displaystyle \frac{P_{M Sw Max}}{E_{sw,On (I_M, V_{DS},T_{jMax})}+E_{sw,Off(I_M, V_{DS},T_{jMAx})}}}$$

(9)

For the selected SiC switch, the maximum allowable switching frequency was estimated to be 75 kHz. The lower boundary of the switching frequency range used in the optimization was set to 10 kHz according to the core minimum limits, as shown in Table 3.

After evaluating all the feasible designs using the defined objective functions and constraints, the NSGA-II algorithm generates a Pareto front representing the trade-off between efficiency, power density, and cost. To obtain a single optimal solution, the objective functions are first normalized, and an ideal reference point corresponding to maximum efficiency and power density, and minimum cost is defined. The Euclidean distance between each Pareto-optimal solution and this ideal point is computed, and the design with the minimum distance is selected as the final optimal solution.

2.6. Modeling, Design, and Operation of DAB Stage

Figure 5 shows the switching waveforms of the DAB stage in forward power flow (HV → LV1) mode. The transformer steps down from HV to LV1. The power flow control uses time-varying voltages ($v_{ac1}$) and ($v_{ac2}$) across the inductor ($L_{DAB}$) with phase shift angle ($\varphi$) between them. A positive phase shift angle causes forward power flow (HV → LV1), while a negative phase shift angle causes reverse power flow (LV1→HV). The signals $u_1\left(t\right)$ and $u_2\left(t\right)$ represent the PWM signals for the primary and secondary H-Bridges, respectively, which are square waves with a 50% duty cycle in the case of single-phase shift (SPS) modulation technique.

The phase shift angle $\varphi$ is represented in time domain as a time delay between HB1 and HB2 with the variable $D$, where $D={\displaystyle \frac{\varphi }{\pi }}$. The current in the body of the MOSFET switching semiconductor is $i_S\left(t\right)$, while the current component in the freewheeling diode is $i_D\left(t\right)$. $i_L\left(t\right)$ is the inductor current, $v_L\left(t\right)$ is the inductor voltage, and $t_D$ is the dead time. Equation (10) shows the power flow control equation of DAB as a function of the phase shift variable ($D$), the converter switching frequency ($f_{sw}$), the inductance ($L_{DAB})$, the HV side voltage ($V_{HV})$, and LV1 side voltage ($V_{LV1}$) [40]. The transformer turns ratio (n) is fixed as the ratio between the nominal voltage of the HV bus and the LV1 bus, as shown in Equation (11).

The minimum inductor size to transfer the power can be estimated as shown in Equation (12) [41]. $D$ can be controlled in the range $(-0.5\le D\le 0.5)$ for the bidirectional power control of the DAB converter $(-P_{Max}\le P_{DAB}\le P_{Max})$. Increasing $D$ requires a larger inductor and expands the ZVS range. According [18,40,42], the optimal D falls within the 0.25–0.33 range, and in this study, D is fixed at 0.25.

The dead time ($t_D$) and SiC output capacitance ($C_{OSS}$) are correlated. Dead time is used to prevent short circuits between the two complementary switches. It also plays a key role in enabling ZVS, allowing the switch’s output capacitance to discharge during turn-off. The required dead time is determined by Equation (13) [43].

$$P_{DAB}={\displaystyle \frac{V_{HV} V_{LV1}D (1-D)}{2 n L_{DAB} f_{sw}}}$$

(10)

$$n={\displaystyle \frac{V_{LV1 Nom}}{V_{HV Nom}}}$$

(11)

$$L_{DAB}={\displaystyle \frac{V_{HV} V_{LV1} D (1-D)}{2 n P_{DAB} f_{sw}}}$$

(12)

$$t_D={\displaystyle \frac{\pi \sqrt{L_{DAB}{C}_{OSS}}}{2}}$$

(13)

The capacitor design is based on Equation (13) [44], where $\Delta Q$ denotes the accumulated charge during filtering. The capacitor current ($i_C$) is obtained by subtracting the DC component ($I_{HV} \mathrm{o}\mathrm{r} I_{LV1}$) from the corresponding H-Bridge current ($i_{HB1} or i_{HB2})$, as illustrated in Figure 5. For each switching frequency in the optimization iterations, the inductor current waveform is first constructed, from which the input/output capacitor current waveforms are derived. The capacitor RMS current ($I_{C RMS})$ is then evaluated over one switching cycle, and the required capacitance is calculated using Equation (14).

The capacitor sizing depends on three factors: the required capacitance, the required RMS current rating, and the maximum allowable ESR. The ESR affects both capacitor losses and voltage ripple. The maximum ESR is determined using Equation (15), which corresponds to the value that produces the maximum voltage ripple under the worst-case transient in the load DC current. The design optimization tool combines multiple capacitors from the database as needed to meet the capacitance, RMS current, and ESR requirements.

$$C={\displaystyle \frac{\Delta Q}{\Delta V_{pp}}}={\displaystyle \frac{\max \left(\frac{1}{T_s}{\int }_0^{T_s}{i}_C dt\right)-\mathrm{m}\mathrm{i}\mathrm{n}\left(\frac{1}{T_s}{\int }_0^{T_s}{i}_C dt\right)}{\Delta V_{pp}}}$$

(14)

$$ES{R}_{MAX}={\displaystyle \frac{\Delta V_{pp}}{2 I_{DC}}}$$

(15)

Equations (16)–(25), adopted from [42] are used to estimate the inductor RMS current ($I_{L_{RMS}})$ and the average current of the SiC and GaN. Both devices support bidirectional conduction when the gate is on. Although GaN lacks a body diode, it can still conduct in the third quadrant via self-commutation in reverse conduction mode, as discussed in [45]. In this mode, the GaN transistor conducts with the gate off in the reverse direction. However, the GaN forward on-state and reverse on-state resistances differ, with the reverse on-state being significantly higher. M is the DAB voltage gain and is kept constant (M = 1) in the optimization.

$$I_1={\displaystyle \frac{V_{HV}}{4L_{DAB} f_{swDAB}}} \left(M+\left(2D-1\right)\right)$$

(16)

$$I_2={\displaystyle \frac{V_{HV}}{4L_{DAB} f_{swDAB}}} \left(1+M\left(2D-1\right)\right)$$

(17)

$$t_z={\displaystyle \frac{(n V_{HV}+V_{LV1}\left(2D-1\right))}{4 f_{sw} (n V_{HV}+V_{LV1})}}$$

(18)

$$I_{L_{RMS}}=\sqrt{{\displaystyle \frac{2}{T_{sw}}}\left[\begin{array}{c}{\displaystyle \frac{I_1^2}{3}}\left({\displaystyle \frac{D{T}_{sw}}{2}}-t_z\right)+\\ \left({\displaystyle \frac{T_{sw}}{2}}-{\displaystyle \frac{D{T}_{sw}}{2}}\right)\left(I_1^2+{\displaystyle \frac{{\left(I_2-I_1\right)}^2}{3}}+I_1\left(I_2-I_1\right)\right)\\ +{\displaystyle \frac{I_2^2 t_z}{3}}\end{array}\right]}$$

(19)

$$I_{M,RMS,HV}=\sqrt{{\displaystyle \frac{1}{T_{sw}}}\left[\begin{array}{c}{\displaystyle \frac{I_1^2}{3}}\left({\displaystyle \frac{D{T}_{sw}}{2}}-t_z\right)+\\ \left({\displaystyle \frac{T_{sw}}{2}}-{\displaystyle \frac{D T_{sw}}{2}}\right)\left(I_1^2+{\displaystyle \frac{{\left(I_2-I_1\right)}^2}{3}}+I_1\left(I_2-I_1\right)\right)\end{array}\right]}$$

(20)

$$I_{D,RMS,HV}=I_2\sqrt{{\displaystyle \frac{t_D}{T_{sw}}}}$$

(21)

$$I_{D,Avg,HV}={\displaystyle \frac{I_2}{T_{sw}}} t_D$$

(22)

$$I_{M,RMS,LV1}={\displaystyle \frac{I_{M_{RMSHV}}}{n}}$$

(23)

$$I_{D,RMS,LV1}={\displaystyle \frac{I_1}{n}}\sqrt{{\displaystyle \frac{t_D}{T_{sw}}}}$$

(24)

$$I_{D,Avg,LV1}={\displaystyle \frac{I_1}{{n T}_{sw}}} t_D$$

(25)

2.7. DAB Analytical Losses Modeling

The total DAB losses $\left(P_{DAB,Loss}\right)$ include contributions from the two H-Bridges $(P_{HB1}, P_{HB2})$, the inductor losses $\left(P_{L_{\mathrm{DAB}}}\right)$, the transformer losses $\left(P_{\mathrm{Tf}}\right)$, and the input/output capacitor losses $(P_{C1},P_{C2})$. All semiconductor loss parameters are extracted from the manufacturer datasheets and scaled to the rated current, rated voltage, and the operating temperature following the methodology in [46]. Equations (26)–(32) present the analytical loss model of the DAB H-Bridges [27,40,45]. The ambient temperature ($T_{\mathrm{Amb}}$) is fixed at $25$ °C.

The HB1 losses ($P_{HB1})$ include the SiC MOSFET conduction loss ($P_{M,HB1,Cond}$), the anti-parallel diode conduction loss ($P_{D,HB1,Cond}$), and the SiC MOSFET switching losses $(P_{M,HB1,Sw}$). $P_{M,HB1,Cond}$ is determined by the on-state resistance ($r_{\mathrm{dson},\mathrm{SiC}}$). $P_{D,HB1,Cond}$ is modeled using the on-state forward voltage drop ($v_{\mathrm{fwd}}$) and resistance $(r_{\mathrm{fwd}}$). The diode reverse recovery energy $\left(E_{\mathrm{rr}}\right)$ is neglected because of its small magnitude. $P_{M,HB1,Sw}$ consists of the turn-off switching energy $(E_{Off, SiC}$). Since ZVS is achieved at the rated operating point, the turn-on energy ($E_{On, SiC}$) is assumed to be zero [40].

The HB2 losses ($P_{HB2})$ include the GaN FET forward on-state conduction losses ($P_{M,HB2,Cond}$), the switching losses ($P_{M,HB2,Sw}$), and the on-state reverse conduction losses during the dead-time period $\left(P_{Dead,HB2}\right)$. $P_{M,HB2,Cond}$ is estimated using the GaN on-state resistance $\left(r_{\mathrm{dson},\mathrm{GaN}}\right)$. Since GaN devices do not contain a physical anti-parallel diode, reverse conduction during the dead-time period ($P_{Dead,HB2})$ occurs through the channel, which is represented using the on-state conduction resistance in reverse $\left(r_{dson,rev,GaN}\right)$. $P_{M,HB2,Sw}$ includes the turn-off energy $\left(E_{Off, GaN}\right)$. The turn-on energy ($E_{On, GaN}$) is assumed to be zero under ZVS.

$$P_{DAB,Loss}=P_{HB1}+P_{HB2}+P_{LDAB}+P_{Tf}+P_{C1}+P_{C2}$$

(26)

$$P_{HB1}=P_{M,HB1,Cond}+P_{M,HB1,Sw}+P_{D,HB1,Cond}$$

(27)

$$P_{HB2}=P_{M,HB2,Cond}+P_{M,HB2,Sw}+P_{Dead, HB2}$$

(28)

$$P_{M,Cond}=\left\{\begin{array}{c} 4 I_{M,RMS,HV}^2 r_{dson,SiC }\left(I_{M,RMS,HV}, T_{Amb}\right), HB1\\ 4 I_{M,RMS,LV1}^2 r_{dson,GaN }(I_{M,RMS,LV1}, T_{Amb}), HB2\end{array}\right.$$

(29)

$$P_{M,Sw}=\left\{\begin{array}{c} 4 \left( E_{Off,SiC }\left(V_{HV}, I_{M,RMS,HV},T_{Amb}\right) \right) f_{swDAB}, HB1\\ 4\left( E_{Off,GaN }\left(V_{LV1}, I_{M,RMS,LV1},T_{Amb}\right)\right)f_{swDAB}, HB2\end{array}\right.$$

(30)

$$P_{D,HB1,Cond}=4 (I_{D,RMS,HV}^2 r_{fwd }\left(I_{D,RMS,HV},T_{Amb}\right)+I_{D,Avg,HV }{v}_{fwd}(I_{D,Avg,HV}, T_{Amb}\left)\right)$$

(31)

$$P_{Dead, HB2}=4 I_{D,RMS,LV1}^2 r_{dson,rev,GaN} (I_{M,RMS,LV1},T_{Amb})$$

(32)

Equations (33)–(36) describe the inductor and transformer loss models. The winding resistance of both components consists of a DC component, arising from the copper conductor, and an AC component, caused by skin and proximity effects [35]. Litz wire conductors are used for the windings to minimize AC losses. The DC and AC resistance components are calculated based on the selected wire gauge, the number of parallel strands, and the number of winding layers, following the methodology presented in [47].

The inductor loss model ($P_{LDAB})$ includes both winding resistive losses and core losses. The winding losses are calculated using the equivalent winding resistance ($r_{L_{\mathrm{DAB}}})$. The core losses are evaluated using the Steinmetz equation [35], with material coefficients corresponding to the selected ferrite core (listed in Table 3), and are expressed as a function of the inductor core volume ($V_{c,LDAB}$) and the maximum inductor flux density ($B_{Max{,L}_{DAB}}$). The inductor is an energy storage element and therefore requires an intentional air gap to prevent core saturation [35]. The air gap losses are computed as a function of the core loss coefficient $\left(k_i\right)$, the core depth ($E_{LDAB})$, and the air gap length ($l_{g,LDAB})$. $B_{Max{,L}_{DAB}}$ is derived from the winding number of turns $\left(N_L\right)$, the inductor core cross-sectional area $\left(A_{c,LDAB}\right)$, and the peak current ($I_{peak}$). $I_{peak}$ is the maximum value of $I_1$ and $I_2$, as estimated in Equations (15) and (16).

The transformer loss model ($P_{Tf})$ includes the primary and secondary winding resistive losses ($r_{\mathrm{wp}}$ and $r_{\mathrm{ws}}$) as well as the transformer core losses computed using the same Steinmetz formulation as function of the transformer core volume $\left(V_{c,Tf}\right)$, and the maximum transformer flux density ($B_{Max,Tf}$). $B_{Max,Tf}$ is obtained using the primary winding number of turns ($N_P$) and the transformer core cross-sectional area ($A_{c,Tf})$ [48].

The capacitor losses model ($P_C)$ is shown in Equation (37), where $r_c$ is the total ESR of the capacitors connected in parallel.

$$P_{LDAB}=I_{L_{RMS}}^2 r_{LDAB}+ k_{fe} f_{swDAB}^{\alpha } B_{Max,LDAB}^{\beta } V_{c,LDAB}+k_i E_{LDAB} l_{g,LDAB} f_{swDAB}{B}_{Max,LDAB}^2$$

(33)

$$B_{Max,LDAB}={\displaystyle \frac{L_{DAB}{I}_{peak}}{N_L A_{c,LDAB}}}$$

(34)

$$P_{Tf}=I_{L_{RMS}}^2 \left(r_{wp}+{\displaystyle \frac{r_{ws}}{n^2}}\right)+k_{fe} f_{swDAB}^{\alpha } B_{Max,Tf}^{\beta } V_{c,Tf}$$

(35)

$$B_{Max,Tf}={\displaystyle \frac{V_{HV}}{4 f_{swDAB} N_P A_{c,Tf}}}$$

(36)

$$P_C=I_{CRMS}^2 r_C$$

(37)

2.8. DAB Power Density Modeling

The second objective is to maximize the power density $\left(\gamma \right)$ in kW/L, defined as the ratio of the DAB output power to the total converter volume ($V_{DAB})$. Equations (38)–(42) show the volume components of the DAB converter, where $V_{\mathit{semic}},V_{LDAB},V_{C1, C2},V_{\mathrm{Tf}}$, and $V_{Heatsink}$ represent the volumes of the switching semiconductors, inductor, transformer, capacitors, and heatsink, respectively.

The volumes of the semiconductors, magnetic cores ($V_{c,LDAB}$ and $V_{c,Tf}$), and capacitors ($V_{C1, C2})$ are obtained from their datasheets. The heatsink volume ($V_{\mathit{heatsink}})$ is predefined according to the selected cooling method (e.g., liquid cooling) and provided as an input to the optimization tool. The winding volumes of the inductor $\left(V_{w,LDAB}\right)$ and transformer $\left(V_{w,Tf}\right)$ are calculated from the number of turns and the cross-sectional area of the selected Litz wire. $V_{w,LDAB}$ is estimated as function of the average turn length of the inductor core ($l_{LDAB,turn})$, the conductor cross-sectional area ($A_{LDAB,cu})$, and the number of turns ($N_L)$. $V_{w,Tf}$ is estimated as a function of the average turn length of the transformer core ($l_{Tf,turn}$), the conductor cross-sectional areas of the primary and secondary windings ${(A}_{p,cu}$, $A_{s,cu}$), and the primary and secondary windings number of turns ($N_P,N_S$).

$$V_{DAB}=V_{Semic}+V_{LDAB}+V_{TF}+V_{C1, C2}+V_{Heatsink}$$

(38)

$$V_{LDAB}=V_{c,LDAB}+V_{w,LDAB}$$

(39)

$$V_{TF}= V_{c,Tf}+V_{w,Tf}$$

(40)

$$V_{w,LDAB}=l_{LDAB,turn} A_{LDAB,cu} N_L$$

(41)

$$V_{w,Tf}= l_{Tf,turn} {(A}_{p,cu} N_p+A_{s,cu} N_s)$$

(42)

2.9. DAB Cost Modeling

The third objective is to minimize the total converter cost (€), as defined in Equation (43) The costs of the semiconductors (€_Semic), capacitors (€_C1,C2), and heatsink (€_Heatsink) are obtained directly from market prices. The inductor cost $\left({€}_{L_{\mathrm{DAB}}}\right)$ and transformer cost (€_Tf) are estimated using modified empirical cost models adapted from [49], as expressed in Equations (44)–(47). The model coefficients from [49] are adjusted to represent the cost of a single manufactured unit, rather than the original minimum order quantity (>1000 units) assumed in [49]. Furthermore, since [49] presented the model only for inductors, the transformer cost model is extended by including the additional costs of design complexity and insulation between primary and secondary windings.

Table 4. Empirical cost model coefficients, adopted from [49].

Parameter	Value
$a$ ($€/\mathrm{k}\mathrm{g}$)	5.5
$b$ ($€/\mathrm{k}\mathrm{g}$)	7
$c$ ($€/\mathrm{k}\mathrm{g}$)	10
$K_L$ (-)	40
$K_{Tf}$ (-)	26
${\rho }_{cu}$ (kg$/{\mathrm{m}}^3$)	8940

lists the applied cost model coefficients.

In the adopted cost model, the inductor and transformer costs are expressed as functions of the core weights $(W_{c,LDAB},W_{c,Tf})$ and the winding weights $(W_{w,LDAB}, W_{w,Tf})$. The core weights are obtained from the manufacturer’s datasheets. The winding weights are calculated from the copper density (${\rho }_{cu})$ and the total winding volume ($V_{w,LDAB}$, $V_{w,Tf}$), where the winding volumes are estimated using Equations (41) and (42).

The cost model is validated by comparing the predicted costs of the transformer and inductor with the actual manufacturing costs obtained from a supplier.

$${€}_{DAB}={€}_{Semic}{+€}_{LDAB}+{€}_{TF}+{€}_{C1,C2}+{€}_{Heatsink}$$

(43)

$${€}_{LDAB}=k_L (3+(a+b)W_{c,LDAB}+{c W}_{w,LDAB})$$

(44)

$${€}_{Tf}=k_{Tf} (15+(a+b)W_{c,Tf}+{c W}_{w,Tf})$$

(45)

$$W_{w,LDAB}={\rho }_{cu} V_{w,LDAB}$$

(46)

$$W_{w,Tf}={\rho }_{cu} V_{w,Tf}$$

(47)

2.10. DAB Design Optimization Results

Figure 6 details the step-by-step optimization workflow, from database initialization and constraint evaluation to NSGA-II evolution and final Pareto-based design selection.

Table 5. DAB optimization input parameters.

Parameter	Symbol	Value/Range
HV nominal voltage	$V_{HV}$	700 V
HV H-Bridge semiconductors	(Q1–Q4)	SiC MOSFET (E3M0075120K, 1200 V/30 A)
LV nominal voltage	$V_{LV}$	48 V
LV H-Bridge semiconductors	(Q5–Q8)	GaN FET 4× (EPC7018, 100 V/90 A)
Rated output power	$P_{Max}$	13 kW
Phase shift variable	D	0.25
Transformer turns ratio	n = ${\displaystyle \frac{V_{LV}}{V_{HV}}}$	0.068
Switching frequency bounds	$f_{sw,min-max}$	10–75 kHz
Input voltage ripple limit	${\Delta V}_{HV Max}$	$35 \mathrm{V}$
Output voltage ripple limit	${\Delta V}_{LV Max}$	$1 \mathrm{V}$
Ambient temperature	Tamb	25 °C
Max allowed core temperature rise	Trise	100 °C
Cooling method	-	Liquid
Inductor ferrite core database index range	${\mathit{id}}_{core\hspace{0.17em}L}$	1… 15
Transformer ferrite core database index range	${\mathit{id}}_{core\hspace{0.17em}Tf}$	1… 15
HV capacitor database index range	${\mathit{id}}_{input\hspace{0.17em}Cap}$	1… 9
LV capacitor database index range	${\mathit{id}}_{output\hspace{0.17em}Cap}$	1… 19
Heatsink volume	-	9.5 × 17.5 × 4 mm3
Heatsink cost	-	100 €

summarizes all input parameters and search space limits used by the multi-objective NSGA-II algorithm. Figure 7 shows the resulting Pareto front obtained from the multi-objective optimization. The optimal design is selected using the Euclidean distance method, where efficiency, power density, and cost are each normalized between zero and one. The best compromise corresponds to the point with the shortest distance to the ideal reference (maximum efficiency and power density, and minimum cost). The corresponding Pareto-optimal solution is highlighted in Figure 7, and its design parameters are reported in

Table 6. DAB hardware design optimization results.

Parameter	Value
$f_{swDAB}$	25 kHz
$L_{DAB} size$	$140 \mathsf{\mu }\mathrm{H}$
$L_{DAB} Core$	E/E 40/16/12
$L_{DAB} Number of Turns \left(N_L\right)$	18
$Transformer Core$	E/E 65/32/27
Transformer number of turns ($N_p:N_s$)	28:2
HV DC filter capacitor size and technology $\left(C1\right)$	$2\times 5 \mathsf{\mu }\mathrm{F}$ (Film Capacitor) rc: 3 mOhm
LV1 filter capacitor size and technology $\left(C2\right)$	$6\times 560 \mathsf{\mu }\mathrm{F}$ (Electrolyte Capacitor) rc: 1.1 mOhm
Power Density ($\mathrm{kw}/\mathrm{L}$)	4.17
Cost (${€}_{DAB}$)	7152
Peak Efficiency (%)	95%

. To verify that the obtained Pareto front is not dependent on random initialization, the optimization was executed in three independent runs. All runs produced consistent fronts with minimal variation, confirming the robustness of the results.

3. Control Design and Stability Analysis

The control design of cascaded power electronic converters is inherently challenging due to the dynamic interactions between stages. In this work, a frequency-domain design methodology is adopted. The primary requirement is to ensure robust voltage regulation of both the 48 V bus and the 12 V bus, with a maximum overshoot limited to 10%. According to standard control theory, this performance specification corresponds to a minimum required phase margin (PM) $\ge$ 60° for both the DAB voltage controller and the buck voltage controller [50].

Secondly, since the output dynamics of the DAB stage act as the input dynamics of the buck stage, the overall cascaded system is stable if the closed-loop output impedance of the DAB remains smaller than the closed-loop input impedance of the buck stage, i.e., $\left|Z_{outDAB,CL}\left(s\right)\right|<\left|Z_{inBuck,CL}\right(s\left)\right|$, in accordance with the Middlebrook stability criterion [51].

The first step in order to design the right PI compensators is to implement the linearized small-signal models of the DAB and buck stages. In the next subsections, the control design of each stage and the stability analysis will be presented.

3.1. DAB Stage Control Design

Figure 8 illustrates the small-signal model of the DAB stage based on the reduced-order modeling approach [18,51,52]. The dependent current source components, $g_1$, $g_2$, and $g_3$, are derived in [51] and expressed in Equations (48)–(50). The open-loop output impedance of the DAB, $Z_{outDAB,OL}\left(s\right),$ is given in Equation (51). $R_{LV1}$ denotes the equivalent load of the DAB at the maximum power of 13 kW, while the buck-stage input current is represented as a perturbation current source, $i_{LV2in}$.

Figure 9 shows the linearized block diagram of the DAB stage used for control design. $H_v\left(s\right)$, defined in Equation (52), represents the DC voltage sensor transfer function, where $f_{BWv}$ is the sensor bandwidth. The term $e^{-s T_d}$ models the delay introduced by sampling, computation, feedback delay, and PWM modulation. In this work, the total delay is approximated as a fixed value corresponding to one sampling period ($T_d=T_s$). The open-loop transfer function from LV1 voltage to phase-shift variable D, $G_{DAB,OL}\left(s\right),$ is given in Equation (53).

The PI voltage controller model, $C_{DAB}\left(s\right)$, is given in Equation (54). The control design follows the zero-placement method [50]. At a chosen crossover frequency ${\omega }_{c,DAB}$ of the closed-loop system, the plant contributes a phase angle ${\mathsf{\Phi }}_{OL}=\angle G_{DAB,OL}\left(j{\omega }_{c,DAB}\right)$. To achieve the desired PM, the closed loop phase ${\mathsf{\Phi }}_{CL}$ must satisfy Equation (55), where ${\mathsf{\Phi }}_C$ is the additional phase provided by the PI compensator. The controller phase is expressed in Equation (55) [50]. By solving Equations (55) and (56), the required PI zero location, ${\omega }_{z,DAB}$, is obtained. The proportional gain $K_{p,DAB}$ is estimated from Equation (57), while the integral gain $K_{i,DAB}$ is calculated by substituting ${\omega }_{z,DAB}$ and $K_{p,DAB}$ in Equation (54). The closed-loop output impedance of the DAB stage, $Z_{outDAB,CL}$, is given in Equation (58). The final discrete controller model is obtained using Tustin’s transformation to the z domain.

$$g_1={\displaystyle \frac{D(1-D)}{2 n L_{DAB} f_{swDAB}}}$$

(48)

$$g_2={\displaystyle \frac{V_{LV1}(1-2D)}{2 n L_{DAB} f_{swDAB}}}$$

(49)

$$g_3={\displaystyle \frac{V_{HV}(1-2D)}{2 n L_{DAB} f_{swDAB}}}$$

(50)

$$Z_{outDAB,OL}\left(s\right)={\left[{\displaystyle \frac{1}{R_{LV1}}}+{\displaystyle \frac{1}{{(r}_{C2}+\frac{1}{s{C}_2})}}\right]}^{-1}$$

(51)

$$H_v\left(s\right)={\displaystyle \frac{1}{1+\frac{s}{{\omega }_{vs}}}},\hspace{1em}{\omega }_{vs}=2\pi f_{BWv}$$

(52)

$$G_{DAB,OL}\left(s\right)=g_3 Z_{outDAB-OL}\left(s\right) H_v\left(s\right) e^{-s T_d}$$

(53)

$$C_{DAB}\left(s\right)=K_{p,DAB}\left(1+{\displaystyle \frac{{\omega }_{z,DAB}}{s}}\right), {\omega }_{zDAB}={\displaystyle \frac{K_{i,DAB}}{K_{p,DAB}}}$$

(54)

$${\mathsf{\Phi }}_{CL}={\mathsf{\Phi }}_{OL}+{\mathsf{\Phi }}_C=-{180}^{°}+PM$$

(55)

$${\mathsf{\Phi }}_C={\tan }^{-1}\left({\displaystyle \frac{{\omega }_{c DAB}}{{\omega }_{z DAB}}}\right)-{90}^{°}$$

(56)

$$K_{pDAB}={\displaystyle \frac{1}{\left|C_{DAB}\left(j{\omega }_{cDAB} \right)\right| \sqrt{1+{\left(\frac{{\omega }_{z,DAB}}{{\omega }_{c,DAB}}\right)}^2}}}$$

(57)

$$Z_{outDAB,CL}(s)={\displaystyle \frac{Z_{outDAB,OL}\left(s\right)}{1+C_{DAB}\left(s\right) G_{DAB,OL}\left(s\right)}}$$

(58)

3.2. Buck-Stage Control Design

To simplify the control design of the two-phase interleaved buck converter, zero current imbalance between the two phase inductors is assumed. Consequently, the small-signal model can be derived for a single phase. Figure 10 illustrates the small-signal model of a single-phase synchronous buck converter [53]. $D_{Buck}$ is the duty cycle of the buck converter, $(D_{Buck}=V_{LV2}/V_{LV1})$. $L_{Buck}$ and $r_{LBuck}$ denote the inductance and its parasitic resistance, respectively. $R_{LV2}$ is the equivalent load resistance on the LV2 bus, which corresponds to 2 kW load power.

Figure 11 presents the control design block diagram of the buck converter. The control-to-output voltage transfer function $G_{vd}\left(s\right)$ is derived in Equations (59)–(65) [54]. The control-to-inductor current transfer function $G_{id}\left(s\right)$ is given in Equation (66) [53]. The open-loop input impedance of the buck converter, $Z_{inBuck,OL}\left(s\right),$ can be estimated using Equations (67) and (68) [54].

The modeling and control design of the voltage control loop, $C_{vBuck}\left(s\right)$, and the current control loop, $C_{iBuck}\left(s\right)$, both PI compensators, follow the same zero-placement method applied for the DAB stage. The buck-stage closed loop input impedance can be estimated as shown in Equation (69).

$$G_{vd}\left(s\right)={\displaystyle \frac{{\widehat{v}}_{LV2}}{\widehat{d}}}=V_{LV1} {\displaystyle \frac{(1+\frac{s}{{\omega }_x})}{1+\frac{s}{{\omega }_o Q}+\frac{s^2}{{\omega }_o^2}}}$$

(59)

$${\omega }_o={\displaystyle \frac{1}{\sqrt{L_{Buck} C_4}}} \sqrt{{\displaystyle \frac{R_{LV2}+r_{LBuck}}{R_{LV2}+r_{C4}}}}$$

(60)

$$Q=\alpha {\left[{\displaystyle \frac{r_{LBuck}+r_{C4}}{Z_C}}+{\displaystyle \frac{Z_C}{R_{LV2}}}\right]}^{-1}$$

(61)

$$Z_C=\sqrt{{\displaystyle \frac{L_{Buck}}{C_4}}}$$

(62)

$$z_{C4}=r_{C4}+{\displaystyle \frac{1}{s{C}_4}}$$

(63)

$$\alpha ={\displaystyle \frac{R_{LV2}+r_{LBuck}}{R_{LV2}}}$$

(64)

$${\omega }_x={\displaystyle \frac{1}{r_{C4} C_4}}$$

(65)

$$G_{id}\left(s\right)={\displaystyle \frac{{\widehat{i}}_L}{\widehat{d}}}=V_{LV1} {\displaystyle \frac{1}{s{L}_{Buck}+r_{LBuck}+\left(\frac{R_{LV2} z_{C4}}{R_{LV2}+z_{C4}}\right)}}$$

(66)

$$Z_{inBuck,OL}\left(s\right)={\displaystyle \frac{{\widehat{v}}_{DC3}}{{\widehat{i}}_{inBuck}}}={\displaystyle \frac{\alpha R_{LV2}}{D_{Buck}^2}} {\displaystyle \frac{1+\frac{s}{{\omega }_o Q}+\frac{s^2}{{\omega }_o^2}}{1+\frac{s}{{\omega }_y}}}$$

(67)

$${\omega }_y={\displaystyle \frac{1}{{{(R}_{LV2}+r}_{C4}) C_4}}$$

(68)

$$Z_{inBuck,CL}\left(s\right)={\displaystyle \frac{Z_{inBuck,OL}\left(s\right)}{1+{C_{iBuck}\left(s\right) G}_{id}\left(s\right) e^{-s T_d}}}$$

(69)

3.3. Parameter Tuning and Stability Analysis

The stability and dynamic performance of the cascaded DAB–buck system depend strongly on the tuning of the crossover frequencies (${\omega }_C$) and the phase margins (PM) of each control loop. The methodology followed ensures that overshoot requirements are met while maintaining stability under sensor and delay constraints.

3.3.1. DAB Voltage Controller Tuning $C_{DAB}\left(z\right)$

The crossover frequency of the DAB voltage loop, ${\omega }_{c,v DAB}$, is constrained by two conditions, as expressed in Equation (70):

• ${\omega }_{c,v DAB}$ must be lower than the voltage sensor bandwidth ${\omega }_{sensor}$.
• ${\omega }_{c,v DAB}$ must be lower than $f_{sw DAB}/10$, where $f_{sw DAB}$ is the DAB switching frequency.

Within these limits, the selected crossover frequency ${\omega }_{C,V DAB}$ shall ensure a voltage overshoot $\left(M_P\right)$ of less than 10%. The corresponding target PM is obtained by first converting the overshoot to an equivalent damping ratio and then mapping this damping ratio to the ideal phase margin, as shown in Equations (71) and (72). Additional correction factors are applied to account for the effects of the sensor delay and the digital control delay. These influences are incorporated through Equations (73) and (74), which together define the final required PM for the DAB voltage controller, as shown in Equation (75).

$${\omega }_{c,v DAB}\le {\omega }_{sensor}\le 2\pi f_{sw}/10$$

(70)

$$\zeta =-{\displaystyle \frac{\ln M_P}{\sqrt{{\pi }^2+{\left(\ln M_P\right)}^2}}}$$

(71)

$$P{M}_{ideal}={\tan }^{-1}\left({\displaystyle \frac{2\zeta }{\sqrt{1+4{\zeta }^4}-2{\zeta }^2}}\right)$$

(72)

$${\varphi }_{sensor}={\tan }^{-1}\left({\displaystyle \frac{{\omega }_c}{{\omega }_{sensor}}}\right)$$

(73)

$${\varphi }_{delay \left(T_d\right)}={\omega }_c{T}_d$$

(74)

$$P{M}_{target}=P{M}_{ideal}+{\varphi }_{delay \left(T_d\right)}+{\varphi }_{sensor}$$

(75)

3.3.2. Buck Current Controller Tuning $C_{i,Buck}\left(z\right)$

To ensure that the buck stage reacts faster than the DAB, the inner current loop crossover frequency is selected, as shown in Equation (76). The corresponding PM is tuned to achieve 10% overshoot in the inductor current step response, using the same stepwise PM estimation procedure as in Equations (71)–(75).

$${\omega }_{c,i,Buck}=6 {\omega }_{c,v,DAB}$$

(76)

3.3.3. Buck Voltage Controller Tuning $C_{v,Buck}\left(z\right)$

The outer voltage loop of the buck stage must be slower than the current loop but faster than the DAB voltage loop. Thus, its crossover frequency is set as shown in (77). The PM is chosen to satisfy a maximum overshoot of 10%.

$${\omega }_{c,v,Buck}={\displaystyle \frac{{\omega }_{c,i,Buck}}{4}}$$

(77)

3.3.4. Stability Analysis

Figure 12 presents the impedance-based stability analysis of the cascaded DAB–buck system. The magnitude of the closed-loop output impedance of the DAB stage $Z_{\mathrm{out},\mathrm{DAB},\mathrm{CL}}$, defined in (58), is compared with the closed-loop input impedance of the buck converter $Z_{\mathrm{in},\mathrm{Buck},\mathrm{CL}}$, defined in (69), over frequency. According to the Middlebrook criterion, the cascaded system remains stable if the output impedance of the upstream converter stays lower than the input impedance of the downstream converter across the relevant frequency range. As shown in Figure 12, this condition is satisfied, indicating the stable operation of the cascaded control architecture.

Table 7. PI controller parameters of the DAB and buck cascaded stages.

Parameter	Value
$fs{w}_{DAB}$	$25 \mathrm{k}\mathrm{H}\mathrm{z}$
$fs{w}_{Buck}$	$500 \mathrm{k}\mathrm{H}\mathrm{z}$
${\omega }_{C,V DAB}$	500 Hz
$P{M}_{v DAB}$	${67}^{°}$
${\omega }_{C,i Buck}$	$3000 \mathrm{H}\mathrm{z}$
$P{M}_{i Buck}$	${49}^{°}$
${\omega }_{C,v Buck}$	$750 \mathrm{H}\mathrm{z}$
$P{M}_{v Buck}$	${69}^{°}$
$T_{s DAB}$	$1 \mathsf{\mu }\mathrm{s}\mathrm{e}\mathrm{c}$
$T_{s Buck}$	$100 \mathrm{n}\mathrm{s}\mathrm{e}\mathrm{c}$

summarizes the cascaded APM corresponding controller design parameters.

Figure 13 shows the Model-In-The-Loop (MIL) co-simulation setup used to validate the cascaded APM control strategy. The APM power stage implemented in PLECS corresponds to the detailed circuit topology presented in Figure 3 and is modeled using a high-fidelity switching representation that includes semiconductor switching behavior, PWM generation, and parasitic elements of the passive components. The DAB converter operates at a switching frequency of 25 kHz, while the interleaved buck converter operates at 500 kHz. The PLECS solver time step is set to 10 ns to accurately capture switching transients. The digital controllers of the DAB and buck stages are implemented using an FPGA-based model in the MATLAB 2023b environemnt and executed with sampling times of 1 µs and 100 ns, respectively, including computation and PWM delays.

Figure 14 compares the responses obtained from the linearized and high-fidelity models of the cascaded DAB–buck system. Figure 14a shows the LV1 bus voltage $V_{LV1}$, where the linearized model achieves the target overshoot of 10%, while the high-fidelity simulation exhibits a higher overshoot of approximately 26% and a short voltage dip to 44 V for about 1 ms when the downstream buck stage is enabled. Figure 14b presents the LV2 bus voltage $V_{LV2}$, which exhibits an overshoot of around 11% that remains within acceptable limits. Figure 14c illustrates the buck inductor current $i_L$, showing a transient overshoot of about 12% and stable current loop dynamics. Finally, Figure 14d shows the LV1 output current transient, highlighting the dynamic interaction between the DAB and buck stages during load engagement. The higher overshoot observed on $V_{LV1}$ is mainly attributed to the reduced-order nature of the linearized DAB model, which does not capture parasitic effects and switching dynamics present in the high-fidelity PLECS model [55].

4. Experimental Setup and Validation

The validation of the APM design optimization and control strategy is conducted in two stages. First, as the proposed multi-LV APM hardware is still under construction, the DAB converter design framework is validated on a representative platform: a 13 kW DAB intended for an on-board charger. The DAB stage operates with a nominal 390 V input, and a 260 V output. A laboratory prototype is developed, and the measured efficiency is compared with the predicted efficiency over several converter gain values. Second, the cascaded control scheme is evaluated by connecting an interleaved buck converter downstream of the DAB and assessing the voltage control design of the DAB stage and the voltage oscillations at the DAB output when the buck stage is enabled.

4.1. DAB-Stage BOM and Losses Estimation Validation

Figure 15 shows the experimental setup of the DAB converter prototype. A programmable power supply provides the HV input, while a Yokogawa power analyzer is used for accurate efficiency measurements. Transient waveforms are captured using a digital oscilloscope. The control system is implemented on a dSPACE MicroLabBox platform, where the developed controller runs on the integrated FPGA board. The power stage consists of two SiC-based H-bridges, an optimized high-frequency transformer, inductor, DC capacitors, and protection components.

Table 8. Laboratory setup values of the DAB prototype.

Parameter	Laboratory Setup Value
$P_{Max}$	13 kW
HV side voltage	390 V
LV side voltage	260 V
Semiconductor (Q1–Q8)	SiC MOSFET (1.2 kV/120 A) (CAS120M12BM2)
$f_{swDAB}$	30 kHz
$L_{DAB} size$	$43.2 \mathsf{\mu }\mathrm{H}$(2 × 22.5 $\mathsf{\mu }\mathrm{H}$)
$L_{DAB} Core$	ELP 64/10/50
$Transformer Core$	E/E 102
Transformer number of turns ($N_p:N_s$)	12:8
Input filter capacitor size and technology $\left(C1\right)$	$1\times 500 \mathsf{\mu }\mathrm{F}$ (Film Capacitor) rc: 1 mOhm
Output filter capacitor size and technology $\left(C1\right)$	1 × 500 μF (Film Capacitor) rc: 1 mOhm

summarizes the optimized design parameters and the corresponding hardware elements used in the prototype.

Figure 16 displays the DAB converter waveforms under SPS modulation with $V_{in}=$ 390 V and the $V_{out}=$ 260 V, and with the supply of a resistive load. The load current exhibits strong ringing due to a misadjusted snubber circuit. Proper tuning is necessary to damp the oscillations, ensure a smoother current, and obtain accurate loss measurements, as ringing affects RMS current and switching losses.

Figure 17 presents a comparison between the simulated and measured efficiencies of the DAB converter at two voltage gain settings: $Vout=260 V (M=1)$ and $Vout=200 V (M=0.7)$. At $M=1$, the efficiency is consistently high across the entire load range, confirming that ZVS is effectively achieved. However, as the output power exceeds 6 kW, a clear deviation emerges between the estimated and measured results. The difference is due to the high switching losses due to the ringing effect.

At $M=0.7$, the efficiency significantly decreases at low power levels due to the loss of ZVS. The deviation between estimated and measured efficiency in this operating mode also stems from simplifications in the losses estimation model, particularly the assumption of zero turn-on losses. Turn-on losses are non-negligible at high switching frequencies and contribute notably to total power loss.

4.2. Cascaded DAB and Buck Converters Control Stability Validation

Figure 18 demonstrates the setup of the buck converter. The buck converter operates at switching frequency of 40 kHz. The DAB converter is a controller for a constant output voltage of 160 V, representing the LV1 bus, and the buck converter is controlled for the output voltage of 50 V, representing the LV2 bus. DAB converter is connected to a constant resistive load of 30 A, while the buck stage is connected to constant resistive load of 8 A.

Figure 19 presents a zoomed-in view of the DAB converter’s turn-on instant, clearly showing the transient behavior. A voltage overshoot of approximately 17% is observed on the LV1 bus. Figure 20 illustrates the turn-on response of the buck converter. In Figure 21, the corresponding LV1 voltage waveform from the DAB output reveals a peak-to-peak oscillation of approximately 10 V following the buck turn-on instant.

5. Conclusions

This paper presented a robust and scalable APM system for medium-duty E-Trucks, supporting a three-bus architecture (HV, 48 V, and 12 V) to manage diverse auxiliary loads. A comparison of state-of-the-art topologies highlighted the cascaded DAB + buck configuration as the most suitable option, offering scalability and compactness despite higher control complexity. A multi-objective NSGA-II framework was applied to optimize efficiency, power density, and cost, with SiC selected for the HV side and GaN for the LV side. The optimized design achieved 95% peak efficiency and 4.1 kW/L power density. Control stability was addressed using impedance-based analysis, with PI controllers designed for both stages and validated experimentally. A 13 kW DAB prototype confirmed the accuracy of the loss models, while integration with a multi-phase buck converter demonstrated stable voltage regulation under dynamic loads. Future work will evaluate the bidirectional power flow between the HV/48 V/12 V buses. Despite the promising results, this work has several limitations. The proposed optimization framework focuses primarily on steady-state operation and does not explicitly account for long-term reliability aspects such as component aging or mission-profile-based thermal cycling. In addition, the experimental validation is limited to unidirectional operation and a specific operating range of the cascaded DAB–buck system. Future work will extend the optimization framework to include reliability and lifetime considerations, as well as bidirectional power flow and fault-operating scenarios.