An EV-Assisted Dual T-Type Inverter SAPF with Model Predictive Control for Advanced Power Quality Enhancement

Abstract

In order to improve power quality in low-voltage distribution networks with nonlinear, distorted, and unbalanced loads, this research suggests an innovative design for Shunt Active Power Filters (SAPFs). Compared to conventional single-inverter SAPF structures, the improved method uses a combination of two T-Type three-level inverters operating in a parallel configuration to improve compensator performance, leading to a higher current-carrying capacity as well as better harmonic reduction and system scalability. The Synchronous Reference Frame (SRF) algorithm is used to extract reference currents in order to achieve the required accuracy of harmonic cancellation. In order to ensure both a quick response and a suitable switch state selection for compensatory current references, the Model Predictive Current Control (MPCC) technique is employed. To maintain the DC-link voltage at a steady level and guarantee its correct operation under rapidly fluctuating loading conditions, a Proportional Integral (PI) controller-based DC–DC converter is also utilized. Four real-time operational circumstances are used to verify the performance of the proposed method using MATLAB/Simulink R2023a (i) SAPF activation under nonlinear loading conditions, (ii) dynamic load variation, (iii) distorted and unbalanced operation, and (iv) grid voltage disturbances including sag and swell conditions. The simulation study’s results show that, in all of the previously indicated scenarios, the source current Total Harmonic Distortion (THD) is reduced and an almost unity power factor is maintained while maintaining a constant DC-link voltage. Furthermore, the obtained performance meets IEEE-519-2022 requirements, demonstrating the feasibility of the suggested SAPF with two inverters under high-load circumstances.

1. Introduction

Electrical power distribution networks have undergone significant changes as a result of the introduction of power electronic converters and renewable energy systems. Nowadays, a variety of technologies are used in commercial, industrial, and residential contexts, such as switched-mode power supply, variable-speed drives, and Electric Vehicle (EV) charging stations. The aforementioned advances improve operational efficiency, but because of their nonlinear behavior, they disrupt power quality [1,2,3].

Nonlinear loads typically draw non-sinusoidal currents from the grid, which can result in harmonic distortion, current imbalance, and reactive power consumption. These effects degrade the quality of power delivered to end users, while also increasing system losses, and may cause overheating or malfunction of sensitive equipment. As a result, maintaining high power quality has become a critical requirement in modern low-voltage distribution networks [4,5,6].

Traditionally, passive filters have been widely used to mitigate harmonic distortion, mainly due to their simple structure and low cost. However, these passive filters suffer from several inherent limitations, such as limited adaptability to load variations, sensitivity to grid impedance changes, and the potential risk of resonance with network parameters [7,8,9].

These drawbacks restrict their effectiveness in dynamic and converter-dominated environments. To address these limitations, SAPFs have emerged as a flexible and effective solution for harmonic mitigation, reactive power compensation, and current balancing. By injecting compensating currents at the point of common coupling (PCC), SAPFs enforce sinusoidal source currents and enable operation close to a unity power factor, even under highly nonlinear and time-varying load conditions [10,11,12].

Additionally, EV charging systems may now switch from passive nonlinear loads to actively regulated energy interfaces that can be used in both grid-to-vehicle (G2V) and vehicle-to-grid (V2G) modes, thanks to recent advancements in power electronics. While G2V refers to the conventional EV charging method, V2G denotes two-way power transfer, allowing EV interfaces to perform ancillary services like energy buffering at the DC-link, reactive power compensation, and power quality enhancement in addition to feeding power back to the grid. This suggests that the EV interfaces may be used within the context of sophisticated SAPF systems. The EV interface will be used in the SAPF configuration for active DC-link support and operate in the V2G mode in the current study.

Recent years have seen a significant amount of study on SAPFs for enhancing power quality in distribution networks. To achieve better harmonic compensation capabilities and efficiency, a variety of converters and control strategies have been taken into consideration. A two-level voltage source inverter is used in traditional SAPF systems due to its straightforward design and straightforward control method [13,14]. Nevertheless, two-level inverters have the drawbacks of higher switching losses, worse voltage precision, and current ripples. It is inappropriate for medium- and high-power applications because of these shortcomings.

Because of its lower switching loss, better output voltage quality, and less electromagnetic interference than the traditional two-level inverter, the three-level T-type inverter has drawn a lot of attention. Additionally, despite having comparable performance characteristics, the T-type inverter uses fewer semiconductor devices than NPC-based inverters. The majority of the current literature, however, has a flaw in that it focuses mostly on single inverter-based SAPF systems, which may have certain inherent limits with regard to power handling capability and thermal management [15,16].

Parallel inverter topologies have been proposed as an effective way to increase current capacity and improve system dependability in order to address these issues. This will be made possible by dividing the loads among multiple converters, which can enhance scalability and lessen the strain on semiconductors. However, the combination of multiple inverters functioning together will cause certain control issues [17].

In terms of control schemes, researchers have described a variety of control methods for application in SAPF systems. Due to their ease of design and simplicity, traditional control methods like PI control and hysteresis current control are still used today. Variations in the switching frequency caused by hysteresis control result in increased losses and electromagnetic interference. However, PI control methods have poor dynamic behavior and sensitivity to parameters. More complex control strategies, such as Sliding Mode Control, adaptive control, and intelligent control strategies, have been proposed to address these drawbacks [18].

Recent advances in bio-inspired and metaheuristic optimization have introduced novel parameter-tuning approaches for power electronic controllers. For instance, the Musical Chairs Algorithm (MCA) and the Star-Nosed Mole Optimizer (SNMO) have demonstrated fast convergence and robustness when applied to parameter-tuning and maximum power point tracking (MPPT) problems in photovoltaic power electronic systems. Although these algorithms have not yet been applied to SAPF controller design, their reported convergence speed and robustness under dynamic operating conditions make them promising candidates for future automated tuning of PI gains and FCS-MPCC cost-function weighting coefficients [19,20].

In recent years, MPC has emerged as one of the most effective methods for using power converters. This is because it can decrease tracking errors through on-the-fly optimization without the need for additional modulation stages, respond very quickly to dynamic changes, and deal directly with switching states [21]. Accurate generation of the reference current is also essential for correct harmonic compensation. Because it can accurately discriminate between the fundamental and harmonic components of the current using dq transformation, the SRF algorithm has gained widespread popularity among all the methods available for that purpose [22].

Despite all these advancements, the majority of current research concentrates on optimal operating conditions rather than thoroughly examining the effects of nonlinear loads, network disruptions, and unbalanced loading. Incorporating supplementary energy sources, such as the EV DC–DC converter, into the SAPF architecture to stabilize the DC-link voltage has also received minimal research [23].

Motivated by the aforementioned limitations, this work presents an enhanced SAPF design that stabilizes the DC-link voltage by combining a dual parallel T-type three-level inverter with an EV-assisted DC–DC converter, as illustrated in Figure 1 [24,25]. The goal of the new design is to maximize the system’s operational dependability, harmonic mitigation, and current-carrying capacity under dynamic circumstances.

An integrated control system architecture is then created by combining the current reference based on SRFs with finite control set model predictive current control (FCS-MPCC) to achieve precise current control. Additionally, because the DC-link voltage is maintained at a constant level, a DC–DC converter managed by a PI regulator is utilized for steady-state compensation [26].

The MATLAB/Simulink R2023a environment is applied to validate the performance of the proposed system for various operational scenarios, such as nonlinear loads, variable loads, distorted/unbalanced and sag and swell voltage supply conditions. The simulation findings validate harmonic current cancellation, waveform regulation, unity power factor, and steady DC-link voltage [27].

To the best of the authors’ knowledge, no prior work has combined a dual parallel T-type three-level inverter with an EV-assisted V2G DC-link interface and a hierarchical FCS-MPCC control framework for SAPF applications. The novelty of this work lies in the integrated system architecture, the EV/V2G DC-link support mechanism, and the comprehensive four-scenario validation.

The key contributions of the paper could be stated as follows:

• A new double parallel T-type three-level inverter structure for SAPF is proposed in order to increase current capacity and enhance harmonic elimination compared to typical inverter structures.
• An EV-based DC–DC converter operating under V2G mode is included in a SAPF structure to provide assistance to the DC bus voltage under variable operational conditions.
• Combining the reference current calculation by using the SRF method with FCS-MPCC creates an efficient control strategy to provide adequate current calculations and dynamic behavior.
• The effectiveness and applicability of the proposed methodology were investigated using simulation tests for various operational modes such as nonlinearity of load, load variation, and distortion/unbalance.

The remainder of this paper is organized as follows. Section 2 presents the mathematical modeling of the proposed system. Section 3 describes the control strategies, including SRF-based reference generation, DC-link voltage regulation, and model predictive current control. Section 4 provides the simulation-based performance evaluation under different operating scenarios. Finally, Section 5 concludes the paper and outlines directions for future work.

2. Modeling of the Proposed System

This section presents the mathematical modeling of the proposed three-phase SAPF. Figure 2 illustrates the overall configuration of the proposed SAPF system. The system consists of an EV-based DC–DC converter connected to the DC-link, which is interfaced with a dual parallel T-type three-level inverter. The inverter is connected to the grid through filter inductors at the point of PCC. The model is developed to describe the dynamic behavior of the system and to provide a suitable basis for the design of the control strategy. The overall system consists of three main subsystems: (i) a dual parallel T-type three-level inverter acting as the compensating unit, (ii) a DC-link stage supported by an EV-assisted DC–DC converter, and (iii) the grid–filter–load interface. The SAPF is connected at the PCC and operates by injecting compensating currents to improve power quality under various operating conditions.

2.1. Dual T-Type Three-Level Inverter Modeling

2.1.1. Switching States and Output Voltage

The compensating unit of the proposed SAPF consists of two parallel T-type three-level inverters connected to the PCC through interfacing inductors. This parallel configuration increases the current handling capability, improves thermal distribution among semiconductor devices, and enhances the overall reliability of the system, making it suitable for medium-power applications [28].

Each inverter, as shown in Figure 3, is composed of three phase legs, where each leg can generate three discrete voltage levels $\{+V_{dc}/2,0,-V_{dc}/2\}$. This multilevel structure offers better output voltage quality and less switching stress than traditional two-level inverters [29]. Each phase’s switching state is determined by a discrete variable. $S_{xk}\in \{-1,0,+1\}$, where $x\in \{a,b,c\}$ denotes the phase, and $k\in \{1,2\}$ symbolizes the index of the inverter. Consequently, the inverter k output phase voltage is determined by:

$$v_{inv,xk}={\displaystyle \frac{V_{dc}}{2}}{S}_{xk}$$

(1)

The corresponding three-phase output voltage vector of inverter k is expressed as [30]:

$${\mathbf{v}}_{inv,k}={[v_{inv,ak},v_{inv,bk},v_{inv,ck}]}^T$$

(2)

2.1.2. Filter Current Dynamics

The $L_f-R_f$ filter, which is crucial for reducing current ripple and ensuring smooth current injection to the power grid, is how each inverter unit communicates with the PCC. The following represents the dynamics of the filter current supplied by inverter unit k

$$L_f{\displaystyle \frac{d{\mathbf{i}}_{f,k}}{dt}}={\mathbf{v}}_{inv,k}-{\mathbf{v}}_g-R_f{\mathbf{i}}_{f,k}$$

(3)

where ${\mathbf{i}}_{f,k}$ is the compensatory current contribution of inverter k, and ${\mathbf{v}}_g$ is the grid voltage vector. As is evident, the inverter output voltage directly regulates the current injection based on the switching states.

The filter resistance adopted in this study is $R_f=0.1\Omega$, which is representative of a practical filter inductor winding resistance at the simulated power level (peak grid phase voltage of 155.6 V, corresponding to $V_s=110$ V RMS; 10 kW). With a peak compensating current of ≈30 A (corresponding to $I_{rms}\approx 21.2$ A, as observed in the filter current waveforms of Figure 4), the per-phase resistive power loss is $P_{loss}=I_{rms}^2\times R_f={\left(21.2\right)}^2\times 0.1\approx 45$ W. Across the three phases, the total resistive loss is $3\times 45=135$ W, corresponding to approximately 1.35% of the rated load power $P_L=10$ kW, which is fully acceptable for a practical SAPF implementation.

Additionally, the explanatory paragraph following Equation (3) has been updated to reflect the corrected value of $R_f=0.1\Omega$, including a quantitative loss analysis confirming the practical acceptability of this parameter.

The total compensatory current injected by the SAPF is as follows because the two inverters run in parallel:

$${\mathbf{i}}_f={\mathbf{i}}_{f,1}+{\mathbf{i}}_{f,2}$$

(4)

By facilitating current sharing by inverters and enhancing overall current handling capability, the parallel arrangement reduces stress on individual components [31].

2.1.3. Discrete-Time Model for Predictive Control

The model must be discretized in order to apply FCS-MPCC. The forward Euler approximation with sampling time Ts is used to do this, resulting in [32]:

$${\mathbf{i}}_{f,k}(n+1)={\mathbf{i}}_{f,k}\left(n\right)+{\displaystyle \frac{T_s}{L_f}}\left({\mathbf{v}}_{inv,k}\left(n\right)-{\mathbf{v}}_g\left(n\right)-R_f{\mathbf{i}}_{f,k}\left(n\right)\right)$$

(5)

The predictive control technique is based on this discrete model, which enables prediction of the future compensating current for every permissible switching state.

2.2. DC-Link and Boost Converter Modeling

Since the DC-link is in charge of storing energy between the inverter section and the power supply network, its proper operation is essential. Only by guaranteeing the stability of the DC-link voltage level for efficient current compensation can this be accomplished [33]. Any fluctuation in the DC-link voltage directly affects the inverter output voltage and, consequently, the quality of the injected compensating currents.

In the proposed system, the DC-link is supported by an EV-assisted DC–DC converter operating in V2G mode. In this configuration, energy is supplied from the EV side to the DC-link, allowing the system to maintain the required voltage level under dynamic load conditions. The G2V mode is not considered in this study.

The DC-link is composed of two series-connected capacitors, and the total DC-link voltage is expressed as:

$$V_{dc}=V_{c1}+V_{c2}$$

(6)

This structure enables voltage sharing across the capacitors and supports the three-level operation of the T-type inverter.

Assuming CCM, the averaged dynamic model of the DC–DC boost converter can be described as follows. The inductor current dynamics are given by

$$L_{dc}{\displaystyle \frac{d{i}_{dc}}{dt}}=V_{in}-(1-d)V_{dc}$$

(7)

where $L_{dc}$ is the boost inductor, $i_{dc}$ is the inductor current, $V_{in}$ represents the EV-side input voltage, and d is the duty cycle of the converter.

The DC-link voltage dynamics are governed by

$$C_{dc}{\displaystyle \frac{d{V}_{dc}}{dt}}=(1-d)i_{dc}-i_{inv}$$

(8)

where $C_{dc}$ is the equivalent DC-link capacitance, and $i_{inv}$ represents the current drawn by the inverter from the DC-link.

These equations show that the DC-link voltage can be regulated by controlling the duty cycle of the DC–DC converter, which determines the amount of energy transferred from the EV interface to the SAPF. As a result, the EV-assisted converter actively contributes to maintaining DC-link stability and supports the compensation process under varying operating conditions [34].

This modeling framework provides the basis for the design of the DC-link voltage control strategy, ensuring reliable operation of the SAPF and consistent compensation performance.

2.3. Grid and Load Modeling

2.3.1. Grid Voltage Model

The external context that the SAPF operates in is the grid-load interface. To evaluate the effectiveness of the compensation plan in real-world scenarios, it becomes essential to accurately predict the grid voltage and load current.

Assuming a sinusoidal waveform, the balanced grid voltage across all three phases is expressed as follows:

$$v_{ga}\left(t\right)=V_{m}sin\left(\omega t\right)$$

(9)

$$v_{gb}\left(t\right)=V_{m}sin\left(\omega t-{\displaystyle \frac{2\pi }{3}}\right)$$

(10)

$$v_{gc}\left(t\right)=V_{m}sin\left(\omega t+{\displaystyle \frac{2\pi }{3}}\right)$$

(11)

where $V_m$ is the amplitude of the phase voltage and $\omega$ is the angular frequency.

2.3.2. Nonlinear Load Model

In reality, the load current is typically nonlinear, which causes the load current to be distorted to produce harmonics. As a result, the load current is represented as the total of its harmonics and fundamental current

$$i_L\left(t\right)=i_1\left(t\right)+{\displaystyle \sum _{h=2}^{\infty }}{i}_h\left(t\right)$$

(12)

where $i_h\left(t\right)$ denotes the harmonic components produced by the nonlinear load, and $i_1\left(t\right)$ is the fundamental component.

2.3.3. Current Relationship at the PCC

Kirchhoff’s current law governs the interaction between the grid current, load current, and compensatory current at the PCC:

$${\mathbf{i}}_g={\mathbf{i}}_L-{\mathbf{i}}_f$$

(13)

This formula highlights the importance of SAPF, which generates a sinusoidal grid current ${\mathbf{i}}_g$ that is phase-synchronized with the grid voltage by providing a compensatory current ${\mathbf{i}}_f$.

Harmonics elimination, reactive power compensation, and current balance result from effective compensatory current control [5].

3. Control Schemes

The control algorithm used in the intended SAPF is presented in this section. The control system’s objective is to provide appropriate DC-link voltage stabilization, current regulation, and harmonic mitigation under various operating situations.

The complete control architecture is organized into three well-coordinated levels that include (i) DC-link voltage control, (ii) reference current generation, and (iii) current tracking control. The control loops work on multiple time scales for optimal performance of the system [35].

The outer control loop’s role is to regulate the DC-link voltage using an EV-assisted DC–DC converter. In order to separate the fundamental and harmonic components of the current, the second stage uses the SRF technique to calculate the reference compensating currents. The third stage follows the reference currents using FCS-MPCC to determine the inverter’s ideal switching states.

This hierarchical control structure enables fast dynamic response, precise current compensation, and robust operation under a wide range of operating conditions [8,36].

3.1. DC-Link Voltage Regulation

Because DC-link voltage regulation controls the quality of the voltage provided by the inverter, it is a crucial parameter for the SAPF to operate efficiently. The current control loop may be impacted by variations in the DC-link voltage, which would reduce harmonic cancellation’s effectiveness.

The EV-assisted DC-to-DC converter will be used in the proposed scheme’s V2G mode to manage the DC-link voltage. In this instance, the EV interface will compensate for the system losses by providing the power input to the DC-link.

The control objective is to maintain the DC-link voltage $V_{dc}$ at a predefined reference value $V_{dc}^{\ast }$ [37]. The voltage error is defined as:

$$e_{dc}\left(t\right)=V_{dc}^{\ast }-V_{dc}\left(t\right)$$

(14)

A PI controller is employed to regulate the DC-link voltage and generate the reference active power required to sustain the DC-link energy

$$P^{\ast }\left(t\right)=K_p{e}_{dc}\left(t\right)+K_i\int e_{dc}\left(t\right)dt$$

(15)

where $K_p$ and $K_i$ stand for integral and proportional gains, respectively.

The d-axis current reference, or the current that should flow in order to exchange active power between the EV interface and SAPF, is then mapped to this active power reference value [38].

A proper time scale separation is made possible by the DC-link voltage control’s modest dynamic reaction in comparison to the inner current controller, which ensures stable functioning [39].

3.2. Reference Current Generation Using SRF Theory

Because it determines how much the harmonics and reactive components need to be adjusted, the compensating reference current is a crucial part of the SAPF process. It is crucial to generate the compensating reference current accurately [40].

In this work, the SRF method is adopted for reference current generation due to its capability to separate fundamental and harmonic components under both balanced and unbalanced conditions. This method is based on transforming the three-phase quantities from the stationary frame into a rotating reference frame synchronized with the grid voltage [22].

First, the measured load currents ${\mathbf{i}}_L={[i_{La},i_{Lb},i_{Lc}]}^T$ are transformed into the stationary $\alpha \beta$ frame using the Clarke transformation

$$\left[\begin{array}{c}{i}_{L\alpha }\\ i_{L\beta }\end{array}\right]={\displaystyle \frac{2}{3}}\left[\begin{array}{ccc}1& -{\displaystyle \frac{1}{2}}& -{\displaystyle \frac{1}{2}}\\ 0& {\displaystyle \frac{\sqrt{3}}{2}}& -{\displaystyle \frac{\sqrt{3}}{2}}\end{array}\right]\left[\begin{array}{c}{i}_{La}\\ i_{Lb}\\ i_{Lc}\end{array}\right]$$

(16)

Then, the stationary components are transformed into the synchronous $dq$ frame using the Park transformation:

$$\left[\begin{array}{c}{i}_{Ld}\\ i_{Lq}\end{array}\right]=\left[\begin{array}{cc}cos\theta & sin\theta \\ -sin\theta & cos\theta \end{array}\right]\left[\begin{array}{c}{i}_{L\alpha }\\ i_{L\beta }\end{array}\right]$$

(17)

where $\theta$ is the grid voltage angle obtained from a phase-locked loop (PLL).

In the synchronous reference frame, the fundamental components of the load current appear as DC quantities, while the harmonic and unbalanced components appear as oscillatory signals. A low-pass filter (LPF) is therefore used to extract the fundamental components:

$$i_{Ld}^{DC}=\mathrm{LPF}\left(i_{Ld}\right),i_{Lq}^{DC}=\mathrm{LPF}\left(i_{Lq}\right)$$

(18)

The reference compensating currents in the $dq$ frame are then defined as:

$$i_{fd}^{\ast }=i_{dc}^{\ast }-(i_{Ld}-i_{Ld}^{DC})$$

(19)

$$i_{fq}^{\ast }=-(i_{Lq}-i_{Lq}^{DC})$$

(20)

Finally, the reference compensating currents are transformed back to the three-phase frame to obtain:

$${\mathbf{i}}_f^{\ast }={[i_{fa}^{\ast },i_{fb}^{\ast },i_{fc}^{\ast }]}^T$$

(21)

This reference current is used by the predictive current controller to ensure accurate tracking and effective harmonic compensation. The complete block diagram of the proposed SRF method [14] is illustrated in Figure 5.

3.3. Finite-Control-Set Model Predictive Current Control

The tracking of the reference compensating current is achieved using FCS-MPCC. This control strategy is particularly suitable for SAPF applications due to its fast dynamic response, direct handling of inverter switching states, and ability to operate without a modulation stage [10].

The predictive control algorithm is based on the discrete-time model of the SAPF derived in Section 2. At each sampling instant, the future value of the compensating current is predicted for all possible switching states of the inverter. The prediction is performed using the discrete model

$${\mathbf{i}}_{f,k}(n+1)={\mathbf{i}}_{f,k}\left(n\right)+{\displaystyle \frac{T_s}{L_f}}\left({\mathbf{v}}_{inv,k}\left(n\right)-{\mathbf{v}}_g\left(n\right)-R_f{\mathbf{i}}_{f,k}\left(n\right)\right)$$

(22)

where ${\mathbf{i}}_{f,k}\left(n\right)$ is the measured current at the current sampling instant, and ${\mathbf{i}}_{f,k}(n+1)$ is the predicted current for the next sampling step.

Both the future compensatory current and the inverter output voltage for every potential switching state are computed. The error in tracking the estimated current by the reference current is, thus, captured by the cost function, which can be expressed as

$$J^{\left(j\right)}=\sum _{x\in \{a,b,c\}}{\left(i_{fx}^{\ast }(n+1)-i_{fx}^{\left(j\right)}(n+1)\right)}^2$$

(23)

where $i_{fx}^{\ast }$ is the reference current, $i_{fx}^{\left(j\right)}$ is the predicted current corresponding to the j-th switching state, and x denotes the phase.

The optimal switching state is selected by minimizing the cost function:

$$j^{\ast }=arg\underset{j}{min}{J}^{\left(j\right)}$$

(24)

The computational feasibility of the FCS-MPCC algorithm within Ts = 5 µs has been evaluated analytically. For a dual T-type inverter with 27 admissible voltage vectors per inverter and 3 phases, the algorithm evaluates 27 cost function instances per sampling interval. On a modern DSP (e.g., TMS320F28379D at 200 MHz) or FPGA (e.g., Xilinx Zynq-7000), this is achievable: prior studies have demonstrated FCS-MPC execution times below 2 µs on equivalent platforms. This timing budget confirms that the control algorithm itself is not a barrier to real-time implementation; the remaining question, addressed in Section 4.6, is how closely a physical realization would track the harmonic performance obtained here in simulation.

The inverter then implements the selected switching state for the subsequent sample interval.

Due to the quick and accurate tracking of the reference compensating current, it is guaranteed that the system’s dynamics and harmonic reduction would be much improved by the suggested control approach [35]. Furthermore, pulse width modulation is not necessary because switching states can be used directly [21].

3.4. Switching Coordination of Dual T-Type Inverters

Two T-type three-level inverters connected in parallel are used in the proposed SAPF system to increase current capacity and improve system dependability. For reliable functioning and appropriate compensating current distribution, both inverters must cooperate well.

In this instance, the FCS-MPCC approach enables the two inverters to cooperate automatically. The predictive controller evaluates all potential switching states throughout each sampling period and selects the best state by minimizing the current tracking error. As a result, the switching sequences for both inverters are decided upon at the same time, which naturally results in sufficient operation coordination [15,16].

As a result, the two inverters share the compensatory current without requiring a separate active current-sharing control loop such as the master/slave or droop-based regulators commonly used in conventional parallel-inverter architectures, since the FCS-MPCC cost function (Equation (24)) jointly evaluates switching states for both inverters at every sampling instant and selects the combination that minimizes total current tracking error across both. This is a structural property of the control architecture: current sharing is a byproduct of joint optimization rather than the output of a dedicated regulator.

It is important to note that this architectural simplification does not, by itself, guarantee ideal current sharing under real hardware conditions. The near-zero current difference observed in simulation (on the order of ${10}^{-6}$ A) reflects ideal software conditions with perfectly matched component parameters and zero switching delay. In a physical implementation, device switching asymmetry, parameter tolerances, and propagation delays between the two inverter legs are not captured by the predictive model and can give rise to residual circulating currents that the control algorithm does not directly suppress. Consistent with standard practice for parallel-connected converters, this residual mismatch is addressed passively, through the insertion of small inter-phase inductors (typically 0.5–2 mH), rather than through an additional active control loop. This preserves the algorithmic simplification described above while acknowledging the hardware-level measure needed to bound circulating currents in practice.

4. Simulation and Results

The simulation analysis of the proposed SAPF under various operating conditions is presented in this section. This analysis aims to investigate the effectiveness of the proposed dual parallel T-type inverter design, control method, and EV-based DC-link support system.

With the help of the parameters listed in

Table 1. System parameters.

Parameter	Symbol	Value
Grid Parameters
Grid voltage (Phase, RMS)	$V_s$	110 V
Grid frequency	f	50 Hz
Grid impedance (inductance, resistance)	$L_s,R_s$	0.1 mH, 0.1 $\Omega$
SAPF Filter Parameters
Filter inductance	$L_f$	2 mH
Filter resistance	$R_f$	0.1 $\Omega$
DC-Link and Boost Converter Parameters
DC-link voltage reference	$V_{dc}^{\ast }$	400 V
DC-link capacitors	$C_1,C_2$	2200 $\mathrm{\mu F}$
Boost converter inductance	$L_{dc}$	4 mH
Boost input voltage	$V_{in}$	200 V
Control and MPC Parameters
Sampling period	$T_s$	5 $\mathrm{\mu s}$
Sampling frequency	$f_s$	200 kHz
PI controller proportional gain	$K_p$	0.19546
PI controller integral gain	$K_i$	17.37
LPF cutoff frequency	$f_c$	50 Hz
Nonlinear Load Parameters (Scenario 1)
Load rated power	$P_L$	10 kW
Load resistance	$R_L$	15 $\Omega$
Load DC-side capacitor	$C_L$	2000 $\mathrm{\mu F}$

, MATLAB/Simulink R2023a was used to model and simulate the system. In this case, the system is viewed as a low-voltage, three-phase distribution system that serves nonlinear loads. In order to provide compensation currents for harmonic compensation, reactive power compensation, and balancing currents, SAPF is coupled at the PCC. The overall system (Figure 2) includes the dual parallel T-type three-level inverter, the DC-link supported by the EV-based DC–DC converter operating in V2G mode, and the grid-load interface. The control scheme combines DC-link voltage regulation, SRF-based reference current generation, and FCS-MPCC. To comprehensively evaluate the performance of the proposed SAPF, four representative operating scenarios are considered. Each scenario is designed to assess a specific aspect of system performance, including steady-state harmonic compensation, dynamic response, robustness under distorted and unbalanced conditions, and operation under grid voltage disturbances. The considered scenarios are: (i) SAPF activation under nonlinear loading conditions, (ii) dynamic load variation, (iii) distorted and unbalanced operation, and (iv) grid voltage disturbances including sag and swell conditions. The harmonic performance of the proposed SAPF is evaluated against the requirements of the IEEE 519-2022 standard, which specifies a maximum THD limit of 5% for individual harmonic currents at the point of common coupling in low-voltage distribution systems [41].

4.1. SAPF Activation Under Nonlinear Load

In this scenario, the performance of the proposed SAPF is evaluated under steady-state nonlinear loading conditions. The objective is to demonstrate the effectiveness of the compensation strategy in reducing harmonic distortion and improving the quality of the source current. Initially, the SAPF is deactivated, and the nonlinear load draws distorted currents from the grid. As a result, the source current exhibits significant harmonic distortion and deviates from the sinusoidal waveform. At a specified time instant, the SAPF is activated, and the compensating current is injected into the system. Figure 4 shows the grid voltage and source current before and after SAPF activation. Due to the nonlinear nature of the load, the source current distortion is extremely significant prior to adjustment. When SAPF is used, the source current becomes almost sinusoidal and synchronized with the grid voltage, indicating a near-unity power factor and appropriate harmonic compensation. The load current and the SAPF compensatory current are shown in Figure 4. This figure illustrates how the SAPF compensates for the load current distortion by adding the necessary harmonic and reactive currents. The DC-link voltage response is shown in Figure 6, where it can be seen that the voltage is maintained close to its reference value with minimal fluctuation, confirming the effectiveness of the EV-assisted DC-link regulation. Figure 7 illustrates the phase-wise current difference between the two parallel T-type inverters, defined as $i_{a1}-i_{a2}$, $i_{b1}-i_{b2}$, and $i_{c1}-i_{c2}$. It can be observed that these difference currents remain very small and oscillate around zero, indicating balanced current sharing between the two inverters. This behavior confirms proper coordination of the parallel inverter structure and demonstrates stable operation of the dual-inverter SAPF. The limited magnitude of the current mismatch further indicates that no significant circulating currents are present, which contributes to improved system reliability and performance.

The THD of the source current is significantly reduced after SAPF activation from 21.97% to 0.45%, as shown in Figure 8, demonstrating the capability of the proposed system to improve power quality under steady-state conditions.

4.2. Dynamic Load Variation

In this scenario, the dynamic performance of the proposed SAPF is evaluated under sudden changes in load conditions. The objective is to assess the ability of the control strategy to maintain effective harmonic compensation and DC-link stability during transient events.

Initially, the system operates under a nonlinear load condition with the SAPF in steady-state operation. At a specified time instant, an additional nonlinear load is introduced, causing a sudden increase in load current and harmonic distortion. This disturbance tests the dynamic response capability of the control system.

Figure 9 shows the grid current, load current, and compensating current during the load transition. It can be observed that the load current increases abruptly at the disturbance instant. In order to maintain a highly sinusoidal grid current with little transient distortion, SAPF responds quickly by adjusting the compensating current.

Figure 10 illustrates the DC-link voltage behavior during load variation. This graphic illustrates how the DC-link voltage can be kept constant in relation to the reference voltage even when the load state abruptly changes.

The absence of any harmonics in the grid current both before and after the disturbance demonstrates the efficacy of the chosen control strategy. Figure 11 illustrates the phase current difference between the two parallel-connected T-type inverters in order to examine the efficacy of a dual inverter system. $i_{a1}-i_{a2}$, $i_{b1}-i_{b2}$, and $i_{c1}-i_{c2}$ represent this.

It is evident that the current is distributed equally across the two inverters because the difference current values are very modest and swing about zero. It indicates that the parallel inverter setup is properly coordinated, and as a result, the SAPF is operating steadily with no circulating currents.

4.3. Distorted and Unbalanced Conditions

In this instance, the system’s distortion and imbalance are examined in relation to the suggested SAPF’s performance. Testing the controller’s ability to provide sufficient harmonic cancellation and current balance in a non-optimal scenario is the aim here.

These imbalances and distortions are created by adding imbalances and distortions to the system, which results in harmonic content and uneven phase currents. This is a representation of actual distribution system scenarios.

The grid voltage, grid current, SAPF compensatory current, and load current waveforms for both distorted and unbalanced situations are shown in Figure 12 and Figure 13 respectively. The SAPF supplies the compensating current so that the grid current is almost sinusoidal and balanced, despite the distorted and unbalanced load current waveform seen in the figures.

These results demonstrate that even in the face of distortions and imbalances, the suggested controller can provide stability, harmonic compensation, and current balance.

The SAPF is activated to compensate both harmonic and unbalanced current components.

4.4. Voltage Sag Condition

In this scenario, a voltage sag is introduced by reducing the grid voltage magnitude within a specified time interval. This condition simulates grid faults or sudden load increases.

Figure 14 shows the grid voltage, load current, SAPF compensating current, and resulting grid current during the voltage sag event. It can be observed that, despite the reduction in grid voltage magnitude, the SAPF maintains the grid current nearly sinusoidal and well controlled.

Figure 15 presents the DC-link capacitor voltages, $V_{c1}$ and $V_{c2}$, and the total DC-link voltage, $V_{dc}$. With a few minor transient fluctuations, the voltage at the DC connection is likewise found to be around the reference value, demonstrating appropriate energy management during sag conditions. Furthermore, even in the case of voltage sag, the harmonics analysis (Figure 16) demonstrates that the THD of the source current is significantly reduced.

This demonstrates that the proposed control strategy will offer appropriate and consistent performance as well as harmonic compensation during voltage sags.

4.5. Voltage Swell Condition

In this instance, the voltage swell is produced by changing the grid’s voltage magnitude over the designated time frame. This overvoltage condition may be brought on by a load disconnect or grid issues.

The voltages and currents at several circuit places where a voltage swell occurs are depicted in Figure 17. The figure shows that there is no issue with the grid current despite an increase in the grid voltage magnitude.

The DC-link capacitor voltages $V_{c1}$ and $V_{c2}$ and the DC-link voltage $V_{dc}$ are displayed in Figure 18. The system appears to be functioning steadily under the swell condition since the DC-link voltage is adequately controlled, and the capacitor voltages are balanced.

This makes it abundantly evident that the suggested SAPF functions effectively even in the presence of the disturbance voltage swell.

Furthermore, as Figure 18 illustrates, the DC-link voltage is highly controlled around its reference value of $400\mathrm{V}$. The success of the DC-link control technique based on PI controllers is demonstrated by the relatively little ripples that occur during the disturbance. The equal capacitor voltages $V_{c1}$ and $V_{c2}$ demonstrate the uniform distribution of energy.

Additionally, even in the case of voltage swell, the harmonics analysis (Figure 19) shows that the THD of the source current is well minimized.

These results unequivocally demonstrate that the twin T-type inverter-based SAPF system’s novel architecture functions well in situations of grid voltage swell.

4.6. Harmonic Distortion Analysis

The generated SAPF’s performance can be further evaluated by using the FFT technique to analyze the signal’s harmonics. The source current spectrum before and after correction is shown in Figure 8.

Table 2. Performance summary.

Scenario	THD After	PF	DC-Link Stability	Remark
Nonlinear Load	0.45%	≈1	Stable	Effective compensation
Dynamic Load	Low	≈1	Fast recovery	Good dynamic response
Unbalanced	Low	≈1	Stable	Robust
Voltage Sag	0.61%	≈1	Minor fluctuation	Fault tolerant
Voltage Swell	1.41%	≈1	Stable	Robust

summarizes the overall performance of the proposed SAPF across the different operating scenarios considered in this study, including nonlinear, dynamic, and unbalanced loads as well as voltage sag and swell conditions, confirming consistently low THD, near-unity power factor, and stable DC-link behavior throughout.

Because of the nonlinear loads, the load current is severely distorted before the SAPF is applied. The source current’s THD is approximately $21.97\%$, and the harmonics are primarily of low order, such as the fifth and seventh harmonics.

The level of harmonics is significantly decreased by using the created SAPF. THD’s value falls to $0.45\%$.

Furthermore, the near-perfect operating power factor performance is achieved by compensating the source current, which produces nearly sinusoidal behavior in harmony with the grid voltage.

Even under nonlinear loads, the measured THD value conforms with the IEEE-519-2022 standard values for low voltage distribution networks [41], confirming the efficacy of the proposed SAPF in enhancing power quality.

Having established in Section 3.3 that the FCS-MPCC algorithm is computationally realizable within the $T_s=5\mathsf{\mu }\mathrm{s}$ sampling window, it is equally important to assess how the reported THD figures would translate to a physical system. The 0.45% value obtained here reflects idealized simulation conditions: noise-free current sensing, perfectly matched filter parameters between the two parallel inverters, and switching-state selection with no additional dead-time or measurement delay beyond the timing budget confirmed above. In practice, current sensor noise and quantization, dead-time, and parameter tolerances between the paralleled inverter branches would introduce additional distortion beyond what an idealized model captures. This is consistent with the broader FCS-MPC-based SAPF literature: MPC-based SAPFs with formal stability guarantees have reduced comparable pre-compensation THD levels to values validated through hardware-in-the-loop testing, SRF-based MPC controllers validated on experimental converters have achieved THD as low as roughly 3%, and controller-hardware-in-the-loop evaluations across various nonlinear load types have consistently reduced double-digit THD to values below 3%. A physical realization of the proposed system is therefore expected to achieve THD in a comparable 1–3% range, still well within the IEEE-519-2022 limit of 5%, though higher than the idealized 0.45% simulation figure. Together with the timing analysis in Section 3.3, this indicates that both the real-time computational requirements and the harmonic compensation performance of the proposed SAPF are expected to hold on physical hardware; formal confirmation of both aspects through DSP/FPGA implementation and HIL testing is identified as the immediate next step for this work (Section 5).

4.7. Comparative Analysis: FCS-MPCC Versus Sliding Mode Control

To further validate the superiority of the proposed FCS-MPCC strategy, a comparative evaluation is conducted against a Sliding Mode Control (SMC) scheme applied to the same dual parallel T-type SAPF configuration under identical operating conditions (Scenario 1: fixed nonlinear load, same system parameters as listed in Table 1).

4.7.1. SAPF Activation Response Under Sliding Mode Control

Figure 20 presents the source current waveforms under the SMC strategy following SAPF activation. After activation, the source current exhibits a transient settling period before reaching steady state. During this transient phase, a noticeable residual ripple is observed, which is attributed to the inherent chattering phenomenon associated with sliding mode controllers. This chattering arises from the high-frequency switching around the sliding surface, causing the system trajectory to oscillate rather than converge smoothly. In steady state, the source current approaches a near-sinusoidal waveform, demonstrating the capability of the SMC to achieve harmonic compensation under fixed nonlinear load conditions.

4.7.2. Harmonic Distortion Analysis Under Sliding Mode Control (SMC)

The FFT spectrum of the source current after SAPF activation under the SMC strategy is presented in Figure 21. Before compensation, the source current THD is approximately $21.97\%$, dominated by low-order harmonic components, particularly the 5th (250 Hz) and 7th (350 Hz) harmonics. After SAPF activation with the SMC controller, the THD is reduced to approximately $1.87\%$. The quantitative harmonic performance of the SMC-based SAPF is summarized in

Table 3. Performance comparison: FCS-MPCC vs. Sliding Mode Control.

Performance Metric	SMC	FCS-MPCC
THD before compensation (%)	21.97	21.97
THD after compensation (%)	1.87	0.45
Settling time (ms)	20	≈20
Steady-state current ripple	low	Very low
DC-link voltage deviation (V)	2	<2
Switching frequency	Fixed	Fixed
Modulator required	No	No
Parameter sensitivity	High	Low
Computational complexity	Low	Moderate
IEEE 519-2022 compliance	yes	Yes

.

4.7.3. Discussion

The comparative results in Table 3 highlight several trade-offs between the proposed FCS-MPCC strategy and the SMC approach:

1.

Lower THD: FCS-MPCC achieves a post-compensation THD of 0.45%, compared to 1.87% under SMC. This suggests that the online cost-function optimization performed at each $T_s=5\mathrm{\mu s}$ enables more precise tracking of the reference compensating current than the fixed switching surface of SMC.

2.

Reduced current ripple: As visible in the filter current waveforms of Figure 20, the FCS-MPCC-compensated current exhibits a smoother profile than the SMC-compensated current, consistent with the chattering phenomenon commonly reported for SMC strategies operating near the sliding surface [42], which is a known source of additional harmonic content and increased switching device stress.

3.

Fixed switching frequency: SMC in its conventional form typically operates at a variable switching frequency [42], which complicates filter design and increases electromagnetic interference (EMI). FCS-MPCC operates at a fixed sampling frequency of 200 kHz, simplifying harmonic analysis and filter design.

4.

Comparable dynamic response: Both strategies exhibit similar settling times (≈20 ms, Table 3), indicating that the two approaches provide comparable transient response during SAPF activation and load changes under the tested conditions.

5.

No modulation stage required: Both strategies operate without a PWM modulator. FCS-MPCC directly selects the optimal switching state from the finite control set, eliminating the need for sliding-surface design and gain tuning, which are known to be sensitive to system parameter variations in SMC, at the cost of a moderately higher per-cycle computational burden.

These results indicate that the proposed FCS-MPCC strategy offers improved harmonic compensation and steady-state current quality, and reduced parameter sensitivity, compared to the SMC approach under identical topology and load conditions, while both strategies achieve compliance with the IEEE 519-2022 harmonic standard [41].

4.8. Summary of Practical Implementation Considerations

While the simulation results confirm the effectiveness of the proposed control strategy, several practical factors affect the transition from simulation to hardware implementation. Six such factors are summarized below, several of which have already been discussed in the relevant sections above.

Computational burden. As shown in Section 3.3, the FCS-MPCC algorithm evaluates 27 cost-function instances per sampling interval ($T_s=5\mathrm{\mu s}$). Prior studies report FCS-MPC execution times below 2 $\mathrm{\mu s}$ on comparable DSP/FPGA platforms, indicating this is achievable, though formal timing verification on the target hardware remains future work.

Dead-time effects. T-type inverters require a dead-time interval between complementary switch transitions to prevent shoot-through across the DC-link. Typical dead-time values for IGBT-based T-type legs are on the order of 1–2 $\mathrm{\mu s}$. Dead-time introduces a voltage error at each switching transition that is proportional to the dead-time duration and switching frequency, and it is a well-known source of low-order current harmonics and zero-current-crossing distortion in VSI-based SAPFs. This effect is not modeled in the present simulation and is expected to be a contributor to the gap between the simulated 0.45% THD and the hardware-realistic 1–3% range discussed in Section 4.6.

Parameter uncertainty. The predictive model (Equation (23)) assumes exact knowledge of $L_f$ and $R_f$. In practice, filter inductor tolerances (typically ±5–10%) and mismatch between the two parallel inverter branches would introduce prediction error in the FCS-MPCC cost function and, as noted in Section 3.4, could give rise to small circulating currents between the two inverters that the idealized simulation (with perfectly matched parameters) does not capture. Mitigation typically takes the form of small inter-phase inductors (0.5–2 mH, as discussed in Section 3.4), a passive hardware measure that does not require an additional active current-sharing controller, consistent with the architectural simplification the FCS-MPCC provides. An online parameter estimator is a candidate active-control extension for future work, should passive mitigation prove insufficient.

Measurement delay. The predictive control law in Section 3.3 assumes the measured current $i_{f,k}\left(n\right)$ is available instantaneously at the start of each sampling interval. In practice, ADC conversion and signal-conditioning introduce a finite delay, commonly addressed in the FCS-MPC literature through one-step-ahead delay compensation (predicting $i_{f,k}(n+2)$ from $i_{f,k}(n+1)$ rather than directly applying the switching state computed from $i_{f,k}\left(n\right)$). This delay-compensation extension was not implemented in the present model and is recommended for the hardware implementation phase.

Switching losses. Because FCS-MPCC does not enforce a fixed carrier-based switching pattern, its effective switching frequency varies with operating conditions but is bounded by the 200 kHz sampling frequency. T-type three-level inverters are reported in the literature to exhibit lower switching losses than equivalent two-level inverters at comparable voltage and current ratings, owing to the reduced voltage step ($V_{dc}/2$ rather than $V_{dc}$) across each commutation. Reported efficiencies for T-type inverters in comparable power ranges are typically in the 97–99% range. Combined with the conduction loss estimate already given in Section 2.1.2 (≈45 W per phase, or ≈1.35% of rated power), total semiconductor losses for the proposed dual-inverter configuration are expected to remain within a similar single-digit percentage of rated power, though a full datasheet-based loss calculation for the selected switching devices has not been performed and is left for future work.

Thermal performance. The parallel configuration distributes the total compensating current across two sets of semiconductor devices rather than one, which is expected to roughly halve the current stress, and consequently the conduction and switching loss, per device relative to a single-inverter SAPF of equivalent rating. This is consistent with the reliability and thermal-distribution motivation stated in the Introduction. However, junction temperature rise depends on device-specific thermal resistance and heatsink design, which have not been modeled here. A formal electro-thermal simulation (e.g., using PLECS or a datasheet-based thermal network) is identified as a necessary step prior to hardware prototyping.

5. Conclusions

This study describes an enhanced three-phase SAPF that uses a dual parallel T-Type three-level inverter topology to improve power quality in low-voltage distribution systems. The suggested system makes use of the SRF methodology to extract reference current, the FCS-MPC approach for current tracking, and the PI controller for DC-link voltage management. The thorough simulation study has taken into account four scenarios: activation filter, fixed and variable load, distorted and unbalanced load, and sag and swell voltage. The simulation results make it abundantly evident that the suggested SAPF successfully lowers the current’s harmonics, balances the source current, and regulates the DC-link voltage in every scenario. According to IEEE-519-2022 regulations, the source current THD is decreased in the situation of distorted grid voltage.

The T-type with two inverters provides better current handling capacity and more effective harmonic suppression than the traditional SAPF with one inverter. Additionally, the usage of FCS-MPC enables effective system operation and quick dynamic reaction because it does not require multi-loop algorithms for PWM generation.

Future study will focus on improving the suggested controller to reduce switching and computing work. Alternative DSP/FPGA controller designs will also be investigated. Moreover, there will be a focus on experimental implementation using a TMS320F28379D DSP or Xilinx Zynq-7000 FPGA, combined with HIL validation using dSPACE or OPAL-RT. The prototype will incorporate $R_f$ = 0.1 $\Omega$, inter-phase inductors, and dead-time compensation.