Three-Bridge LLC-LC Resonant Converter with Wide Output Voltage Control Ranges

Abstract

This paper presents an enhanced three-bridge LLC-LC DC-DC converter featuring notch filters implemented with an LC parallel resonant circuit. The proposed topology enables seamless output voltage regulation from the rated output voltage down to 0 V_DC. To ensure stable operation over a wide output voltage range while maintaining a limited switching frequency variation, the converter adopts five operating-mode transitions, allowing effective voltage regulation even with a relatively large magnetizing inductance. Furthermore, excessive current in the LC parallel resonant tank is significantly reduced by restricting the voltage applied to the resonant circuit to one-quarter of the input voltage, even when operating at the LC resonant frequency. The operating principles of the proposed converter are thoroughly analyzed, and its performance and feasibility are validated experimentally.

1. Introduction

Due to the rise of environmental pollution issues, E-mobility, which operates with electric motors instead of conventional internal combustion engines, has been increasing. Consequently, various E-mobility applications with different battery packs are being developed, necessitating DC-DC converters that support a wide output voltage range for charging with a single power supply unit. In such applications, LLC resonant converters, capable of zero voltage switching (ZVS) during the variable switching frequency control operation around the resonant frequency to facilitate boost and buck operations, have gained attention. However, conventional LLC resonant converters have difficulty controlling output voltage due to the small gain change when operating above and below the resonant frequency [1,2]. To achieve a wider output voltage control range, methods to reduce the transformer’s magnetizing inductance ($L_m$) have been proposed to extend the output voltage control range [3,4,5]. However, reducing the magnetizing inductance ($L_m$) increases the resonant current, leading to higher conduction losses and increased transformer electromagnetic interference (EMI) due to the fringing effect from increased air gaps. To address these issues, improved LLC resonant converters have been developed that vary the values of the resonant components, such as the resonant capacitors or resonant inductors to shift the resonant frequency to a lower frequency. The converters widen the gain range due to the increased transformer magnetizing current, thus extending the boost and buck range and the hold-up time [6,7,8,9,10].

Furthermore, an LLC resonant converter with a wide output voltage control range has been developed by applying a variable topology from full bridge (FB) to half bridge (HB) [11,12,13,14]. However, there is a drawback of unstable output voltage operation due to the abrupt change in voltage gain immediately after the transition from FB to HB topology. To address this issue, a morphing control LLC resonant converter has been introduced that employs duty modulation (DM) for gradual duty control during the mode transition and frequency modulation (FM) for precise output voltage control to respond to gain changes [15,16,17,18]. Nonetheless, achieving a voltage control range beyond four times remains a challenge.

In another approach to extend the output voltage control range, a two-phase interleaved LLC resonant converter with hybrid rectifier was introduced [19]. However, during the phase shift and out-of-phase modulation, the converter can produce differences in voltage gain characteristics due to parameter differences and current imbalance in the resonant circuits, and it is challenging to control the output voltage by four times or more.

A three-bridge LLC resonant converter, capable of operating over a wide output voltage range (1 $V_o$ to −16 $V_o$) through topology transition among four operation modes and morphing control, has been proposed [20,21,22]. However, this three-bridge LLC resonant converter must have a small magnetizing inductance ($L_m$) to achieve a wide output voltage control range and ZVS within a narrow switching frequency control range. Consequently, it still suffers from increased switching and conduction losses due to the reduced magnetizing inductance ($L_m$) and a wide operational frequency control range (0.9 $f_r$ to 2.3 $f_r$) under light load conditions. Additionally, due to the DC gain characteristics of LLC resonant converters using variable switching frequency control (FM), reducing the output voltage to 0 $V_{DC}$ is impossible, leading to overcurrent situations during overload and short-circuit conditions, necessitating system shutdown [23].

To address overcurrent and short-circuit loads while reducing the output voltage to 0 V_DC, an LLC resonant converter with a notch filter and an LC parallel resonant circuit has been introduced [24,25,26,27,28]. While this allows reduction of the output voltage to 0 $V_{DC}$ at the notch filter’s parallel resonant frequency, excessive parallel resonant current flows as the input voltage ($V_{in}$) is fully applied to the notch filter, limiting its application.

As demonstrated in previous literature, the necessity of developing converters capable of handling wide output voltage requirements is widely recognized. As part of the efforts to address this issue, this paper presents a research and development study on an LLC-LC DC-DC converter with an LC parallel resonant circuit (notch filter) applied to the three-bridge LLC resonant converter, as shown in Figure 1. This proposed circuit is designed with efficiency in mind, leveraging the LC parallel resonant circuit’s characteristic of sharply increasing impedance at the parallel resonant frequency ($f_{rp}$) to limit the maximum switching operating frequency control range to the LC parallel resonant frequency ($f_{rp}$), thereby improving gain characteristics. The improved gain characteristics allow the selection of a higher magnetizing inductance ($L_{pm}$) than conventional designs while maintaining controllable output voltage gain characteristics, reducing switching, conduction, and transformer winding losses. In particular, in case of overload or short-circuit load, it transits to Mode 0 and operates by reducing the output voltage ($V_o$) to 0 $V_{DC}$. At this time, because 1/4 of the input voltage ($V_{in}$) is applied to the high-impedance notch filter, excessive parallel resonance tank current could be reduced.

The structure of this paper is as follows: Section 2 describes the operating principles, input impedance characteristics, and gain characteristics of the proposed converter. Section 3 explains the control methods for mode transitions applied to the circuit. amd verifies the functionality and applicability of the proposed converter through experimental results and analysis of a 6 kW prototype, followed by the conclusion in Section 4.

2. Proposed Three-Bridge LLC-LC Resonant Converter

2.1. Circuit Topology and Operation Principles

The schematic of the three-bridge LLC-LC resonant converter proposed in this paper is shown in Figure 1. The circuit is divided into primary and secondary sides. The primary side consists of switching devices Q₁–Q₆ and two resonant tanks. Each of the two resonant tanks is composed of a transformer, a notch filter, and a resonant capacitor. The secondary side comprises rectifier diodes (D₁–D₆) and the secondary windings of the transformers (T₁, T₂). Current flows from the primary to the secondary side through the transformers. The meanings of the symbols on the circuit diagram are detailed within the text. The resonant inductor of the circuit is the equivalent leakage inductance ($L_{eq}$) composed of the primary and secondary leakage inductances ($L_{pl}$, $N^2{L}_{sl}$) and magnetizing inductance ($L_{pm}$) of the HF transformer, and the resonant capacitance ($C_r$) is connected in series with it. The parallel resonant inductors ($L_p$) and parallel resonant capacitors ($C_p$) of the parallel LC resonant circuit are connected in series with the LLC resonant tank (LLC Res. Tank) described earlier. The following assumptions are made to simplify the analysis of the circuits.

• LLC Res. Tank 1 and LLC Res. Tank 2 have the same parameters. $L_{pl}=L_{pl1}=L_{pl2}$, $L_{pm}=L_{pm1}=L_{pm2}$, $L_{sl}=L_{ps1}=L_{ps2}$, $L_{eq}=L_{eq1}=L_{eq2}$, $C_r=C_{r1}=C_{r2}$.
• Notch filter 1 and notch filter 2 of parallel LC resonant circuit have the same parameters. $L_p=L_{p1}=L_{p2}$, $C_p=C_{p1}=C_{p2}$.
• Both transformers have the same turn ratio. $N=N_P/N_S$, $N_P=N_{P1}=N_{P2}$, $N_S=N_{S11}=N_{S12}=N_{S21}=N_{S22}$.

The proposed converter operates in five operating modes (Mode 0, Mode 1, Mode 2, Mode 3, and Mode 4) according to the switching patterns of the six main switching devices (Q₁/Q₂, Q₃/Q₄, Q₅/Q₆). Figure 2, Figure 3, Figure 4, Figure 5 and Figure 6 show the main waveforms and current flow diagrams during steady-state operation of each mode, divided into six steps.

2.1.1. Steady-State Analysis in Mode 0

In Mode 0, the main switching device Q₂ is always turned on; Q₁, Q₃, and Q₄ are always turned off; and Q₅ and Q₆ are turned on/off with a 50% duty cycle each period. This configuration causes the two primary-side resonant circuits to be connected in series, and the secondary windings of the transformers are connected in parallel according to the transformer polarity, resulting in half-bridge operation.

• Step 0-I ($t_0\le t<t_1$): In this step, the main switching device Q₅ is turned on while Q₆ is turned off. When the primary-side resonant current ($I_{PT1},I_{PT2}$) flows through Q₂ and Q₅, the current decreases from positive to negative direction, causing the secondary-side rectifying diodes D₁ and D₆ to conduct. At this time, the voltage induced from the primary side is applied to the secondary side of the transformer. This step ends when the primary-side resonant current ($I_{PT1},I_{PT2}$) becomes equal to the primary-side magnetizing current ($I_{pm1},I_{pm2}$) and the transformer secondary-side current ($I_{S12},I_{S21}$) becomes 0 A.
• Step 0-II ($t_1\le t<t_2$): $I_{S12}$ and $I_{S21}$ decrease to 0 A, causing D₁ and D₆ to become reverse-biased. At this time, the output load and the transformer secondary side operate separately, and $I_{PT1}$ and $I_{PT2}$ flow through $L_{pl}$ and $C_r$, the notch filter, and $L_{pm}$, causing $L_{pm}$ to participate in resonance.
• Step 0-III ($t_2\le t<t_3$): When Q₅ turns off at $t_2$, the primary-side resonant voltage ($V_{ab}$, $V_{bc}$) increases from –$V_{in}$/2 to 0 $V_{DC}$, and $I_{PT1}$ and $I_{PT2}$ start to rise from negative to positive direction. Moreover, the parasitic capacitance-voltage of Q₅ is charged to the input voltage, and simultaneously, the parasitic capacitance-voltage of Q₆ is discharged to 0 $V_{DC}$.
• Step 0-IV–Step 0-VI ($t_3\le t<t_6$): The main switching device Q₆ is turned on with ZVS when the primary-side resonant current ($I_{PT1}$, $I_{PT2}$) is flowing through the anti-parallel diode of Q₆ at $t_3$. The input voltage is separated from the primary-side resonant circuit, and due to the energy stored in the resonant capacitor $C_r$, $I_{PT1}$ and $I_{PT2}$ flow through Q₂ and Q₆, causing the secondary-side rectifying diodes D₃ and D₄ to conduct. For the remaining half-cycle, the subsequent operation is similar to step 0-I to step 0-III.

2.1.2. Steady-State Analysis in Mode 1

In Mode 1, the main switching devices Q₃ and Q₄ are always turned off, and Q₁/Q₂ and Q₆/Q₅ are turned on/off with a 50% duty cycle each period. Mode 1 operates with the primary series and secondary parallel connections according to the switching pattern, resulting in full bridge operation. Therefore, operating in the $V_o$ to 2 $V_o$ range through variable switching frequency control is possible.

• Step 1-I–Step 1-II ($t_0\le t<t_2$): This interval operates the same as step 0-I to step 0-II explained earlier.
• Step 1-III ($t_2\le t<t_3$): When Q₅ turns off at $t_2$, $V_{ab}$ and $V_{bc}$ increase from –$V_{in}$/2 to $V_{in}$/2, and $I_{PT1}$ and $I_{PT2}$ start to rise from negative to positive direction. Moreover, the parasitic capacitors of Q₂ and Q₅ are charged to the input voltage ($V_{in}$), and simultaneously, the parasitic capacitors of Q₁ and Q₆ are discharged to 0 $V_{DC}$.
• Step 1-IV ($t_3\le t<t_4$): The main switching devices Q₁ and Q₆ at $t_3$ are turned on with ZVS when the primary-side resonant current ($I_{PT1}$, $I_{PT2}$) is flowing through the anti-parallel diodes of Q₁ and Q₆. Furthermore, $I_{PT1}$ and $I_{PT2}$ start flowing through Q₁ and Q₆, with the current rising in the positive direction. At this time, D₃ and D₄ conduct, and the voltage induced from the primary side is applied to the secondary side of the transformer. This step ends when $I_{PT1}$ and $I_{PT2}$ become equal to $I_{pm1}$ and $I_{pm2}$, and the transformer secondary-side currents ($I_{S11}$, $I_{S22}$) become 0 A.
• Step 1-V ($t_4\le t<t_5$): $I_{S11}$ and $I_{S22}$ decrease to 0 A, causing D₃ and D₄ to become reverse-biased. At this time, the output load and the transformer secondary side operate separately, and $I_{PT1}$ and $I_{PT2}$ flow through $L_{pl}$ and $C_r$, the notch filter, and $L_{pm}$, causing $L_{pm}$ to participate in resonance.
• Step 1-VI ($t_5\le t<t_6$): When Q₁ and Q₆ turn off at $t_5$, $V_{ab}$ and $V_{bc}$ decrease from $V_{in}$/2 to –$V_{in}$/2, and $I_{PT1}$ and $I_{PT2}$ start to fall from positive to negative direction. Moreover, the parasitic capacitors of Q₁ and Q₆ are charged to the input voltage ($V_{in}$), and simultaneously, the parasitic capacitors of Q₂ and Q₅ are discharged to 0 $V_{DC}$.

2.1.3. Steady-State Analysis in Mode 2

In Mode 2, the main switching devices Q₂ and Q₆ are always turned on, Q₁ and Q₅ are always turned off, and Q₃ and Q₄ are turned on/off with a 50% duty cycle each period. This causes the two primary-side resonant circuits to be connected in parallel, and the secondary windings of the transformers are connected in series according to the transformer polarity, resulting in half-bridge operation. Therefore, it is possible to operate in the 2 $V_o$ to 4 $V_o$ range through variable switching frequency control.

• Step 2-I ($t_0\le t<t_1$): In this step, the main switching device Q₃ is turned on while Q₄ is turned off from the previous step. When the primary-side resonant current flows through Q₃, Q₂, and Q₆, $I_{PT1}$ decreases from positive to negative direction, and $I_{PT2}$ rises in the opposite direction, causing the secondary-side rectifying diode D₅ to conduct. At this time, the voltage induced from the primary side is applied to the secondary side of the transformer, and the magnetic energy of $L_{pm}$ increases linearly, with $L_{pm}$ not participating in resonance. This step ends when $I_{PT1}$ and $I_{PT2}$ become equal to $I_{pm1}$ and $I_{pm2}$, and $I_{S12}$ and $I_{S22}$ become 0 A.
• Step 2-II ($t_1\le t<t_2$): $I_{S12}$ and $I_{S22}$ decrease to 0 A, causing D₅ to become reverse-biased. Currently, the output load and the transformer secondary side operate separately, and $I_{PT1}$ and $I_{PT2}$ flow through the notch filter, $L_{pl}$, $C_r$, and $L_{pm}$, causing $L_{pm}$ to participate in resonance.
• Step 2-III ($t_2\le t<t_3$): When Q₃ turns off at $t_2$, $V_{ab}$ increases from –$V_{in}$ to 0 $V_{DC}$, and $V_{bc}$ decreases from $V_{in}$ to 0 $V_{DC}$. At this time, $I_{PT1}$ and $I_{PT2}$ start to rise and fall in the opposite direction of their previous flow. Moreover, the parasitic capacitor of Q₃ is charged to the input voltage ($V_{in}$), and simultaneously, the parasitic capacitor of Q₄ is discharged to 0 $V_{DC}$.
• Step 2-IV–Step 2-VI ($t_3\le t<t_6$): For the remaining half-cycle, Q₄ is turned on while Q₃ is turned off from the previous step. The input voltage is separated from the primary-side resonant circuit, and due to the energy stored in the resonant capacitor $C_r$, the primary-side resonant current flows through Q₄, Q₂, and Q₆, causing the secondary-side rectifying diode D₂ to conduct. The subsequent operation is similar to step 2-I to step 2-III.

2.1.4. Steady-State Analysis in Mode 3

In Mode 3, the main switching device Q₆ is always turned on, Q₅ is always turned off, and Q₁/Q₂ and Q₄/Q₃ are turned on/off with a 50% duty cycle each period. Therefore, the circuit is connected in the same way as Mode 2, but each resonant circuit operates in full-bridge and half-bridge modes.

• Step 3-I–Step 3-II ($t_0\le t<t_2$): This interval operates the same as step 2-I to step 2-II explained earlier.
• Step 3-III ($t_2\le t<t_3$): $V_{GS2}$ and $V_{GS3}$ become 0 $V_{DC}$, and Q₂ and Q₃ turn off. As a result, $V_{ab}$ increases from –$V_{in}$ to $V_{in}$, and $V_{bc}$ decreases from $V_{in}$ to 0 $V_{DC}$. At this time, $I_{PT1}$ and $I_{PT2}$ rise and fall in the opposite direction of their previous flow. Moreover, the parasitic capacitors of Q₂ and Q₃ are charged to the input voltage ($V_{in}$), and simultaneously, the parasitic capacitors of Q₁ and Q₄ are discharged to 0 $V_{DC}$.
• Step 3-IV ($t_3\le t<t_4$): Q₁ and Q₄ turn on with ZVS condition due to the resonant current flowing through anti-parallel diodes of Q₁ and Q₄, and $I_{PT1}$ flows through Q₁ and Q₄, with the current rising from negative to positive direction. In contrast, $I_{PT2}$ flows through Q₄ and Q₆, falling in the opposite direction. This causes D₂ to conduct. At this time, $N{V}_o$ voltage induced from resonant tank 1 and $N{V}_o/2$ voltage induced from resonant tank 2 are applied to the secondary side of the transformer, and the magnetic energy of $L_{pm}$ increases linearly, with $L_{pm}$ not participating in resonance. This step ends when $I_{PT1}$ and $I_{PT2}$ become equal to $I_{pm1}$ and $I_{pm2}$, and $I_{S11}$ and $I_{S21}$ become 0 A.
• Step 3-V ($t_5\le t<t_6$): $I_{S11}$ and $I_{S21}$ decrease to 0 A, causing D₂ to become reverse-biased. Currently, the output load and the transformer secondary side operate separately, and $I_{PT1}$ and $I_{PT2}$ flow through $L_{pm}$, $L_{pl}$, $C_r$, and the notch filter, causing $L_{pm}$ to participate in resonance.

2.1.5. Steady-State Analysis in Mode 4

In Mode 4, the main switching devices Q₁, Q₄, Q₅ and Q₂, Q₃, Q₆ are turned on and off with a 50% duty cycle each period. This results in the same circuit connection as Mode 2, but with full-bridge operation.

• Step 4-I–Step 4-II ($t_0\le t<t_2$): This interval operates the same as step 2-I to step 2-II explained earlier.
• Step 4-III ($t_2\le t<t_3$): At $t_2$, $V_{GS2}$, $V_{GS3}$, and $V_{GS6}$ become 0 $V_{DC}$, and Q₂, Q₃, and Q₆ turn off. As a result, $V_{ab}$ increases from –$V_{in}$ to $V_{in}$, and $V_{bc}$ decreases from $V_{in}$ to –$V_{in}$. At this time, $I_{PT1}$ and $I_{PT2}$ rise and fall in the opposite direction of their previous flow. Moreover, the parasitic capacitors of Q₂, Q₃, and Q₆ are charged to the input voltage ($V_{in}$), and simultaneously, the parasitic capacitors of Q₁, Q₄, and Q₅ are discharged to 0 $V_{DC}$.
• Step 4-IV ($t_3\le t<t_4$): The main switching devices Q₁, Q₄, and Q₅ turn on, and $I_{PT1}$ flows through Q₁ and Q₄, rising from negative to positive direction, while $I_{PT2}$ flows through Q₅ and Q₄, falling in the opposite direction. This causes D₂ to conduct. At this time, the voltage induced from the primary side is applied to the secondary side of the transformer, and the magnetic energy of $L_{pm}$ increases linearly, with $L_{pm}$ not participating in resonance. This step ends when $I_{PT1}$ and $I_{PT2}$ become equal to $I_{pm1}$ and $I_{pm2}$, and $I_{S11}$ and $I_{S21}$ become 0 A.
• Step 4-V ($t_4\le t<t_5$): $I_{S11}$ and $I_{S21}$ decrease to 0 A, causing D₂ to become reverse-biased. Currently, the output load and the transformer secondary side operate separately, and $I_{PT1}$ and $I_{PT2}$ flow through $L_{pm}$, $L_{pl}$, $C_r$, and the notch filter, causing $L_{pm}$ to participate in resonance.
• Step 4-VI ($t_5\le t<t_6$): At $t_5$, Q₁, Q₄, and Q₅ turn off; as a result, $V_{ab}$ decreases from $V_{in}$ to –$V_{in}$, and $V_{bc}$ increases from –$V_{in}$ to $V_{in}$. $I_{PT1}$ and $I_{PT2}$ start to fall and rise in the opposite direction of their previous flow. Moreover, the parasitic capacitors of Q₁, Q₄, and Q₅ are charged to the input voltage, and simultaneously, the parasitic capacitors of Q₂, Q₃, and Q₆ are discharged to 0 $V_{DC}$.

2.2. Input Impedance Characteristics

The three-bridge LLC-LC resonant converter, with an LC parallel resonant circuit of the notch filter, can obtain five resonant frequencies ($f_r$, $f_{rs}$, $f_{rp}$, $f_{r1}$, $f_{r2}$) that are equally applicable in all operating modes. To analyze this, equivalent circuits for Mode 0/Mode 1 and Mode 2/Mode 3/Mode 4 viewed from the primary side are shown in Figure 7. Note that the symbols used in the equivalent circuit are described in Section 2.1. In Figure 7a, Mode 0 and Mode 1 operate with two LLC resonant tanks (LLC Res. Tank) connected in input-series, output-parallel (ISOP), and each LLC Res Tank has $V_o$ voltage applied on the secondary side. On the other hand, in Figure 7b, Mode 2, Mode 3, and Mode 4 operate with two LLC Res. Tanks connected in input-parallel, output-series (IPOS). The reflected secondary sides of the two LLC Res. Tanks are connected in series, and each LLC Res Tank has a $V_o$/2 voltage applied on the secondary side. Based on the DC output resistance ($R_L$) of Mode 0/Mode 1 and Mode 2/Mode 3/Mode 4, the AC equivalent resistance ($R_{ac\_x}$) can be defined as shown in Equation (1). In AC equivalent circuits and formulas, when expressing secondary parameters as primary parameters, the high-frequency transformer turns ratio (N) must be taken into consideration.

$$R_{ac\_x}=\left\{\begin{array}{cc}{\displaystyle \frac{8}{{\pi }^2}}{\displaystyle \frac{V_0^2}{P_0}}={\displaystyle \frac{8}{{\pi }^2}}{R}_L\hfill & x=I\mathrm{if}\mathrm{Mode}0\mathrm{or}1\hfill \\ {\displaystyle \frac{8}{{\pi }^2}}{\displaystyle \frac{{(V_0/2)}^2}{P_0/2}}={\displaystyle \frac{8}{{\pi }^2}}{\displaystyle \frac{R_L}{2}}\hfill & x=II\mathrm{if}\mathrm{Mode}2\mathrm{or}3\mathrm{or}4\hfill \end{array}\right.$$

(1)

The input impedance ($Z_{LLC\_x}$) to the LLC Res Tank for Mode 0/Mode 1 and Mode 2/Mode 3/Mode 4 is shown in Equation (2), and the LC parallel resonant tank impedance ($Z_{rp}$) is shown in Equation (3).

$$Z_{LLC\_x}=\left\{\begin{array}{cc}2\left|j\omega \right\{L_{pl}+{\displaystyle \frac{L_{pm}·(j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})}{j\omega L_{pm}+(j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})}}-{\displaystyle \frac{1}{{\omega }^2{C}_r}}\left\}\right|\hfill & x=I\hfill \\ {\displaystyle \frac{1}{2}}\left|j\omega \{L_{pl}+{\displaystyle \frac{L_{pm}·(j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})}{j\omega L_{pm}+(j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})}}-{\displaystyle \frac{1}{{\omega }^2{C}_r}}\}\right|\hfill & x=II\hfill \end{array}\right.$$

(2)

$$Z_{rp}=\left|{\displaystyle \frac{j\omega L_p}{1-{\omega }^2{L}_p{C}_p}}\right|$$

(3)

By simplifying Equation (2) in the open-load state, the LLC resonant frequency ($f_r$) was derived as Equation (4), and by simplifying in the short-load state, the LLC series resonant frequency ($f_{rs}$) was derived as Equation (5). Additionally, by simplifying Equation (3), the LC parallel resonant frequency ($f_{rp}$) is expressed as Equation (6).

$$f_r={\displaystyle \frac{1}{2\pi \sqrt{(L_{pl}+L_{pm})C_r}}}$$

(4)

$$f_{rs}={\displaystyle \frac{1}{2\pi \sqrt{L_{eq}{C}_r}}}$$

(5)

$$f_{rp}={\displaystyle \frac{1}{2\pi \sqrt{L_p{C}_p}}}$$

(6)

The input impedance ($Z_{in\_x}$) of Mode 0/Mode 1 and Mode 2/Mode 3/Mode 4 of the three-bridge LLC-LC resonant converter with the notch filter can be expressed as Equation (7).

$$Z_{in\_x}=\left\{\begin{array}{cc}2\left|j\omega L_{pm}\left[A+\left(A+{\displaystyle \frac{B}{1+B}}\right)·C+D\right]\right|\hfill & x=I\hfill \\ {\displaystyle \frac{1}{2}}\left|j\omega L_{pm}\left[A+\left(A+{\displaystyle \frac{B}{1+B}}\right)·C+D\right]\right|\hfill & x=II\hfill \end{array}\right.$$

(7)

The notation in Equation (7) is illustrated in the following:

• $A=L_{pl}/L_{pm}$, 1st leakage/magnetizing inductance ratio
• $B=N^2{L}_{sl}/L_{pm}$, 2nd leakage/magnetizing inductance ratio as seen from the 1st side
• $C=\left(Q_{p\_x}{F}_{pn}\right)/\left(Q_{r\_x}{F}_{rn}\right)·1/(1-F_{pn}^2)-1/F_{rn}^2$
• $D=(j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})/(j\omega L_{pm}+j\omega N^2{L}_{sl}+N^2{R}_{ac\_x})$
• $L_{eq}=L_{pl}+(L_{pm}//N^2{L}_{sl})$, equivalent leakage inductance
• $Q_{p\_x}=Z_p/N^2{R}_{ac\_x}$, LC parallel resonant load quality factor
• $Q_{r\_x}=Z_{eq}/N^2{R}_{ac\_x}$, LLC series resonant load quality factor
• $F_{pn}=f_s/f_{rp}$, switching frequency normalized to LC parallel resonant frequency
• $F_{rn}=f_s/f_{rs}$, switching frequency normalized to LLC series resonant frequency

The first resonant frequency ($f_{r1}$) of the three-bridge LLC-LC resonant converter was derived as Equation (8) by using Equation (7) in the load short-circuited state. In addition, the second resonant frequency ($f_{r2}$) of the three-bridge LLC-LC resonant converter under load open condition was calculated by and expressed in Equation (9). The two resonant frequencies $f_{r1}$ and $f_{r2}$ are affected by the LC parallel resonant tank element, as shown in Equations (8) and (9), respectively. This causes them to shift to lower frequencies compared to the LLC series resonant frequency ($f_{rs}$) and the LLC resonant frequency ($f_r$).

$$f_{r1}={\left[{\displaystyle \frac{1}{2}}(f_{rs}^2+f_{rp}^2+{\lambda }_{eq}^{-1}{f}_{rs}{f}_{rp}\pm \sqrt{{(f_{rs}^2+f_{rp}^2+{\lambda }_{eq}^{-1}{f}_{rs}{f}_{rp})}^2-4f_{rs}^2{f}_{rp}^2)}\right]}^{{\displaystyle \frac{1}{2}}}$$

(8)

$$f_{r2}={\left[{\displaystyle \frac{1}{2}}(f_{rs}^2+f_{rp}^2+{\lambda }_o^{-1}{f}_r{f}_{rp}\pm \sqrt{{(f_r^2+f_{rp}^2+{\lambda }_o^{-1}{f}_r{f}_{rp})}^2-4f_r^2{f}_{rp}^2)}\right]}^{{\displaystyle \frac{1}{2}}}$$

(9)

The notation in Equations (8) and (9) is illustrated in the following:

• ${\lambda }_{eq}=Z_{eq}/Z_p$, LLC Series /LC parallel resonant characteristic impedance ratio
• ${\lambda }_o=Z_o/Z_p$, LLC series resonant characteristic impedance
• $Z_{eq}=\sqrt{L_{eq}/C_r}$, LLC series resonant characteristic impedance
• $Z_o=\sqrt{(L_{pl}+L_{pm})/C_r}$, LLC resonant characteristic impedance
• $Z_p=\sqrt{L_p/C_p}$, LC parallel resonant characteristic impedance

Based on Equations (2) and (7), the changes in input impedance for each operating mode according to the switching frequency change of the LLC resonant tank (LLC Res. Tank) and the three-bridge LLC-LC resonant converter are normalized and shown in Figure 8. The series resonant frequencies of the two circuits shown are the $f_{rs}$ and $f_{r1}$ points. At this time, the impedance is 0, and all fundamental wave inputs are transferred to the output, resulting in a gain of 1 when not considering the transformer’s turn ratio. When the operating frequency becomes higher than this ($f_s>f_{rs},f_s>f_{r1}$), it becomes smaller than 1. At this time, as shown in Figure 8a, the impedance change in the LLC Res Tank increases gradually with the frequency increase. This indicates that a wide operating frequency range is essential to have a wide output voltage gain range. The impedance changes in the three-bridge LLC-LC resonant converter shown in Figure 8b are similar to that of the LLC Res. Tank in the ZVS₁ region ($f_{r2}<f_s\le f_{r1}$), where $Z_{in\_x}$ decreases rapidly as the operating frequency increases. This means that it has impedance characteristics similar to those of LLC Res. Tank in the region below the series resonant frequency ($f_{r1}$). In the ZVS₂ region ($f_{r1}<f_s\le f_{rp}$), $Z_{in}$ increases rapidly as the frequency increases, indicating that rapid gain changes are possible in this region. At $f_s$ = $f_{rp}$, $Z_{in\_x}$ has infinite impedance, allowing the input–output voltage gain to be reduced to 0. Therefore, the proposed circuit can operate with Boost characteristics below the series resonant frequency ($f_{r1}$) and Buck characteristics above the series resonant frequency ($f_{r1}$) and can control a wide output voltage range in a narrow operating frequency range due to the rapid impedance change near the LC parallel resonant frequency ($f_{rp}$).

2.3. Input–Output Voltage Gain Characteristics

The theoretical voltage gain ($G_{v\_M}$) equations for the proposed circuit were derived based on the first harmonic approximation (FHA) approach, using the AC equivalent resistance ($R_{ac\_x}$) from Equation (1) and the input impedance ($Z_{in\_x}$) from Equation (7) for each mode. As shown in Figure 7, Mode 0 can be represented by the same circuit as Mode 1, and Mode 2 can be represented by the same circuit as Mode 3 and Mode 4. However, unlike Mode 0/Mode 2, which operate in half-bridge switching, Mode 1/Mode 3 operate in full-bridge switching, and Mode 2 operates in full/half-bridge switching. Therefore, the voltage gain ($G_{v\_1}$) of Mode 1 can be expressed as twice the voltage gain ($G_{v\_0}$) of Mode 0, and the voltage gains ($G_{v\_3}$, $G_{v\_4}$) of Mode 3 and Mode 4 can be expressed as 1.5 times and 2 times the voltage gain ($G_{v\_2}$) of Mode 2, respectively. These formulas are defined in Equations (10)–(12).

$$G_{v\_M}=\left\{\begin{array}{cc}{\displaystyle \frac{1}{4N}}{G}_{vx}\hfill & M=0\mathrm{if}\mathrm{Mode}0\hfill \\ {\displaystyle \frac{1}{2N}}{G}_{vx}\hfill & M=1\mathrm{if}\mathrm{Mode}1\hfill \\ {\displaystyle \frac{1}{N}}{G}_{vx}\hfill & M=2\mathrm{if}\mathrm{Mode}2\hfill \\ {\displaystyle \frac{3}{2N}}{G}_{vx}\hfill & M=3\mathrm{if}\mathrm{Mode}3\hfill \\ {\displaystyle \frac{2}{N}}{G}_{vx}\hfill & M=4\mathrm{if}\mathrm{Mode}4\hfill \end{array}\right.$$

(10)

$$G_{vx}=\left\{\begin{array}{cc}{G}_v\hfill & x=I\hfill \\ G_v\hfill & x=II\hfill \end{array}\right.$$

(11)

$$G_v=1/\sqrt{{\Lambda }_1^2+{\Lambda }_2^2}$$

(12)

where ${\Lambda }_1=1+A+(A+{\displaystyle \frac{B}{1+B}})·C$, and ${\Lambda }_2=Q_{r\_x}{F}_{rn}·(1+B)·(1+C)$. A, B, and C are already discussed in Equation (7).

In LLC resonant converters, the magnetizing inductance ($L_{pm}$) of the transformers (T₁, T₂) determines the ZVS operation of the main switching devices. This must be considered in Mode 0, which has the lowest voltage gain among the operating modes of the proposed three-bridge LLC-LC converter. The magnetizing inductance ($L_{pm}$) for the ZVS operation is determined by Equation (13).

$$L_{pm\_zvs}\le {\displaystyle \frac{N{V}_o{t}_{dead}}{8C_{oss}{V}_{in}{f}_s}}=363\mathsf{\mu }\mathrm{H}$$

(13)

Magnetizing inductance ($L_{pm}$) is involved in DC gain, and a smaller value can widen the output voltage range. However, this means an increase in the magnitude of the magnetizing current flowing on the primary side, resulting in more significant conduction losses. In other words, when selecting the magnetizing inductance, considerations should include not exceeding the maximum magnetizing inductance required for ZVS operation while simultaneously choosing a value that meets the desired output voltage.

Figure 9 shows a graph of the output voltage gain changes according to variations in switching frequency ($f_s$) and magnetizing inductance ($L_{pm}$). The XY plane represents the maximum output voltage gain ($G_{v\_0}$) of Mode 0, and 290 μH, which is the maximum value of the magnetizing inductance ($L_{pm}$) that satisfies this, was selected as the transformer’s magnetizing inductance ($L_{pm}$). With the addition of a notch filter, the gain characteristics were improved, and it became possible to select a higher magnetizing inductance ($L_{pm}$), which can reduce conduction losses and winding losses.

The three-bridge LLC-LC resonant converter proposed in this paper operates in five modes described in Section 2.1, with a wide output voltage control range of 0 $V_{DC}$ to 120 $V_{DC}$. If only variable switching frequency control (FM) is used to control the output voltage ($V_o$), the output voltage gain may change significantly during mode transitions, and transient states may occur in the output voltage ($V_o$) and output current (Io). Therefore, to stably and precisely control the output voltage ($V_o$) even during mode transitions, morphing control, which simultaneously employs variable switching frequency control (FM) and duty control (DM), was applied. To set the band gap, which is the mode transition interval where morphing control occurs, the gain characteristic curves for each operation mode, as shown in Figure 10, are considered by applying the parameters selected in Equations (10)–(12). To ensure mode transitions occur at all rated loads, the gain characteristic curves are expressed under the rated load current (50 A, for example) conditions, where the input–output voltage gain characteristics are lowest. Based on the gain characteristic curve simulation in Figure 10, the output voltage control range for each operation mode (Mode 0: 0 $V_{DC}$–15 $V_{DC}$, Mode 1: 15 $V_{DC}$–30 $V_{DC}$, Mode 2: 30 $V_{DC}$–60 $V_{DC}$, Mode 3: 60 $V_{DC}$–90 $V_{DC}$, Mode 4: 90 $V_{DC}$–120 $V_{DC}$) was selected to satisfy the charging voltage range of the battery pack that each operation mode must handle. However, mode transition operations based on reference voltages could risk malfunction during morphing control for mode transitions, so we have applied band gaps between intervals to prevent malfunctions.

2.4. Control Algorithm for 3-Bridge LLC-LC Resonant Converter

Figure 11 shows the algorithm for determining the operating mode using the selected bandgap. Within the bandgap, the current operating mode (Mode x, x = 0, 1, 2, 3, 4) and the previous cycle’s operating mode (Mode_b) are compared every cycle. When Mode x > Mode_b, the transition from a lower operating mode to a higher operating mode occurs when the output voltage reaches UB. When Mode x < Mode_b, the transition from a higher operating mode to a lower operating mode occurs when it reaches LB. This prevents malfunctions during operating mode transitions. When an operating mode transition occurs, morphing control is implemented. Morphing control is a control method where variable switching frequency control (FM) and duty control (DM) are performed simultaneously. This allows for stable output voltage control by preventing transient states in the operating mode transition intervals. The TMS320F28377D MCU from Texas Instruments was used to implement this morphing control. This MCU has a CPU and an auxiliary core called CLA that can operate in parallel. Therefore, the CPU is responsible for the overall control of the circuit, while the CLA handles calculations related to PI control, ADC, duty, and phase conversion to control the circuit.

Figure 12 shows the operation flow chart of the CPU and CLA. The CPU transmits the reference voltage ($V_{o\_ref}$), reference current ($I_{o\_ref}$), and current limit ($I_{o\_limit}$) to the CLA for use in PI control. This is used for variable switching frequency control (FM). On the other hand, the CLA sends the calculated analog–digital conversion (ADC) values to the CPU for use in selecting the operating mode. If there is a change in the output voltage and the current operating mode differs from the previous operating mode, the CPU sends the target duty (Duty Target) to the CLA for operating mode transition. Additionally, if the circuit’s output current ($I_o$) exceeds the set current limit ($I_{o\_limit}$), an overcurrent protection signal is sent to the CLA. The CLA then reduces the reference voltage ($V_{o\_ref}$) according to the droop control set during PI control, allowing for stabilization of the output current.

When the CLA receives the target duty according to the operation mode change, it simultaneously performs variable switching frequency control (FM) and duty control (DM) through the operation mechanism shown in Figure 13. The variable switching frequency control (FM) operates in the constant voltage control (CV Mode) or constant current control (CC Mode) modes set in the main core. During normal operation, it operates in constant voltage control (CV Mode). It performs PI control using the error obtained by comparing the set reference voltage ($V_{o\_ref}$) and the ADC value of the output voltage (ADC_$V_o$) calculated in the CLA. The result of the PI control sets the maximum value of the ramp carrier that determines the period of the PWM Module, thereby changing the circuit’s operating frequency and controlling the output voltage. Additionally, if an overcurrent condition occurs during constant voltage control (CV Mode), an overcurrent protection signal (Current_limit) is generated. At this time, droop control is applied to reduce the reference voltage ($V_{o\_ref}$) by the amount of PI control result using the error obtained by comparing the output current (ADC_$I_o$) and the set current limit ($I_{o\_limit}$), enabling overcurrent protection through output voltage reduction.

Furthermore, duty control (DM) repeatedly performs gradual increase and decrease operations to reach the target value by comparing the current duty with the target duty after the target duty for operation mode change is set. The result of this duty control (PWM Duty) is transmitted to the PWM Module, allowing for gradual duty changes and ultimately enabling switching pattern changes as shown in Figure 14. Stable output voltage control in the operation mode transition interval was implemented with variable switching frequency control (FM) to suppress the transient state of the output voltage that may occur through duty changes.

3. Experiment Results

In this paper, we fabricated a prototype of a three-bridge LLC-LC converter with a maximum capacity of 6 kW/120 $V_{DC}$/50 A, operating in a wide output voltage control range ($V_o$: 0 $V_{DC}$–120 $V_{DC}$).

Table 1. Major ratings and devices used in three-bridge LLC-LC resonant converter.

Parameters	Value
Input voltage, $V_{in}$	700 ${\mathrm{V}}_{DC}$
Output voltage range, $V_o$	1 $V_{DC}$–120 $V_{DC}$
Output current range, $I_o$	5–50 A
Output power range, $P_o$	6 kW
1st LLC-LC resonant frequency, $f_{r1}$	148 kHz
2nd LLC-LC resonant frequency, $f_{r2}$	101 kHz
LC parallel resonant frequency, $f_{rp}$	255 kHz
Switching frequency range, $f_s$	140–255 kHz
Switching devices, Q1–Q6	UJ3C120040K3S (1200 $V_{DC}$, 65 A, 35 mΩ, SiC)
Output diodes, D1, D3, D4, D6/D2, D5	UJ3D06560KS/UJ3D06560KS × 2 (650 $V_{DC}$, 60 A, VF: 1.5 $V_{DC}$, SiC)

shows the main specifications and components used in the experiment, and

Table 2. Transformers and notch filter parameters for three-bridge LLC-LC resonant converter.

Parameters	Value
Transformer turn ratio, $N(=N_P/N_S)$	18 (=36/2)
Primary leakage inductance, $L_{pl1}$ /$L_{pl2}$	28.20 μH/28.09 μH
Secondary leakage inductance, $L_{sl1}$/$L_{sl2}$	541.00 nH/545.00 nH
Magnetizing inductance, $L_{pm1}$/$L_{pm2}$	291.13 μH/288.48 μH
Equivalent leakage inductance, $L_{eq1}$/$L_{eq2}$	137.67 μH/137.58 μH
LLC resonant capacitor, $C_{r1}$/$C_{r2}$	6.30 nF/6.33 nF
LC parallel resonant inductance, $L_{p1}$/$L_{p2}$	28.79 μH/28.66 μH
LC parallel resonant capacitor, $C_{p1}$/$C_{p2}$	13.52 nF/13.43 nF

shows the parameters of the LLC resonant circuit and LC parallel resonant circuit.

An experimental study was conducted to verify that ZVS is achieved even under specific load conditions (e.g., 10 A) at the rated voltage of each mode and that the output voltage tracks the reference voltage. The experiment is carried out with an input voltage $V_{in}$ of 700 VDC applied, while the constant-current load is set from 10 A to 50 A. At this time, the output voltage $V_o$ is controlled to track the preset target output voltage (reference voltage) $V_{o\_ref}$. The experiments are carried out for two scenarios of the reference voltage setting: (1) a constant value and (2) a linear variation from 0 V to 120 V to 0 V. Note that the second experiment was conducted under a constant-current load condition of 20 A.

Figure 15 shows the prototype of the proposed converter and the measurement equipment used during the experiment. A DC power supply (Keysight N8950A, 1000 V/30 A/10 kW) was used for the input voltage, and an electronic load (Chroma 63206A, 6 kW) was employed for the output load. A digital oscilloscope (Tektronix MSO44) was used to observe the waveforms during the experiment, and a power analyzer (Hioki PW3390) was utilized to measure the output power and efficiency.

Figure 16 shows the voltage ($V_{ab}$) and current ($I_{PT1}$) of the primary resonant circuit and the voltage ($V_{ef}$) and rectified current ($I_{S12}$) of the secondary center-tap winding for each operating mode under light load (10 A) and heavy load (50 A) conditions at rated voltages (12 $V_{DC}$, 24 $V_{DC}$, 48 $V_{DC}$, 72 $V_{DC}$, 96 $V_{DC}$, 120 $V_{DC}$). Before analyzing the experimental results shown in the figures, it is necessary to understand the specific operating conditions across different modes and loads. Figure 16a,b show the experimental waveforms when operating at the rated voltage of 12 $V_{DC}$ in Mode 0. In Mode 0, the two primary resonant circuits are connected in series and operate in half-bridge mode, so we can confirm that $-V_{in}$/2 and 0 $V_{DC}$ are applied to the primary side voltage ($V_{ab}$) of resonant circuit 1. Figure 16c,d show the experimental waveforms at the rated voltage of 24 $V_{DC}$ in Mode 1. Mode 1 also has the two primary resonant circuits connected in series. Still, unlike Mode 0, it operates in full-bridge mode, so we can confirm that $-V_{in}$/2 and $V_{in}$/2 voltages are applied to the primary side voltage ($V_{ab}$) of resonant circuit 1. We can observe oscillation in the primary side voltage waveforms of Mode 0 and Mode 1, which occurs due to parasitic resonance between the parasitic capacitance of the turned-off switches Q₃, Q₄ and the leakage inductance of the transformers (T₁, T₂) in the resonant circuit. Figure 16e,f show the experimental waveforms when operating at the rated voltage of 48 $V_{DC}$ in Mode 2. In Mode 2, the two primary resonant circuits are connected in parallel, and due to half-bridge operation, we can confirm that $-V_{in}$ and 0 $V_{DC}$ are applied to the primary side voltage ($V_{ab}$) of resonant circuit 1. Figure 16g,h show the experimental waveforms when operating at the rated voltage of 72 $V_{DC}$ in Mode 3. In Mode 3, we can confirm $-V_{in}$ and $V_{in}$ voltage on the primary side voltage ($V_{ab}$) of resonant circuit 1, indicating that transformer T₁ is operating in full-bridge mode. Figure 16i,j show the experimental waveforms when operating at the rated voltage of 96 $V_{DC}$ in Mode 4. In Mode 4, the two primary resonant circuits are connected in parallel, and due to full-bridge operation, we can confirm that $-V_{in}$ and $V_{in}$ are applied to the primary side voltage ($V_{ab}$) of resonant circuit 1. We can also observe an increase in the secondary resonant current ($I_{S12}$) waveform, confirming that in Mode 4, the secondary windings of the two transformers (T₁, T₂) in the resonant circuit are also connected in series, such as in Mode 3. Figure 16k,l show the experimental waveforms when operating at the maximum output voltage of 120 $V_{DC}$ in Mode 4 to verify the maximum output voltage operation of the proposed circuit. As seen from the experimental waveforms in each operating mode, we can confirm that ZVS is achieved in all operating modes by switching when reverse current flows through the anti-parallel diodes of the main switches.

Figure 17 shows a graph of the measurement efficiency for each operation mode. As shown in Figure 17, the maximum efficiency in Mode 0 is 87.56% at 180 W output load (12 $V_{DC}$, 15 A), and the maximum efficiency in Mode 1 is 92.25% at 720 W output load (24 $V_{DC}$, 30 A). Furthermore, the maximum efficiency in Mode 2 is 94.86% at 720 W output load (48 $V_{DC}$, 15 A), and the maximum efficiency in Mode 3 is 95.39% at 1.8kW output load (72 $V_{\mathrm{DC}}$, 25 A). The highest efficiency in all operating modes was 95.98% in Mode 4 under the output load conditions of 2.4 kW (96 $V_{DC}$/ 25 A) and 4.2 kW (120 $V_{DC}$/35 A), respectively.

Experiments were conducted by increasing and decreasing the output voltage reference to verify the mode transition with the applied morphing control. In the experimental waveform, CH 1, CH 2, and CH 3 show the drain–source voltages (V_{Q1_DS}, V_{Q3_DS}, V_{Q5_DS}) of the main switching devices Q₁, Q₃, and Q₅ to confirm the operation mode change, while CH 4 shows the output voltage ($V_o$). As can be seen in Figure 18, when the reference voltage ($V_{ref}$) rises from 0 $V_{DC}$ to 120 $V_{DC}$ over 3 s, the output voltage ($V_o$) can be observed to rise, tracking the reference voltage ($V_{ref}$). When the output voltage ($V_o$) reaches the selected upper band (Mode 0: 15.5 $V_{DC}$, Mode 1: 31 $V_{DC}$, Mode 2: 61 $V_{DC}$, Mode 3: 91 $V_{DC}$), mode transition occurs through morphing control. This mode transition can be confirmed through changes in the drain–source voltages of the main switching devices. Each switch operates as follows: in Mode 0, Q₁: off, Q₃: off, Q₅: 50% duty cycle; in Mode 1, Q₁: 50% duty, Q₃: off, Q₅: 50% duty; in Mode 2, Q₁: off, Q₃: 50%, Q₅: off; in Mode 3, Q₁: 50%, Q₃: 50%, Q₅: off; in Mode 4, Q₁: 50%, Q₃: 50%, Q₅: 50% duty. We can observe that the voltage waveforms of the switches change accordingly as the operation mode changes. The mode transition between Mode 0 and Mode 1 is controlled within a 0.5 $V_{DC}$ band gap voltage, while transitions between Mode 1 and Mode 2, Mode 2 and Mode 3, and Mode 3 and Mode 4 are controlled within a 1 $V_{DC}$ band gap voltage. The gain changes caused by duty cycle variations in mode transition are mitigated through variable switching frequency control (FM).

Figure 19 and Figure 20 show the experimental results of load variations conducted to validate the robustness of the morphing control under overload conditions. Both experiments simulated an overload state by applying a transient overcurrent exceeding 70 A while restricting the baseline output current to 45 A. Upon reaching the 45 A threshold due to the overload, the controller suppresses the current by reducing the output voltage via switching frequency acceleration and mode transition. As shown in Figure 19, under the 48 V and 45 A condition, the controller successfully transitions to Mode 1 based on the preset switching conditions, keeping the current stable at 45 A. In contrast, Figure 20 depicts the results for the 100 V and 45 A condition, confirming that the system transitions to Mode 3 under the same overload to ensure stable current regulation at 45 A.

To check the parallel resonance current ($I_p=I_{Lp},I_{Cp}$) flowing through the notch filter under load short-circuit conditions, a constant voltage control experiment was conducted with the reference voltage ($V_{ref}$) set to 0 $V_{DC}$. The three-bridge LLC-LC resonant converter operates at the LC parallel resonant frequency ($f_{rp}$) to control the output voltage to 0 $V_{DC}$ under load short-circuit conditions. In the experimental waveform shown in Figure 21, CH 1 is the gate signal voltage ($V_{GS3}$) of Q₃ for verifying the operating mode, CH 2 is the output voltage ($V_o$) for checking the output voltage under load short-circuit conditions, and CH 3 and CH 4 measure the voltage ($V_{p1}$, $V_{p2}$)/current ($I_{p1}$, $I_{p2}$) waveforms of the notch filters in each resonant circuit.

Through the experimental waveform of CH 1, it can be seen that the gate signal voltage of Q₃ is continuously applied at $-5$$V_{DC}$, indicating that it operates in Mode 0. In addition, it can be seen that under short-circuit load conditions, the turn-on/turn-off switching operation of Q₅ and Q₆ operates at 255 kHz, which is the LC parallel resonance frequency ($f_{rp}$), and is controlled by a 0 $V_{DC}$ constant voltage. At this time, there is a difference in the voltage/current applied to the notch filters of each resonant circuit. This phenomenon occurs due to the switching pattern of Mode 0 where the primary side operates in series, causing the current to flow in the order of resonant circuit 2 → resonant circuit 1, and the input voltage is blocked by notch filter 2 of resonant circuit 2, resulting in a voltage difference applied to notch filter 1 and notch filter 2. This experiment confirmed that under load short-circuit conditions of abnormal operation, the output voltage can be reduced to 0 $V_{DC}$ by controlling the switching frequency ($f_s$) to the LC parallel resonant frequency ($f_{rp}$).

4. Conclusions

In this paper, we analyzed the gain characteristics, input impedance characteristics, circuit operation algorithm, and control method for a three-bridge LLC-LC resonant converter with a wide output voltage range. We presented that a wide output voltage control (0 $V_{DC}$ to 120 $V_{DC}$) is possible within a narrow switching frequency control range (140 kHz to 255 kHz) by applying a notch filter, an LC parallel resonant circuit. Additionally, we confirmed that the proposed three-bridge LLC-LC resonant converter achieves ZVS operation of the applied switching devices under all load and input/output voltage conditions and when controlling the output voltage ($V_o$) below 1 $V_{DC}$. Even if switching at the LC parallel resonant frequency ($f_{rp}$), the LC parallel resonant current ($I_{Lp},I_{Cp}$) flows about 1/2 to 1/4 less compared to conventional half-bridge and full-bridge LLC-LC resonant converters, enabling a reduction in the notch filter size. Furthermore, we confirmed an increase in efficiency due to reduced conduction losses as the addition of the notch filter allowed for an increase in magnetizing inductance ($L_{pm}$).