GaN Electric Vehicle Systems—A Comparative Review

Abstract

Gallium nitride (GaN) devices are gaining rapid adoption in electric vehicle (EV) power electronics because of their high switching speed, efficiency, and passive size reduction. The remaining gaps concern reliability across real drive cycles, integration with vehicle-level thermal subsystems, and scalability to high-voltage platforms. This review addresses these gaps by synthesizing experimental reports and automotive case studies from 2019 to 2025. We examine reliability through junction stress and derating maps derived from urban/highway duty profiles and temperature extremes, and we link device hot-spots to thermal pathways (TIMs, spreaders, liquid/air cooling) within the EV thermal budget. We then compare GaN-based onboard chargers (OBCs), DC–DC stages (LLC/CLLC/DAB), traction inverters, and EMI strategies against Si/SiC baselines. Results indicate OBC efficiencies of 96–98% at 100–500 kHz, with 30–60% passive reduction; inverter efficiencies > 98% on 400 V platforms; and strong potential for GaN paired with Vienna or T-type rectifiers in 800 V charging, while >900 V traction remains largely SiC-led. We conclude with a topology-selection framework that balances switching and conduction losses, gate-driver complexity, and EMI, plus a roadmap toward EMI-compliant MHz operation and data-driven reliability evaluation.

1. Introduction

Electric vehicles (EVs) are reshaping modern transportation, creating demand for compact, efficient, and reliable power conversion systems. Conventional silicon-based devices are increasingly constrained in switching frequency, voltage stress, and thermal robustness, limiting their suitability for next-generation EV requirements [1,2]. Wide-bandgap (WBG) semiconductors, notably gallium nitride (GaN), offer a wide bandgap of 3.4 eV, high electron mobility, and negligible reverse recovery, enabling faster switching, reduced passive size, and higher efficiency compared with silicon and even silicon carbide (SiC) [3,4,5]. These features have accelerated GaN’s adoption in critical EV subsystems such as on-board chargers (OBCs), DC–DC converters, traction inverters, and EMI filters [6,7]. At the material and device level, GaN’s wurtzite lattice supports high breakdown fields (Figure 1), while the AlGaN/GaN heterostructure forms a high-mobility two-dimensional electron gas (2DEG) channel used in practical HEMTs (Figure 2 and Figure 3) [3,4,5].

Several recent reviews have summarized GaN’s role in electric mobility. Rahman et al. [8] provided a broad survey of WBG devices, integrating material physics, subsystem applications, and reliability. Similarly, Soomro et al. [9] offered a forward-looking analysis of GaN in traction drives. While informative, these surveys often combine GaN with SiC or focus on selected subsystems, leaving open questions about GaN’s role across the entire EV power chain. Furthermore, the existing literature seldom addresses reliability under real-world drive cycles, the interaction between localized GaN heating and vehicle-level thermal budgets, or systematic guidance for scaling converters in 400 V and 800 V battery platforms, where SiC devices still dominate traction inverters [10,11,12].

This paper addresses these gaps by presenting a subsystem-oriented review that compares GaN implementations in OBCs, DC–DC converters, traction inverters, and EMI filters, while developing a reliability- and topology-aware framework for evaluating trade-offs. In particular, we synthesize experimental reports and case studies from 2019 to 2025 to (i) link device-level heating to vehicle thermal management strategies [13,14,15], (ii) assess scaling feasibility for 400/800 V EV architectures [10,16], and (iii) provide a comparative basis for selecting topologies such as Vienna vs. T-type rectifiers in high-power OBCs [17,18]. By correlating device physics with system-level design, this review delivers differentiated insights beyond prior surveys and offers practical guidance for GaN integration in EV powertrains [19].

Organization of the paper: The remainder is structured into six sections plus the conclusion. Section 2 consolidates GaN material/device background and the review methodology (2019–2025 scope, databases, inclusion/exclusion, and evaluation metrics). Section 3 examines reliability under real drive cycles and links device-level heating to the vehicle thermal budget. Section 4 reviews GaN-based AC–DC front ends for 400 V/800 V platforms, comparing Vienna and T-type NPC choices. Section 5 covers the DC–DC stages (LLC/CLLC/DAB), emphasizing ZVS/ZCS and scaling trade-offs. Section 6 treats EMI and compliance, including a dual-LISN DM/CM workflow and a practical topology-selection framework (Pareto maps/decision matrix). Section 7 concludes with key findings and a roadmap.

2. GaN Material/Device Background and Review Methodology

Gallium nitride (GaN) crystallizes in the wurtzite structure and, with an AlGaN barrier, forms a high-mobility two-dimensional electron gas (2DEG) that enables fast, low-loss switching in power HEMTs. The device’s physical traits that are most relevant to EV converters—negligible reverse-recovery charge, low $C_{oss}$ and gate charge, and a high breakdown electric field $E_{crit}$—translate into higher practical switching frequency, reduced magnetic/passive volume, and efficiency that is competitive with Si and, in many 400 V cases, even SiC [3,4,5]. In EV subsystems (OBCs, HV–LV/HV–HV DC–DC converters, traction inverters, EMI filters), enhancement mode (p-GaN gate) HEMTs and cascade GaN are the dominant options: both minimize stored charge but require careful ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ control through a gate-loop design and layout to avoid overshoot, ringing, and false turn-on.

Figure 1, Figure 2 and Figure 3 illustrate the crystal structure and typical AlGaN/GaN HEMT cross-sections used throughout this review [3,4,5]. Figure 4 compares Si/SiC/GaN device properties (bandgap, $E_{crit}$, mobility, specific $R_{DS\left(on\right)}$, $Q_{rr}$, and $C_{oss}$) to anchor later platform (400 V/800 V) and topology comparisons.

Table 1. Comparison of key properties of Si, SiC, and GaN devices.

Property	Silicon (Si)	Silicon Carbide (SiC)	Gallium Nitride (GaN)	Significance
Bandgap Energy (eV)	1.1	3.3	3.4	A wider bandgap enables higher temperature and voltage operation.
Breakdown Electric Field (MV/cm)	0.3	2.8	3.0	Higher values allow thinner drift regions and smaller devices.
Electron Mobility (cm2/V·s)	1500	900	1500	Higher mobility supports faster switching.
Saturation Velocity (cm/s)	1 × ${10}^7$	2 × ${10}^7$	2.5 × ${10}^7$	Enables high-frequency, low-loss switching.
Thermal Conductivity (W/cm·K)	1.5	3.7	1.3	Affects heat dissipation efficiency.
Reverse Recovery Charge ($Q_{rr}$)	High	Moderate	0	Zero $Q_{rr}$ reduces switching losses and EMI.
Gate Charge ($Q_g$)	High	Moderate	Low	Lower $Q_g$ supports fast switching with low drive loss.

lists the key parameters we reference repeatedly in Section 3, Section 4, Section 5 and Section 6.

High-slew operation makes layout/packaging and thermal paths first-order EV design variables. Minimizing common-source inductance (Kelvin-source returns, compact current loops, laminated buses) and managing Miller coupling (clamps or controlled slew) preserve switching benefits and contain EMI. Because GaN pushes frequency upward, junction-to-ambient paths (TIMs, spreaders, cold plates) must be co-optimized with magnetics and EMI, so device $T_j$ remains within automotive limits across urban/highway/temperature-extreme mission profiles—this linkage is developed further in Section 3. Recent 400 V OBC prototypes with GaN demonstrate the frequency/efficiency/power-density advantages that are now achievable, and the packaging/thermal practices needed for robust operation [20,21,22].

In practical GaN power devices, the drain-to-source resistance cannot be treated as a fixed static value because transient charge-trapping phenomena introduce a dynamic component [23]. The apparent resistance during switching can be expressed as

$$R_{DS\left(ON\right)}^{dyn}\left(\mathrm{t}\right)=R_{DS\left(ON\right)}^{stat}[1+{\Delta }_{trap}(V_{DS,off}, T_j, T_{off}\left)\right],$$

(1)

where $R_{DS\left(ON\right)}^{stat}$ is the steady-state resistance, and ${\Delta }_{trap}$ is a bias- and temperature-dependent correction term associated with electron trapping in surface and buffer states during the preceding off-state [24]. When a GaN HEMT is subjected to high $V_{DS,off}$, off and elevated junction temperature $T_j$ electrons are captured in deep traps at the GaN/AlGaN interface or buffer layer [25]. Upon the next turn-on, these trapped charges temporarily reduce channel conductivity, leading to the well-known current-collapse phenomenon and an elevated dynamic, $R_{DS\left(ON\right)}^{dyn}$. The transient evolution of this resistance can be modeled as

$${\Delta }_{trap}(\mathrm{t})={\sum }_i{\alpha }_i(1-e^{{\displaystyle \frac{t}{{\tau }_i}}}),$$

(2)

where each ${\tau }_i$ represents a characteristic emission time constant for a specific trap population, and ${\alpha }_i$ denotes its relative occupancy [26]. This time-dependent formulation captures the slow recovery of the channel as trapped carriers are released between switching cycles. The total conduction loss during dynamic operation therefore increases by

$$p_{Cond}^{dyn}=I_{D,rms}^2{R}_{DS\left(ON\right)}^{dyn}$$

(3)

Because the trapping process depends strongly on the off-state dwell time $T_{off}$ and drain bias $V_{DS,off}$, accurate characterization requires pulsed double-pulse testing (DPPT) or on-wafer dynamic $R_{ON}$ measurement systems that replicate realistic converter operating sequences [27].

Recent experimental work introduced a reconfigurable test setup that is capable of emulating variable blocking voltages, current slopes, and duty ratios, enabling the extraction of $R_{DS\left(ON\right)}^{dyn}$(t) under automotive-grade conditions (Alemanno et al., 2023 [28]). Such dynamic measurement remains an active research area because it bridges material-level trapping physics with circuit-level conduction-loss modeling, which is essential for reliability-aware GaN design in EV converters [29].

To keep comparisons fair across heterogeneous reports, this review considers EV-relevant works (2019–2025) that publish measurable electrical, thermal, and EMI outcomes across the OBC, DC–DC, inverter, and EMI-filter stages [30]. We track efficiency at/near the rated load; switching frequency and mode (soft vs. hard); reported power density; thermal headroom (peak $T_j$ and cooling architecture); EMI margin to automotive limits using LISN-based methods; and reliability indicators (mission-profile mapping, dynamic $R_{DS\left(on\right)}$, power-cycling/HTOL notes). For EMI method references, we use CISPR-25 [31] and widely used practitioner notes clarifying voltage vs. current probe approaches. For three-phase AC/DC front ends on 400/800 V platforms, comparative studies of Vienna and T-type NPC rectifiers consistently show high efficiency, with different trade-offs in bidirectionality, control, and device count; these inform the selection framework developed in Section 4, Section 5 and Section 6.

3. Reliability Under Real Drive Cycles and Linkage to the Vehicle Thermal Budget

Reliable GaN deployment in EVs depends on how converter stress accumulates over real drive cycles and how that stress is absorbed by the vehicle thermal subsystem. At the device level, GaN’s negligible reverse-recovery charge and low stored charge reduce switching loss versus Si and often SiC, but fast edges concentrate stress into short intervals that are sensitive to parasites and temperature. Practical degradation channels include p-GaN gate wear-out, trapping and dynamic $R_{DS\left(on\right)}$, current collapse, hot-electron effects at high field, and thermo-mechanical fatigue in interconnects and die-attach [32,33,34], whose evolution under drive cycle stress directly couples to the charge-trapping mechanisms and measurement challenges outlined in Section 2. Accurate lifetime prediction therefore requires profile-aware screening of dynamic $R_{DS\left(on\right)}$ using pulsed or on-wafer characterization to capture trap-induced drift across blocking intervals.

Recent wafer-level characterization studies have underscored these challenges by demonstrating that even controlled dynamic $R_{DS\left(ON\right)}$ measurements are strongly influenced by the parasitic impedance of probe fixtures and the thermal time constants of high-voltage dies. In particular, Alemanno et al. [28] presented a reconfigurable on-wafer setup that was capable of emulating realistic blocking and conduction intervals, revealing how temperature rise and trap filling alter the measured on-resistance. Such experimental frameworks provide valuable calibration data for correlating laboratory switching stress with the in-vehicle thermal budget and for refining lifetime prediction under mission-profile conditions.

Mission profile matters: urban cycles (frequent transients) create many modest Δ$T_j$ events, while highway cycles create fewer but larger thermal excursions. Consequently, lifetime predictions and derating must be built around profile-aware stress metrics, rather than single worst-case points [35]. As depicted in Figure 5a–c, we map the drive cycle to electrical and thermal trajectories.

To translate vehicle duty into converter stress, we map speed/torque and charging events to electrical loading (DC-link ripple, phase currents, switching conditions). With measured thermal impedances ($R_{\theta jc},$ $R_{\theta ca}$) and coolant set-points, this yields a junction-temperature trajectory $T_j$(t). Those trajectories feed three lifetime surrogates:

(i)

Arrhenius-type acceleration for steady high-temperature wear mechanisms;

(ii)

Coffin–Manson accumulation for thermo-mechanical cycling;

(iii)

Screening of dynamic $R_{DS\left(ON\right)}$ as a proxy for trapping-induced conduction-loss drift under realistic blocking/rest intervals. JEDEC-style dynamic $R_{DS\left(ON\right)}$ procedures and double-pulse tests make these metrics comparable across reports [36,37]. Figure 5 illustrates the pipeline from duty cycle → electrical load → $T_j\left(\mathrm{t}\right)$.

The thermal budget constraint that drives the derating logic is

$$T_j=T_{cool,in}+Q_{loss}(R_{\theta jc}+R_{\theta ca}) \le T_{j,max}-H_{th}$$

(4)

here $T_{cool},in$ is the coolant inlet temperature, $Q_{loss}$ is the total device heat at the operating point, $R_{\theta jc}$ and $R_{\theta ca}$ are the junction-to-case and case-to-ambient (or cold-plate) thermal impedances, $T_{j,max}$ is the allowed junction limit, and $H_{th}$. There is a guard margin for ambient swings, coolant derating, and sensor tolerance. In practical converter assemblies, the steady-state form of (4) may underestimate localized junction heating. Factors such as voids in the die attach, solder fatigue, and coolant-flow nonuniformity increase the effective thermal impedance $Z_{th}$. over time. Reliability prediction should therefore include transient thermal-impedance data and temperature-dependent material properties to capture these cumulative effects.

Because GaN enables a higher switching frequency, magnetics and EMI filters shrink but heat-flux density rises; spreaders and cold-plates must therefore be co-optimized with gate-loop and layout choices that cap overshoot, ringing, and ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ [38,39]. In practice, designers sweep frequency versus loss and coolant set-point to generate a reliability-aware derating map that defines safe operating regions over ambient, load factor, and vehicle speed. As summarized in Figure 6, the safe region is bounded by the $T_j$ limit (e.g., 125 °C with a margin) and a temperature-dependent dynamic $R_{DS\left(on\right)}$ screen [40].

Measurement and screening close the loop. Double-pulse tests with controlled blocking intervals expose dynamic $R_{\left(on\right)}$; HTOL/HV off-state campaigns track gate wear-out; and power-cycling quantifies attach/wire fatigue across representative Δ$T_j$ bands, while LISN-based DM/CM scans verify conducted-EMI margins for the chosen operating point [41,42,43,44]. Used properly, these datasets enable guard-banded windows that meet multi-year automotive targets without sacrificing the frequency advantages that are central to GaN. The resulting profile-aware derating approach is as follows: cap $T_j$ (with margin), limit ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ via driver and layout to reduce EMI-linked stress, and validate with LISN-based DM/CM scans so thermal and EMI design are closed concurrently, not sequentially.

The derating map constrains not only the allowable junction temperature but also the dissipation available for snubbers and EMI networks. Since filter and snubber losses are concentrated at a high frequency, the chosen switching spectrum and any edge-shaping that improves EMI must be verified against the same thermal budget used to cap $T_j$. Section 6 quantifies the required DM/CM attenuation and shows how topology and edge control can meet those limits without violating the reliability envelope defined here.

4. GaN-Based AC–DC Front Ends for 400 V/800 V EV Platforms

GaN enables a higher switching frequency and a much lower switching charge than Si/SiC, which is especially valuable at the AC–DC front end of the OBC, where grid power quality (PFC), efficiency, and power density are tightly constrained [45,46,47]. Throughout this section, key converter acronyms are defined for convenience: totem-pole power factor correction (TP-PFC), neutral-point-clamped (NPC), on-board charger (OBC), and electromagnetic interference (EMI).

For single-phase charging, the bridgeless totem-pole PFC (TP-PFC), followed by a resonant DC–DC stage (LLC/CLLC/DAB), is now a mainstream GaN solution, as depicted in Figure 7. For three-phase charging, GaN favors three-level (3L) rectifiers that halve device voltage stress and reduce ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$: the Vienna rectifier (unidirectional by default; Figure 8) and the T-type neutral-point-clamped (NPC) rectifier (naturally bidirectional V2G/V2H; v 9). These options respond directly to 400/800 V scaling and the Vienna vs. T-type trade-offs [48,49,50], while providing a quantitative basis for the topology selection [51].

• Single-phase TP-PFC + resonant DC–DC (LLC/CLLC/DAB)

Unity-power-factor (UPF) control is achieved by shaping the input current reference proportionally to the instantaneous mains voltage

$$i_{ref}(\mathrm{t})={\displaystyle \frac{2P_{out}}{V_{g, rms}^2}}{v}_{g }(\mathrm{t}),$$

(5)

with current mode or predictive control maintaining $i_{ref}$(t) = k $v_{in}$(t), where k is set by the desired input conductance i (t) ≈ $i_{ref}$(t) [52]. The resonant stage uses the standard definitions [53]. Where $L_r$ and $C_r$ are the tank elements, $R_L$ is the reflected load, and ${\omega }_r$ = 2π$f_r$.

$$f_r={\displaystyle \frac{1}{2 \pi \sqrt{L_r C_r}}}, \mathrm{Q}={\displaystyle \frac{R_L}{{\omega }_r L_r}},$$

(6)

ZVS is obtained when the tank energy during dead time exceeds the energy to commutate device capacitances [54]:

$${\displaystyle \frac{1}{2}}{L}_{eq}{i}_L^2\ge = {\sum }_k{\displaystyle \frac{1}{2}}{C}_{oss, k}{V}_{ds, k}^2$$

(7)

In this GaN-based arrangement, switching transitions are fast and largely capacitive, so $E_{SW}$ ∝ $C_{eq }$ $V^2$ is minimized; magnetics and EMI filters shrink, improving density [55].

Equation (7) expresses the ideal ZVS boundary, assuming perfectly linear capacitances and negligible loop inductance. In hardware, parasitic inductance and the non-linear voltage dependence of $C_{oss }\left(V\right)$ reduce the stored energy available for commutation, while the gate-driver delay and dead time variation shift the actual ZVS point. Time-domain simulation or double-pulse verification is required to confirm full-range soft switching.

b.

Three-phase front ends—Vienna vs. T-type (Figure 8 and Figure 9).

For 400/800 V buses, GaN benefits from 3L rectifiers because device voltage stress is halved:

$$V_{ds, max }^{\left(3L\right)}\approx {\displaystyle \frac{V_{dc}}{2}}\mathrm{vs}. V_{ds, max }^{\left(2L\right)}\approx V_{dc}$$

(8)

Current shaping for unity PF per phase is

$$i_{a }^{*}(\mathrm{t})=\mathrm{k} V_a(\mathrm{t}), \mathrm{k}={\displaystyle \frac{2 P_{out}}{3 V_{ph, rms}^2}},$$

(9)

with analogous expressions for b and c. In both 3L topologies, the split-DC link requires neutral-point balance; a small duty-offset $\delta$ (or redundant state selection) regulates the capacitor voltages $V_{c1}\approx$ $V_{c2 }$:

$${\displaystyle \frac{d}{dt}}(V_{c1 }- V_{c2 }) = {\displaystyle \frac{i_N \left(\delta \right)}{C}},$$

(10)

where $i_N$ is the neutral current modulated by δ [56]. Building on (8)–(10), the loss and EMI implications of three-level (3L) front ends can be summarized as follows.

• Switching-loss scaling (3L vs. 2L)

For hard transitions, the energy per event scales with the square of the device voltage. Because a 3L leg limits device stress to ≈${\displaystyle \frac{V_{dc }}{2}}$, the per-transition energy is approximately quartered:

$$E_{SW }^{\left(3L\right)}\approx C_{eq}({\displaystyle \frac{V_{dc }}{2}}{)}^2= {\displaystyle \frac{1}{4}}{C}_{eq}{V}_{dc }^2$$

(11)

This reduction, together with GaN’s inherently low output capacitance, enables operation at higher switching frequencies $f_s$ and smaller passives [57], as depicted in Figure 8 (Vienna) and Figure 9 (T-type). Consequently, a 3L leg achieves roughly one-fourth of the switching energy compared with a conventional two-level leg.

The proportionality in (11) neglects the overlap current and dynamic output–capacitance variation. Under high ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ or mismatched dead times, the effective $E_{SW}$ deviates from the ideal quarter-scaling. Experimental calibration using measured $R_{DS\left(ON\right)}\left(T\right)$ and loop inductance $L_{loop}$ is needed for accurate loss estimation.

• Conduction loss composition. For phase RMS current $I_{rms}$,

$$P_{cond}={\sum }_{active path}{ I }_{rms}^2{R}_{DS \left(on\right)}+{\sum }_{diodes}{V}_f{I}_{avg},$$

(12)

So, Vienna (with diodes in some current paths) incurs an additional $V_f$ $I_{avg}$ term, whereas the T-type is fully active (no diode drops) but uses more switches and drivers. Which term dominates depends on the operating point and device choices [58].

• Common mode ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ and EMI

The displacement current to the chassis is $i_{CM}$ ≈ $C_{par}$ ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$. Because a 3L transition halves $\Delta V$ and typically reduces ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ for a given edge time, the Vienna and T-type generally relax conducted EMI filtering compared with two-level legs—consistent with LISN-based methods seen later in Section 6—see Figure 8 and Figure 9 for the commutation states that set $\Delta V$ [59,60].

Topology implications and platform fit.

• Vienna rectifier (Figure 8)—Unidirectional by default, simple modulation, very low switching loss from (8), and device stress limited by (5). It is a strong choice when peak efficiency and simplicity are priorities and vehicle-to-grid (V2G) is not required.
• T-type NPC (Figure 9)—Naturally bidirectional (V2G/V2H), with the same 3L stress relief. It requires neutral-point control per (7), careful commutation sequencing, and a higher driver/channel count.

For 400 V buses (650 V GaN), both 3L options comfortably reach $f_s$ ≈ 100–300 kHz with high efficiency and manageable EMI. For 800 V buses, the 3L front ends allow the reuse of 650/700/900 V GaN while keeping $V_{ds}$ in a comfortable range; direct two-level GaN at 800 V is usually limited to series-stacked solutions with active sharing [61,62].

c.

Quantitative selection rubric

A pragmatic way to balance losses, EMI, and implementation effort is

$$\mathrm{J}=\alpha P_{sw}+\beta P_{cond}+\gamma {\mathsf{\varphi }}_{EMI}+\zeta C_{drv}$$

(13)

where ${\mathsf{\varphi }}_{EMI}$ reflects driver/channel count and $C_{drv}$ reflects driver/channel count neutral-point control effort. Minimizing $J$ over candidate topologies and switching frequencies $f_s$, subject to thermal constraints from Section 3, yields the recommended operating point [63].

Stage efficiency accounting. For all three front ends (TP-PFC, Vienna, T-type), the overall conversion efficiency is

$$\mathsf{\eta }={\displaystyle \frac{P_{sw}}{P_{out }+ P_{sw}+ P_{cond} + P_{cu} + P_{gdrv}}},$$

(14)

with $P_{sw}$ and $P_{cond}$ from (13) and (14), and magnetic losses from Steinmetz/AC-resistance models at the chosen $f_s$, and $P_{gdrv}$, set by gate charge and switching frequency [64]. The schematic and current paths referenced in (10)–(14) are shown in Figure 8 (Vienna) and Figure 9 (T-type).

Applying (13)–(16) to the three-level front end shows a crossover region in which the Vienna rectifier attains a small but measurable efficiency edge at a give $f_s$ due to diode-assisted commutation and reduced driver count, whereas the T-type NPC becomes preferable when bidirectionality and neutral-point control are required. In both cases, halved device-node swing in (8) reduces CM injection, easing the EMI margin requirement ΔE in Section 6. The selection boundary can thus be parameterized by {$P_{rated}$, $f_s$, $I_{RMS}$, Δ$v_{node}$, $C_{par}$, $C_{eq}$}, with complexity cost C (Equation (13)) tipping the decision when V2G/V2H is mandated.

d.

Gate driver and parasitic control for GaN AC–DC legs (TP-PFC, Vienna, T-type).

At GaN edge rates, the gate loop and power loop behave as coupled RF networks, so driver choice and physical layout directly determine loss, overshoot, and EMI in the AC–DC front ends. The critical parasites are the common-source inductance (CSI) in the gate return and the Miller coupling $C_{gd}$ from the switching node to the gate. The gate perturbation from the commutation current is

$$V_{GS, bounce}\approx L_{CSI}{\displaystyle \frac{{di}_D}{dt}}$$

(15)

so even $L_{CSI}$ = 2–10  nH, with ${\displaystyle \raisebox{1ex}{$di$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ of tens of A/ns, can inject several hundred millivolts on the gate, unless a Kelvin-source return is used and the driver is placed within a few millimeters of the devices [65,66]. During fast drain transitions, the Miller current into the off device is

$$i_{Miller}\approx C_{gd}{\displaystyle \frac{{dV}_D}{dt}}, \Delta V_{GS, off}\approx {\displaystyle \frac{C_{gd}}{C_{gs}+C_{stray}}}\Delta V_D$$

(16)

which can cause a false turn-on if the off-path is weak. Immunity is achieved with a strong turn-off path (low $R_{g, off}$), an active Miller clamp (engaged when $V_{GS}$ falls below a clamp threshold), and—only where permitted by the datasheet—a slight negative off-bias to increase the margin to $V_{th}$. The resulting off-state condition may be checked by

$$V_{th, off}\le V_{th, min}-(\left|V_{th, bounce}\right|+\Delta V_{GS, off}).$$

(17)

Ref. [67] shows power-loop parasitic set overshoot and ringing, impacting EMI and snubber loss. Minimizing the commutation triangle (high-side FET–low-side FET–DC-link MLCC), routing the gate loop as a tight differential pair to the Kelvin-source, and separating gate and power returns limit both $L_{loop}$ and $C_{par}$ [68]. These measures are especially effective in three-level Vienna and T-type rectifiers, where reduced device swing already halves Δv relative to two-level legs, easing CM injection and filter burden.

As depicted in Figure 10, the half-bridge parasitic network highlights the external/ESL inductances that create $V_{\left(overshoot\right)}$ ≈ L ${\displaystyle \raisebox{1ex}{$di$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ and the device/source inductances that shape ringing. As depicted in Figure 11, the gate-loop schematic shows the $C_{gd}$ Miller’s path and the remedies (split $R_g$, active clamp, optional negative bias) used to keep $V_{GS, off}$ below the threshold during hard edges.

The AC–DC front-end choices in Section 4 determine the operating envelope of the isolated stage that follows. Three-level rectifiers (Vienna, T-type) halve device-node swing and reduce CM injection at the line side, which in turn relaxes the input filter burden and permits a higher switching frequency with an acceptable EMI. The downstream LLC/CLLC or DAB stage should therefore be sized for the front-end’s DC-link ripple, allowable spectrum, and thermal headroom, established in Section 3. In practice, the front-end’s effective ΔV and ripple current set the tank stress, the ZVS margin, and the circulating current of the resonant stage—these dependencies motivate the scaling and ZVS/ZCS trade-offs analyzed in Section 5.

5. DC–DC Stages (LLC/CLLC/DAB): ZVS/ZCS and Scaling Trade-Offs

Isolated DC–DC conversion bridges the AC–DC front end and the battery/DC link. In GaN-based EV chargers, this stage is dominated by resonant LLC/CLLC and dual active bridge (DAB) architectures operating from a few hundred kilohertz up to the low-MHz range to shrink magnetics [69,70]. The design objective is to exploit GaN’s low $C_{oss}$ and negligible reverse recovery to realize soft switching—primary-side ZVS and, where advantageous, secondary-side ZCS—while preventing circulating current and transformer/core loss from eroding efficiency as frequency scales [71].

For LLC/CLLC, the soft-switching windows follow directly from the tank resonances and quality factor. With the usual definitions, the two relevant resonances for CLLC are [72,73]

$$f_{r1}={\displaystyle \frac{1}{2 \pi \sqrt{L_r C_r}}}, f_{r2}={\displaystyle \frac{1}{2 \pi \sqrt{{(L}_r+ L_m) C_r}}}$$

(18)

Equation (19) represents the idealized gain of a lossless tank. In practice, magnetizing current, device output capacitance, and transformer leakage inductance perturb the phase trajectory and shift the ZVS/ZCS boundaries. An accurate design must therefore include these parasitic elements when selecting $L_r$, $C_r,$ and the permissible dead time window.

Operating at or above $f_{r1}$ typically secures primary-side ZVS, because the tank current during dead time can charge/discharge the switch output capacitances before turn-on; operating near/below $f_{r2}$ can promote secondary-side ZCS, reducing rectifier stress [74]. In practice, designers place the nominal switching frequency slightly above $f_{r1}$ and regulate around the resonance to balance the ZVS margin against the magnetizing current [75]. Figure 12 shows the LLC/CLLC tanks, indicating $f_{r1}$ and $f_{r2}$, and overlays a ZVS/ZCS map versus normalized frequency and load.

The primary ZVS margin can be expressed by an energy balance. Let $C_{eq}$ be the effective capacitance to be commutated (dominated by the device $C_{coss}),V_{sw}$ the voltage at the switch node, and $I_{dead}$. The tank current during dead time flowing through an effective inductance $L_{eq}$. ZVS is obtained when [76]

$${\displaystyle \frac{1}{2}}{C}_{eq}{V}_{sw }^2 (C_{oss}\mathrm{energy}) \le {\displaystyle \frac{1}{2}}{L}_{eq}{I}_{dead }^2(\mathrm{inductor} \mathrm{energy} \mathrm{during} \mathrm{dead} \mathrm{time}) \Rightarrow I_{dead}\ge V_{sw}\sqrt{{\displaystyle \frac{C_{eq}}{L_{eq}}}}$$

(19)

Because GaN significantly lowers $C_{eq}$, the required $I_{dead}$ is modest even as $f_s$ rises; this is the key enabler for MHz-class LLC/CLLC with compact planar magnetics and manageable circulating power [77]. However, as $f_s$ increases, the available dead time shrinks, so $L_r, L_{m }$, and dead time programming must be co-designed to preserve [69]. These trade-offs are illustrated in Figure 12 by superimposing the constant efficiency contours (from measured $P_{core}$ and $R_{ac } \left(f\right))$ over the ZVS/ZCS regions [78,79].

A second practical axis is the circulating current versus magnetics trade-off. Running above resonance flattens the LLC gain and eases regulation, but it increases the magnetizing current if $L_m$ is small; excessive $I_{mage }$ inflates copper loss and hot-spot temperature [80,81]. The transformer design, therefore, co-optimizes the core loss (e.g., Steinmetz $P_{core }=$ $k{f}^{\alpha } B^{\beta }$ $V_{core}$) and frequency-dependent copper loss $P_{cu }$, using $R_{ac }\left(f\right)$ models [82]. Overall stage efficiency is tracked by [83]

$$\mathsf{\eta }={\displaystyle \frac{P_{sw}}{P_{out }+ P_{sw}+ P_{cond} + P_{cu} + P_{drv}}},$$

(20)

with $P_{sw}$ being largely governed through the ZVS margin, and $P_{core, }{ P}_{cu }$ being increasingly dominant as $f_{s }$ approaches the low-MHz regime. In GaN hardware, maintaining ZVS with minimal circulating current is the central lever for simultaneously hitting high η and power density.

For DAB (single phase-shift, SPS), soft switching is achieved by timing the bridge currents (via the leakage or series inductance $L_{\mathcal{l}}$) so that device capacitances are commutated before each edge [84]. With square-wave bridges of amplitudes, $V_1$ and $V_2$, the ideal SPS power transfer is [85].

$$P_{DAB }(\mathsf{\delta })={\displaystyle \frac{V_1 V_2 }{\omega L_{eq }}}{\displaystyle \frac{\mathsf{\delta }(\mathsf{\pi }-\mathsf{\delta })}{\pi }}, 0 \le \delta \le \pi ,$$

(21)

where δ is the phase shift. For a given $L_{eq }$, raising f reduces the required δ at a target power, but off-nominal bus ratios ($V_1$ $\ne$ $V_2$) increase RMS current and can jeopardize ZVS at a light load if the inductor current is insufficient during transitions [86]. Designers, therefore, pick the transformer turns ratio to keep δ moderate around the nominal and may add frequency or multi-phase control at the extremes to preserve ZVS [87]. Figure 13 plots P(δ) show typical inductor current waveforms and overlay a ZVS feasibility boundary versus load and ratio ${\displaystyle \raisebox{1ex}{$V_2$}\!\left/ \!\raisebox{-1ex}{$V_1$}\right.}$.

Scaling to 400 V and 800 V platforms follows on from these relations. On 400 V packs, full-bridge LLC/CLLC with 650–700 V GaN is straightforward at $f_s$ ≈ 300–800 kHz, with planar magnetics and ZVS margins derived. On 800 V buses [88], designers commonly

I.

Retain 650/700/900 V GaN in three-level bridges (keeping device $V_{ds}$ well below rating).

II.

Use DAB with a turns ratio chosen to minimize δ near the nominal, thereby sustaining ZVS across the drive cycle and charging use-cases [89]. The feasible design space over $f_s$ and power, constrained by (12) and by transformer flux density limits, is summarized in Figure 14.

Reported implementations align with this picture: multi-CLLC splits the tank currents to reduce device stress at the cost of magnetic complexity; interleaved LLC near 1 MHz attains ZVS with very compact magnetics but demands careful digital timing; DAB at ∼500 kHz achieves bidirectionality and wide-range operation while requiring thermal management of the circulating current when the bus ratio departs from unity [90]. GaN’s soft-switching headroom enables frequency scaling, while the practical limits are the RMS current, magnetic loss, and controller dynamics, all of which feed directly into the system-level efficiency model. As depicted in Figure 12, Figure 13 and Figure 14, the “sweet spot” typically sits where is comfortably met and $P_{core }+ P_{cu }$ remain sub-dominant.

Finally, it is useful to connect the DC–DC choices to the EMI strategies (Section 6) and the profile-aware derating maps (Section 3). Higher $f_s$ reduces the magnetic size but shifts the switching spectra upward; with GaN’s fast edges, common-mode noise and ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ couple more strongly into parasites, tank design and gate-loop layout should be co-optimized with the DM/CM filter targets defined in Section 6 [91]. At the same time, the operating point chosen from Figure 12, Figure 13 and Figure 14 must land inside the safe region of the derating maps (Figure 6): raise $f_s$ only to the point where thermal headroom and the dynamic $R_{ds }\left(on\right)$ screen remains satisfied with the mission profiles summarized in Figure 5. This cross-link ensures that the resonant/DAB stage does not just meet bench specs but survives real-cycle stresses while passing CISPR-25-conducted EMI requirements [92].

• Driver tuning and parasitic in resonant DC–DC (LLC/CLLC/DAB).

In resonant stages, the driver’s task is to guarantee ZVS/ZCS with a minimal circulating current. Because the ZVS condition (15) requires sufficient energy in the tank during dead time to commutate device capacitances, the on-edge shaping set by $R_{g, on}$ controls the attainable ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ and the available $I_{dead}$ [93]. A practical design outcome is to choose $R_{g, on}$ so that the ZVS energy balance in (15) is met at a light-to-nominal load, while the switching spectrum remains within the target EMI bands; the off-edge is kept firm with a smaller $R_{g, off}$ and an active Miller clamp for immunity over the full gain range [94].

The same two parasitic channels define robustness as follows: CSI-induced gate bounce and Miller injection. Using the estimates in (14)–(16) with the resonant stage’s worst-case ${\displaystyle \raisebox{1ex}{$di$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ and ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ provides a quantitative immunity screen [95]. Where allowed by the device, a slight negative off-bias can increase the margin to $V_{th}$ during the high-slew transitions of DAB at off-nominal ratios [96]. Propagation-delay matching and programmed dead time are co-designed with the tank, so ZVS is preserved without excessive third-quadrant conduction; too short invites shoot-through, but too long inflates the circulating current and degrades the loss terms [97]. Isolation and level-shift paths must meet the converter’s CMTI requirement, and bootstrap networks should tolerate the same ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ [98].

Include driver dissipation in the stage model via [99].

$$P_{gdrv}=Q_G{V}_{DRV}{f}_s\mathrm{per} \mathrm{device},$$

(22)

and verify that the chosen edges satisfy ZVS while keeping snubber power (Section 6) acceptable when any residual ringing is damped [100]. For completeness, the off-state immunity and timing constraints can be summarized as

$$V_{GS, off}\le V_{th, min}-(\left|V_{GS, bounce }\right|+\Delta V_{GS,off})$$

(23)

$$\mathrm{dead} \mathrm{time} \ge t_{commute}(I_{dead}, C_{eq})$$

(24)

$${CMTL}_{iso}\ge ({\displaystyle \raisebox{1ex}{${dV}_D$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}{)}_{max}+\mathrm{margin}$$

(25)

where $V_{GS, bounce }\approx$ $L_{CSI}{\displaystyle \raisebox{1ex}{$di$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ (gate bounce from common-source inductance) and Δ$V_{GS, off}$ is the Miller-induced off-gate rise during fast ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$.

As depicted in Figure 15a, the recommended gate/power-loop partition uses a Kelvin-source return, highlights the common-source inductance, and keeps the commutation loop compact—this directly relaxes the ZVS current needed in Equation (15). As depicted in Figure 15b, the simplified driver–device view shows the $C_{gd}$ and $C_{gs}$ paths that create the off-gate bump; the split $R_g$ and Miller clamp suppresses it and stabilizes the timing at high ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$.

The preceding analysis of gate-driver coordination and parasitic control completes the discussion of wired resonant converters, where energy transfer is confined to the magnetics and PCB traces.

However, the same physical attributes that make GaN devices attractive in LLC/CLLC and DAB stages—low $C_{oss}$, high ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ capability, and stable ZVS at multi-hundred-kilohertz frequencies—are now transforming contactless and high-specific-power architectures.

These include wireless power-transfer (WPT/CPT) interfaces for conductive-free charging and the electrified propulsion modules used in emerging three-dimensional transportation (eVTOL and omnidirectional vehicles).

These emerging implementations motivate an extended analytical treatment, in which the resonant-converter principles developed above are generalized to spatially coupled and high–high-power-density topologies, yielding equivalent transfer relations and efficiency scaling laws that quantify GaN’s operational limits in wireless and propulsion-grade systems.

• GaN-Enabled Wireless Transfer and Multidimensional Propulsion Extensions

While the resonant DC–DC analysis above has emphasized hard- and soft-switching coordination within cabled converters, the same GaN switching advantages now extend to contactless power transfer and three-dimensional propulsion platforms.

Both domains reuse the design languages of ZVS/ZCS control, thermal headroom, and EMI constraint described earlier, but operate at higher frequencies and with spatial coupling as the energy-transfer medium.

I.

Wireless Power Transfer (WPT) with Ferrite-Guided Circular Coils

Recent EV charging architectures exploit GaN bridges switching in the 100 kHz–13.56 MHz band to excite loosely coupled coils [101].

A simplified series–series resonant link can be expressed as

$$\mathsf{\eta }={\displaystyle \frac{{\omega }^2 M^2 R_L}{\left(R_1+R_2\right)2+{\omega }^2 M^{2 } \frac{R_1+R_2}{R_L} }}$$

(26)

where M is the mutual inductance, $R_1$ and $R_2$ are winding resistances, and $R_L$ the reflected load [102].

Because GaN transistors sustain low switching loss at high $\omega$, both M and the coupling coefficient

$$\mathrm{K}={\displaystyle \frac{M}{\sqrt{L_1 L_2}}}$$

are strongly frequency-dependent [103]. As depicted in Figure 16, the ferrite shield enclosure shapes the magnetic flux and redirects it toward the receiver plane, effectively enhancing vertical coupling while suppressing lateral field leakage and eddy-current loss into the chassis ground plane [104]. This flux guidance increases the local permeability between the coils and mitigates cross-coupling to nearby conductive structures, enabling higher efficiency at moderate air gaps [105].

Designers must, however, re-evaluate the ZVS inequality from (27), using the complex load $Z_2$($\omega ,$ $R_L$ M) to confirm that the available tank energy exceeds the commutation requirement throughout misalignment excursions [106]. The effective detuning factor

$$\mathsf{\xi }={\displaystyle \frac{\omega -{\omega }_0}{{\omega }_0}}$$

(27)

should remain within ±10% to preserve ZVS and maintain soft-switching operation across dynamic alignment states [107]. Excessive detuning enlarges the magnetizing current and may violate EMI constraints by shifting the harmonic envelope toward CISPR-25 limits [108]. Therefore, GaN WPT drivers incorporate adaptive frequency tracking (AFT) and phase-locked resonance control to sustain maximum-efficiency points while minimizing common mode noise [109].

In advanced implementations, ferrite-assisted circular coils are co-simulated with full-bridge GaN drivers in SPICE/Simulink environments to capture the interplay between device switching transients, magnetic coupling variations, and EMI spectral shifts [110]. The high ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ edges of GaN require coordinated gate-loop shaping and snubber damping to prevent radiated leakage through the ferrite interfaces, a challenge that is increasingly addressed by integrated shield winding or multi-layer ferrite tiles [111].

As shown in Figure 16, the optimized ferrite geometry raises mutual inductance by 20–35% under 30 mm misalignment, while reducing leakage flux density near metallic surfaces by nearly 40% [112]. Such characteristics enable mid-range dynamic charging pads and in-motion (dynamic WPT) systems compatible with GaN-based traction inverters and three-dimensional propulsion concepts [113].

II.

Capacitive Power Transfer (CPT) and Compensation Converter Optimization

Where magnetic fields are limited—e.g., aluminum chassis or narrow under-body clearance—capacitive power transfer provides galvanic isolation via coupling plates [114].

The total plate reactance, $X_p$ = −${\displaystyle \frac{1}{\omega C_p}}$, varies with gap and dielectric, so compensation converters are used to achieve a zero-phase angle (ZPA) at the inverter port, minimizing reactive power [115]. For the widely adopted LCL network, ZPA is reached when [116]

$${\omega }^2{L}_s{C}_{eq}(C_p, C_s, R_L)\approx 1$$

(28)

ensuring unity power factor (Cos $\varnothing$ ≈ 1). Alternative LCC and CLC configurations shift part of the reactive cancelation to the secondary side [117,118]:

$${\omega }^2{L}_s{C}_s\approx 1, X_p+ X_{Cc}\approx 0 X_{Cc}= - {\displaystyle \frac{1}{(\omega C_{C)}}}$$

(29)

These variants enable flexible impedance tuning across different load conditions [119]. The LCC network minimizes the circulating current, offering moderate voltage stress [120], while the CLC configuration achieves the thinnest structural form factor, which is beneficial in confined environments such as vehicle chassis or robotic arms [121].

Comparative analysis shows that LCL compensation provides the broadest ZPA tolerance and the highest coupling stability [122], but at the cost of a larger physical footprint and higher magnetic interaction [123]. LCC compensation optimizes current distribution and voltage-stress balance [124], making it suitable for dynamic load conditions [125]. CLC compensation, on the other hand, achieves a compact geometry with high field uniformity [126], although it exhibits a narrower ZPA bandwidth and greater sensitivity to $C_P$ drift or dielectric variation [127].

At higher switching frequencies, GaN-based devices substantially enhance the performance of all three networks [128]. Their ultra-fast switching capability and low output capacitance, $C_{oss}$, reduce the phase delay between voltage and current [129], enabling MHz-range CPT operation with minimal loss [130]. The improved edge control and low gate charge allow for precise modulation of the compensation network, resulting in lower reactive circulation and enhanced electromagnetic compatibility [131].

Overall, GaN’s high-speed operation facilitates compact, high-density CPT systems with a reduced component count and superior unity-power-factor (PF) control [132]. It allows for stable ZPA tracking despite capacitive drift, mechanical misalignment, or load fluctuation [133], ensuring reliable power transfer through dielectric-based couplers [134]. The overall configuration and its phasor relationship are illustrated in Figure 17, which depicts the electric-field coupling mechanism and compensation behavior within a representative CPT topology.

The optimization of capacitive power-transfer architectures not only advances high-efficiency charging interfaces but also lays the groundwork for energy routing in dynamic, multi-axis propulsion systems. The same GaN-enabled compensation strategies that sustain zero-phase-angle (ZPA) operation and high power density in stationary CPT modules extend naturally to the domain of three-dimensional electrified transportation, where converters must operate under rapidly varying load, alignment, and thermal conditions. By exploiting MHz-range switching and precise electric-field control, CPT concepts evolve into lightweight, contactless power-distribution frameworks that are capable of feeding distributed drive modules, actuators, and propulsion coils without magnetic bulk or heavy interconnects. These characteristics make GaN-based CPT topologies a key enabler for compact, thermally efficient, and electromagnetically compliant drive platforms used in vertical-take-off, aerial, and omnidirectional vehicles.

Building on these foundations, Section 3 explores how these converter and material advancements transition into full propulsion systems, analyzing GaN-based architectures for high-voltage buses, dual-active-bridge (DAB) and CLLC converters, and multi-phase inverters. The discussion introduces the power-processing factor (PPF) as a unified figure of merit to evaluate converter efficiency, frequency scalability, and electronic mass in next-generation three-dimensional mobility applications.

III.

Electrified Propulsion for Three-Dimensional Transportation

Emerging vertical-take-off and omnidirectional vehicles extend EV electronics into new mechanical dimensions where weight, cooling, and EMI become co-dominant constraints [135].

Each propulsion module typically contains a high-voltage bus, a bidirectional DAB or CLLC converter interfacing the battery, and multi-phase traction inverters.

To evaluate competing topologies, a useful normalized metric is the power-processing factor [77]

$$\mathrm{PPF}={\displaystyle \frac{\eta f_s}{m_{elec}}}[\mathrm{kHz}/\mathrm{kg}],$$

(30)

which rewards converters that preserve efficiency, η, while raising the switching frequency, $f_s$, and reducing electronic mass, $m_{elec}$ [136].

Parameter selection must jointly satisfy three coupled conditions—thermal, soft-switching, and EMI, which are already formalized in previous sections [137]:

$$T_J= T_{cool, in}+ P_{loss}(f_s, I, \Delta V) (R_{\theta JC}+ R_{\theta Ca}) \le T_{J, max}- H_{th},$$

$${\displaystyle \frac{1}{2}}{L}_{eq}{I}_{dead}^2\ge C_{eq}{V}_{SW}^2, A_{DM/CM}^{req}\left(f\right)=V_{mea}\left(f\right)-V_{lim}\left(f\right)+M$$

The intersection of these constraints defines the feasible operating region [138].

GaN’s low $R_{DS\left(ON\right)}$ and reduced $P_{SW}$ widen this region, achieving higher PPF while maintaining the junction temperature and EMI compliance [46].

As depicted in Figure 18, the design space expands toward a higher frequency and power density compared with Si/SiC counterparts, illustrating the enabling role of GaN in next-generation aerial EV propulsion [139].

This expansion in the GaN design domain translates into measurable propulsion efficiency and weight advantages for aerial electric vehicles (AEVs) and vertical-take-off-and-landing (VTOL) systems [140]. As converter mass and thermal loading scale increase nonlinearly with the switching frequency, GaN’s superior figure of merit (FOM = $R_{DS\left(ON\right)}$ × $Q_g$) permits higher $f_s$ without excessive conduction or gate-drive losses, thus achieving higher specific power (W/kg) and power density (W/L) ratios than Si- or SiC-based designs [141].

Moreover, by supporting the MHz-class operation, GaN allows for drastic downsizing of the magnetics and capacitive components, which are traditionally dominant in propulsion-stage volume [142]. This improvement directly affects the thrust-to-weight ratio of eVTOL platforms and distributed propulsion arrays, where power converters are co-located with individual motors [143]. The resulting architecture minimizes cabling losses, enhances fault isolation, and simplifies EMI containment across high-voltage bus networks [144].

Thermally, GaN’s reduced switching and conduction losses alleviate the need for bulky heat spreaders and enable integrated liquid-cooling or cold-plate microchannel solutions [145]. These compact thermal paths not only stabilize $T_j$ within allowable margins but also maintain soft-switching boundaries over wide ambient and altitude ranges—an essential reliability condition for aerospace-certified propulsion electronics [146].

Furthermore, the enhanced dynamic response and low output capacitance ($C_{OSS}$) of GaN transistors allows for precise modulation of pulse-density or phase-shifted control in CLLC or DAB converters, ensuring continuous soft-switching even under load transients or regenerative braking events [147]. This attribute enhances the bidirectional energy flow and improves the battery-to-thruster efficiency during flight mode transitions [148].

Collectively, these characteristics confirm that GaN is redefining the multi-dimensional performance envelope for electrified propulsion—delivering high efficiency, ultra-fast switching, superior thermal integrity, and compact EMI-compliant power stages that align with the stringent mass–energy balance requirements of next-generation aerial mobility systems.

To extend this performance perspective into long-term operation, it is equally important to evaluate how different converter topologies influence the reliability trajectory of GaN devices under sustained electrical and thermal cycling.

While propulsion-oriented systems demonstrate GaN’s immediate gains in frequency and density, field deployment longevity still hinges on how each topology manages dynamic $R_{DS\left(ON\right)}$ drift, gate bias stress, and junction temperature gradients over repetitive mission profiles [149].

A comparative reliability view, therefore, complements the preceding functional analysis—linking the architecture-level design choices to device-level endurance.

IV.

Reliability Mapping Across Converter Topologies

While GaN devices offer superior switching performance, their long-term reliability strongly depends on the converter architecture and its associated electrical and thermal stress distribution [150]. Different topologies impose distinct duty profiles on the switches, affecting the junction temperature swing $\Delta T_j$, dynamic $R_{DS\left(ON\right)}$ drift, and gate stress $V_{GS}$ cycling amplitude [151].

Table 2. Summary of key reliability mechanisms and mitigation strategies across common GaN converter topologies.

Converter Type	Stress Mechanism	$\mathbf{Typical} \Delta {\mathit{T}}_{\mathit{j}}$ (°C)	Reliability Concern	Remarks/Mitigation
Synchronous Buck/Boost	High repetitive hard-switching, asymmetric conduction	40–60	Dynamic $R_{DS\left(ON\right)}$ drift and hot-carrier injection at high $V_{DS}$	Use soft-gate drive and active snubber to minimize ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ overshoot
Totem-Pole PFC (TPPFC)	Alternating conduction between the fast GaN leg and the slow SiC/SBR leg	50–70	Cross-conduction and body-diode dynamic recovery heating	Optimize dead time; synchronous mode with gate-voltage shaping reduces reverse stress [152]
CLLC Resonant/Dual Active Bridge	ZVS/ZCS transitions minimize switching stress; thermal stress from circulating current	20–40	Bias temperature instability in continuous operation	Design for balanced magnetizing current; ensure minimal residual hard commutation
Vienna/T-type NPC	Multi-device series paths share voltage but increase thermal imbalance risk	45–65	Unequal device aging, gate charge mismatch	Thermal coupling through the baseplate and dynamic current sharing improve lifetime consistency [153]
Bidirectional OBC/DC-link SST	High-frequency bidirectional power flow	30–55	Repetitive dynamic stress; EMI–thermal co-coupling	Spread-spectrum modulation and digital THD control reduce repetitive EMI-induced heating [154]

summarizes the main reliability–topology correlations.

Quantitative mission profile simulations using a 400 V/3.3 kW Vienna rectifier and a 1 MHz GaN-based CLLC converter (adapted from [21,68]) show that the average junction temperature rise is 25–40 °C lower in soft-switching topologies compared to hard-switched buck–boost equivalents at the same output power. This translates to a 2–3× improvement in mean time to failure (MTTF), according to the Arrhenius relationship:

$$\mathrm{MTTF} \propto e^{({\displaystyle \frac{E_a}{k T_j }})},$$

(31)

where $E_a$ is the activation energy for failure, and k is the Boltzmann constant.

Soft-switching topologies, such as CLLC and DAB, therefore, provide a reliability–efficiency co-optimization, whereas TPPFC and buck-derived stages demand stricter gate-driver voltage control and thermal balancing to suppress dynamic $R_{DS\left(ON\right)}$ degradation.

Overall, mapping reliability against topology reveals that soft-commutated GaN converters (e.g., CLLC, DAB) dominate in sustained operation, due to their low ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ stress and narrower thermal cycling amplitude, while hard-switched structures (buck, TPPFC) require enhanced gate management and EMI mitigation to achieve comparable device endurance.

6. EMI and Compliance: Dual-LISN DM/CM Workflow and a Practical Topology-Selection Framework

Abbreviations used in this section: electromagnetic interference (EMI), differential-mode (DM), common-mode (CM), and line impedance stabilization network (LISN).

A.

Dual-LISN representation with compact DM/CM emission models

In CISPR-25 style benches for EV power converters, two 5 µH/50 Ω LISNs (line and return) enable the orthogonal reconstruction of differential-mode (DM) and common-mode (CM) conducted emissions from the simultaneously acquired port voltages $V_{+}\left(f\right)$ and $V_{-}\left(f\right)$ [155]. The standard relations are [156]

$$V_{DM}\left(f\right)={\displaystyle \frac{V_{+}\left(f\right)-V_{-}\left(f\right) }{2}}, V_{CM}\left(f\right)={\displaystyle \frac{V_{+}\left(f\right)+V_{-}\left(f\right) }{2}}$$

(32)

With each LISN port ~50Ω to ground, the implied noise currents are [157]

$$I_{DM}={\displaystyle \frac{V_{DM}}{50 \Omega }} \mathrm{and} I_{CM}={\displaystyle \frac{V_{CM}}{50 \Omega }}(\mathrm{two} \mathrm{shunts} \mathrm{in} \mathrm{parallel})$$

(33)

The analytical relations in (32) assume perfectly balanced LISNs and symmetric cabling. In experimental setups, stray capacitance to chassis and probe loading can distort $V_{DM}$ and $V_{CM}$. Measurement accuracy improves when the setup is calibrated with a 150 Ω reference source or a verified LISN pair to account for these non-idealities, which also matches the current probe method annotated in Figure 19. Comparing $V_{DM}\left(f\right)$ and $V_{CM}\left(f\right)$ (dBµV) to the selected limit lines yields the required attenuation with a modest margin, M, to cover unit-to-unit spread [158]:

$$A_{DM}^{req}\left(f\right)= V_{DM}\left(f\right)- V_{lim, DM}\left(f\right)+ M, A_{CM}^{req}\left(f\right)= V_{CM}\left(f\right)- V_{lim, CM}\left(f\right)+M$$

(34)

We measured the spectra map naturally to compact physical models. As illustrated in Figure 19, CM noise is driven by the capacitive injection from hot switch nodes, packages, heat-sinks, and interwinding capacitances to the chassis, which was well-approximated by [159]

$$i_{CM}\left(\mathrm{t}\right) \approx C_{par}{\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.},$$

(35)

where $C_{par}$ is the effective parasite to the chassis. DM content follows the input current slew through the loop inductance in the line/return path [160]:

$$v_{par}\left(\mathrm{t}\right) \approx L_{par}{\displaystyle \raisebox{1ex}{$di$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.},$$

(36)

The high-frequency power that excites the spectrum is bounded by the energy required to commutate device/output capacitances each cycle [161],

$$E_{SW}\approx {\displaystyle \frac{1}{2}}{C}_{OSS}{V}^2, P_{SW, HF}\approx f_S{E}_{SW},$$

(37)

so GaN’s low $C_{oss}$ is intrinsically favorable—provided the effective dv/dt and high-frequency loop areas are controlled by topology and layout [162]. Figure 20 illustrates these DM/CM return-path mechanisms and the LISN-based reconstruction in (32)–(34).

B.

From attenuation targets to realizable DM/CM networks, with integrated topology/edge-shaping selection and thermal co-constraints

The attenuation targets in (15) define the stopband placement of the DM/CM networks. For a chosen second-order corner and characteristic impedance,

$$f_c={\displaystyle \frac{1}{2\pi \sqrt{LC}}}, Z_O={\displaystyle \frac{1}{ \sqrt{LC}}} \Rightarrow \mathrm{L}={\displaystyle \frac{Z_O}{ 2\pi f_c}}, \mathrm{C}={\displaystyle \frac{1}{2\pi f_{c } Z_O}}$$

(38)

first-order element values follow directly. Reported OBC front ends commonly realize DM sections as series-L/shunt-C across the line and return (powder-iron cores tolerate ripple), while CM chokes employ high-µ ferrites with deliberate leakage, so the DM path does not peak [163]. Damping near $Z_O$ suppresses residual resonances [164],

$$R_{damp}\approx (0.3–1) Z_O\left(\mathrm{placed}\mathrm{in}\mathrm{series}\mathrm{with}\mathrm{shunt}\text{-}\mathrm{C}\mathrm{or}\mathrm{as}\mathrm{an}\mathrm{RC}\mathrm{across}\mathrm{the}\mathrm{choke}\right),$$

(39)

and any switch-node snubber is checked against the thermal budget through [165]:

$$P_{snub}\approx {\displaystyle \frac{1}{2}} C_{snub}{V}^2{f}_s$$

(40)

Because the same parasites that generate emissions also determine filter efficacy, layout is a first-stage filter: minimize the switch–capacitor–FET current triangle, provide a Kelvin-source return for the driver, partition “noisy” and “quiet” reference planes with a single CM tie near the LISN side, and maintain creepage from hot nodes to chassis to reduce $C_{par}$ and $L_{par}$ in (35) and (36) [41]. As depicted in Figure 21, a damped input EMI filter with series $L_f$ and shunt $C_f$ sets the cutoff; a damping capacitor $C_d$ (across $C_{IN}$) or an RC branch mitigates peaking between $V_A$ and $V_B$.

The DM/CM attenuation targets and any switch-node snubbing consume thermal headroom from the profile-aware derating map in Section 3. Hence, the feasible EMI solution set is the intersection of the following: (i) the ZVS/ZCS conditions and circulating current limits of Section 5, and (ii) the junction-temperature and dynamic-$R_{DS\left(ON\right)}$) screens of Section 3. Designing EMI and reliability concurrently avoids meeting CISPR-25 at the expense of long-term device margins.

C.

Decision map linking EMI, efficiency, power density, and complexity

EMI compliance is co-determined by these networks and by the chosen topology and edge shaping. Soft-switching DC–DC stages (LLC/CLLC/DAB; Section 5) shift energy out of DM-critical bands and lower CM injection by reducing the effective ΔV at switching nodes; three-level AC–DC front ends (Vienna, T-type; Section 4) halve device-node voltage swing relative to two-level legs, easing CM filtering [166].

The feasible operating region is the intersection of:

• Sufficient ZVS/ZCS margin from the resonant/bridge analysis;
• The derating map from Section 3 (junction-temperature limit and any dynamic $R_{DS\left(ON\right)}$ screen);
• A compact DM/CM network that delivers $A^{req} \left(f\right)$ from (34) with acceptable damping and $P_{snub}$ from (40) [167].

These coupled constraints are conveniently visualized by a Pareto/decision map whose axes are efficiency, η, power density, ρ, EMI margin, ΔE (dB below the limit after filtering), and implementation complexity, C (device/driver count, balancing and control). In such maps, single-phase TP-PFC + LLC/CLLC tends to maximize ρ at moderate C; Vienna + CLLC commonly leads in η and ΔE at a higher power, due to three-level commutation; and T-type NPC + DAB offers native bidirectionality with similar CM advantages but a higher C and circulating current thermal cost [168].

The preferred operating point is where the chosen topology, switching frequency, and ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$ not only meet the attenuation targets, but also lie inside the shaded thermal-reliability region established earlier. As depicted in Figure 22, the Pareto map (η vs. ρ; marker size ∝ complexity; labels give EMI margin ΔE) highlights the feasible operating region as the shaded thermal-reliability envelope and guides the final topology/$f_s$ choice.

The decision map in Figure 22 provides a graphical trade-off among efficiency, power density, EMI margin, and implementation complexity. However, to contextualize this theoretical envelope with experimentally demonstrated systems, it is essential to benchmark the real GaN-based converter results reported in the recent literature. Such comparative evaluation links the analytical framework developed in Section 3, Section 4 and Section 5 with practical data measured under standardized CISPR-25 or DO-160 test environments.

Therefore, a consolidated benchmarking study has been performed, summarizing representative prototypes of GaN-based EV subsystems—including on-board chargers (OBCs), DC–DC converters, and traction inverters—published between 2019 and 2025. Each entry in

Table 3. Comparative benchmarking of GaN-based EV converter subsystems (2019–2025): efficiency (η), power density (ρ), and EMI margin (ΔE) across representative OBC, DC–DC, and inverter implementations.

Subsystem	Topology	${\mathit{F}}_{\mathit{s}}$ (kHz)	η (%)	Power Density (W/L)	$\mathbf{EMI} \mathbf{Margin} \Delta \mathit{E}$ (dBµV Below Limit)	Reference Range (2019–2025)
OBC (400 V)	GaN TP-PFC + CLLC	200–500	96–98	3.5–5.0	−5 to −8	[46]
OBC (800 V)	GaN T-Type 3L + DAB	150–300	95–97	4.2–4.8	−4 to −7	[169]
DC–DC Stage	LLC/CLLC	300–1000	96–98	6.0–9.0	−3 to −6	[141]
Traction Inverter	3-Phase GaN NPC	100–200	98–99	7.5–10	−2 to −5	[170]
EMI Filter Benchmarks	Hybrid CM/DM Filter + GaN Leg	500–1000	-	-	−6 to −10	[171]

quantifies efficiency (η), volumetric power density (ρ), and EMI margin (ΔE dBµV below the applicable limit), normalized on a per-kilowatt basis to ensure fair comparison across voltage classes and topologies.

This extension transforms the synthesis into a semi-quantitative validation step: it demonstrates how GaN technology simultaneously advances switching frequency, thermal stability, and EMI compliance compared with its Si/SiC counterparts, thereby validating the proposed framework and expanding its relevance beyond analytical modeling to real experimental practice.

The consistency between the Pareto envelope in Figure 16 and the experimental range summarized in Table 3 confirms that GaN technology now occupies the optimal efficiency–density–EMI space for EV power electronics [172]. This alignment validates the proposed decision framework as a predictive design tool for next-generation converter optimization.

While the decision framework in Figure 22 effectively maps efficiency, power density, EMI margin, and implementation complexity, a complete roadmap must also define measurable design milestones. In current EV system development, performance validation requires quantifiable targets rather than qualitative trends. Hence, this section extends the analytical and benchmarking discussion toward a metrics-driven roadmap, establishing explicit technical goals for GaN platforms across 400 V and 800 V domains.

These targets provide the missing link between converter-level optimization and subsystem-level validation, integrating the reliability, thermal, and EMI constraints derived throughout Section 3, Section 4, Section 5 and Section 6. The roadmap serves both as a verification checklist and as a guide for future GaN integration in high-voltage EV architectures. The quantitative metrics, summarized in

Table 4. Quantitative roadmap targets for GaN-based EV converter subsystems at 400 V and 800 V platforms.

Subsystem	Platform	Topology Band (Favored)	${\mathit{F}}_{\mathit{s}}$ (kHz)	Target η (%)	$\mathbf{Target} \mathit{\rho }$ (W/L)	$\mathbf{Target}\Delta \mathit{E}$ (dBµV)	$\mathbf{Thermal} \mathbf{Headroom} {\mathit{H}}_{\mathit{t}\mathit{h}}$
OBC AC-DC [46]	400 V	TP-PFC → LLC/CLLC	150–400 kHz	≥97.5%	≥4.5	≤−6 (150 k–30 MHz)	≥15 °C at $T_{Cool, in}$ = 15 °C
OBC AC-DC	800 V [173]	3L Vienna/T-type NPC	120–300 kHz	≥97.0% (Vienna), ≥96.5% (T-type)	≥4.2	≤−5	≥12 °C
Isolated DC-AC [174]	400 V	LLC/CLLC, DAB	300–900 kHz	≥97.8% (peak), ≥97.0% (rated)	≥6.5	≤−6	≥15 °C
Isolated DC-AC [175]	800 V	3L-LLC/CLLC or DAB	250–700 kHz	≥97.2%	≥5.8	≤−5	≥12 °C
Traction Inverter [176]	400 V	3-phase NPC (GaN)	60–150 kHz	≥98.8%	≥8.0	≤−3 (DM bands; CM shaping)	≥10 °C
Traction Inverter [177]	800 V	3-phase NPC (GaN, stacked/3L)	50–120 kHz	≥98.3%	≥7.0	≤−3	≥10 °C

, express realistic boundary conditions that next-generation converters must achieve to align with the proposed framework.

Roadmap with Quantitative Targets and Verification Path

To translate the selection framework into deployable specifications, we define the following metrics used throughout the paper:

• Efficiency: η at rated load (and a light-load point).
• Power density: ρ in W/L (converter volume excludes cabling).
• EMI margin: ΔE = (measured DM/CM level − limit) in dBµV, negative is a compliant margin.
• Power-processing factor: PPF = ${\displaystyle \frac{\eta f_s}{M_{elec}}}$ (Equation (30)).
• Thermal headroom: $H_{th}$= $T_{J, max}$ − $T_J$ under mission profile load (Equation (4)).

Table 4 sets platform-specific technical targets for GaN EV subsystems. These values are selected to (i) retain ZVS/ZCS feasibility (Section 5), (ii) remain within the derating envelope (Section 3), and (iii) pass CISPR-25 conducted-EMI with a margin, using the dual-LISN workflow (Section 6).

Achieving the Table 4 milestones while remaining within the thermal reliability and EMI envelope of Figure 16 defines a quantitative benchmark for GaN EV converters. Together with the experimental benchmarking in Table 4, this roadmap transforms the study from a qualitative synthesis into a metrics-validated design framework—linking analytical derivations, empirical data, and verifiable subsystem targets for future 400 V/800 V platforms.

7. Conclusions and Roadmap

This review traced GaN from device physics to EV system design, showing how low charge and high critical fields translate into higher switching frequency, smaller passives, and high efficiency—provided ${\displaystyle \raisebox{1ex}{$dv$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.}$, parasitics, and thermal paths are co-controlled. Real drive cycle analysis linked device heating and dynamic $R_{DS\left(ON\right)}$ to vehicle-level thermal budgets; three-level front ends (Vienna, T-type) were shown to halve device stress and ease CM emissions; and isolated stages (LLC/CLLC/DAB) were framed with explicit ZVS/ZCS conditions and scaling limits. A dual-LISN DM/CM workflow tied measured spectra to compact source models and to filter synthesis within thermal headroom, yielding a practical selection map that balances efficiency, power density, EMI margin, and implementation effort.

The proposed roadmap also bridges the gaps identified in the introduction by integrating reliability analysis under real drive cycles, vehicle-level thermal coordination of junction-to-coolant paths with magnetic and EMI losses, and seamless scalability toward 400 V and 800 V EV architectures. By aligning these aspects with measurable EMI and thermal margins, the roadmap transforms open research challenges into actionable design parameters that can be validated through both simulation and hardware prototyping.

Future work should emphasize data-driven parameter extraction—from mission-profile logging to electro-thermal digital twins and lifetime estimation—so that reliability, EMI compliance, and efficiency can be optimized concurrently within a unified design framework.