Non-Isolated High Step-Up DC-DC Interleaved Boost Converter Based on Coupled Inductors and Voltage Multiplier Cells

Abstract

This work introduces a non-isolated high step-up dc-dc interleaved boost converter combining magnetic coupling and voltage multiplier cells (VMCs). The proposed topology features a transformer with two primary windings of equal turns, interconnected to each other, enabling improved current sharing, and multiple secondary windings that contribute to extending the voltage gain. A three-winding coupled inductor is integrated into the design, while VMCs not only boost the output voltage but also significantly reduce the voltage stresses on the switches, eliminating the need for extreme duty ratios. The converter exhibits inherent modularity, allowing for voltage gain adjustments either through the turns ratio of the coupled inductor or by incorporating additional VMCs. An in-depth analysis of the topology is derived, and an experimental prototype rated at 48 V/400 V, 25 kHz, and 1 kW is implemented to verify and validate the theoretical claims, achieving an efficiency of 95.12% at full-load conditions.

1. Introduction

Several modern applications rely on dc-dc converters, such as general-purpose switch-mode power supplies (SMPSs), electric vehicles (EVs), uninterruptible power systems (UPSs), renewable energy conversion systems, and telecommunications, among others [1]. When galvanic isolation is not a mandatory requirement, non-isolated high step-up dc-dc converters are interesting choices to extend the voltage gain and achieve high power density rather than using high-frequency transformers [2].

In several applications, including grid-connected and standalone photovoltaic (PV) systems, such converters play a crucial role in supplying a cascade inverter with a high dc-link voltage, thereby eliminating the need to connect multiple dc voltage sources, such as PV modules or batteries, in series [3]. According to [4], to achieve typical root mean square (rms) ac voltages of 127 V or 220 V, dc-link voltages of approximately 250 V or 400 V are necessary, respectively, with these ratings considered conservative. As for three-phase systems, dc-link voltages of around 400 V or 800 V are typically required to produce rms phase voltages of 127 V or 220 V, respectively.

Notably, the conception of novel non-isolated high step-up converters has been a hot topic in power electronics research. According to [5], several techniques can extend the conversion ratio of basic dc-dc converter topologies, such as voltage lifting, switched capacitors, switched inductors, magnetic coupling, and voltage multiplier cells (VMCs), as well as a combination of multiple solutions. For instance, combining switched capacitors and coupled inductors with the conventional boost converter, as demonstrated in [6,7], results in an extended voltage gain and reduced stress on the semiconductor devices. Similarly, the family of converters based on magnetic coupling and ladder switched capacitors, as proposed in [8], can achieve good trade-offs between voltage gain and component count. Another interesting possibility for improving power density in such structures involves the use of wide-bandgap semiconductors and the adoption of magnetic integration approaches, as discussed in [9,10], respectively.

In this sense, a plethora of novel structures have been proposed in the literature, primarily aiming to achieve the highest possible voltage gain. However, the comprehensive analysis presented in [11] showed that this is not the only aspect that matters, as distinct design trade-offs involving voltage gain, component count, semiconductor stresses, cost, and power density must also be taken into account.

The input currents of non-isolated high step-up converters are often high, even at low power ratings of around few hundred watts. This issue motivated the application of the interleaving concept to develop multi-phase structures capable of achieving partial ripple cancellation, high efficiency, and enhanced thermal distribution [12]. For instance, the six-phase interleaved boost converter proposed in [13] can achieve very high efficiency in a marine hybrid system powered by fuel cells. However, it cannot reach a high voltage gain. Conversely, the topology addressed in [14] integrates a voltage-lift capacitor and a VMC into a two-phase interleaved boost converter to mitigate this inconvenience, but some important drawbacks cannot be neglected. While the input current presents a large ripple, a clamping circuit is required to mitigate the high voltage spikes on the switches due to coupled windings associated with the input filter inductors. Despite requiring a low component count, the efficiency is around 92% at the rated power of 1000 W, rendering the topology unfeasible for high-power applications.

The interleaved boost converter proposed in [15] has the advantage of being a minimum-phase system without right-half-plane (RHP) zeros, operating over a wide duty cycle range with low voltage stress on the switch. While the converter was designed for a rated power of 200 W only, it cannot reach very high gains. Combining a voltage-lift capacitor and coupled inductors as in [16] offers enhanced voltage gain. Furthermore, an active clamping circuit allows for soft-switching operation of the converter, reaching a high efficiency of around 96.5% at 210 W.

The interleaved boost converter based on a built-in transformer, as presented in [17], significantly extends the voltage gain by employing two voltage-doubler circuits composed of diodes and capacitors on the secondary side. This configuration also recycles the energy stored in the transformer’s leakage inductance. Although the efficiency remains consistent over a wide load range, it reaches only 93% at the rated power of 200 W. Meanwhile, the high-gain interleaved dc-dc converter introduced in [18] relies on an asymmetric VMC (AVMC) and a lossless passive snubber. Compared to the classical interleaved boost converter, it can achieve much higher voltage gains due to the AVMC and a coupled inductor. It exhibits low input current ripple as a result of the interleaved structure, and the voltage stresses on both switches and diodes are substantially low, enabling the use of semiconductors with low on-resistance.

The two-switch boost converter based on a three-winding coupled inductor and a charge pump circuit introduced in [19] can achieve moderate voltage gain while incorporating important advantages such as magnetic integration. However, other drawbacks, such as large input current ripple and lack of a common ground connection, cannot be neglected in the design. Another configuration incorporating a built-in transformer and VMCs, assessed in [20], provides an extended voltage gain and high efficiency.

The configuration introduced in [21] relies on a VMC to obtain a voltage gain approximately three times greater than that of the traditional boost converter. Although its component count remains low, the approach is suitable only for modest conversion ratios. In contrast, the topology in [22] employs switched capacitors in conjunction with step-up cells to enhance the gain. However, the need for seven inductors renders the design bulky and unfeasible for practical applications.

To achieve higher conversion ratios, interleaved boost converters combined with coupled inductors have been investigated in the literature. By selecting appropriate turns ratios, excessively high duty ratios can be avoided, thereby reducing conduction losses in power switches. The converter analyzed in [23] exemplifies this approach by integrating two magnetically coupled windings into the input filter inductors, resulting in reduced voltage stress on the switches and a manageable component count. A similar architecture designed for PV systems is evaluated in [24]. While it exhibits high efficiency at around 900 W, the voltage gain remains below three, a performance already achievable with a conventional two-phase interleaved boost converter without the need for advanced step-up techniques or additional circuitry.

High voltage gains can also be achieved by combining coupled inductors with multiple passive elements, as demonstrated in [25]. Although this configuration provides a voltage gain close to 20, the experimental prototype operates at relatively low power levels and fails to achieve high efficiency under full-load conditions. Additionally, voltage multiplier rectifiers (VMRs) have been combined with coupled inductors in [26]. However, voltage imbalance across output capacitors remains a critical issue, limiting their applicability in real-world systems.

A design associating a VMC with a built-in transformer is proposed in [27]. Although the experimental results demonstrate satisfactory current sharing between the system phases, this behavior is not inherent in the topology and depends heavily on the precise matching of input filter inductors. A family of interleaved high step-up converters employing magnetic coupling is introduced in [28]. Despite voltage gains being proportional to the square of the duty cycle, potential drawbacks include a high component count, the need for active devices with distinct voltage and current ratings, and the lack of a common ground connection.

Another approach consisting of integrated coupled inductors and built-in transformers, as demonstrated in [29], can enhance the voltage gain while enabling optimization through turns ratio adjustments of the magnetic elements. However, the bulky nature of the resulting hardware restricts its application primarily to low-power systems. In contrast, the converter introduced in [30] adopts a series-stacked architecture to provide high step-up, but at the cost of a significantly higher component count.

The cascaded two-stage architecture presented in [31] achieves ultra-high voltage gain by combining advanced techniques such as interleaving, switched-capacitor networks, and magnetic coupling. Despite these innovations, its overall efficiency remains low, limiting its applicability in high-power scenarios. The structure employing two three-winding magnetic couplers and a pair of VMCs explored in [32] also achieves a high conversion ratio. However, the experimental results reveal significant voltage spikes on the active switches, primarily caused by the leakage inductance.

Overall, it is reasonable to state that non-isolated dc-dc interleaved boost converters available in the literature can be classified into three major groups:

(1)

Topologies with high or ultra-high voltage gain and rated power in the range of a few hundred watts, available in thousands of publications.

(2)

Topologies with low voltage gain and power levels ranging from a few kilowatts to tens of kilowatts, as seen in conventional interleaved converters without high step-up capability.

(3)

Topologies with high voltage gain and rated power in the range of a few kilowatts, which are addressed in a significantly smaller number of works.

In the context of the third group, this work presents a novel non-isolated high step-up dc-dc interleaved boost converter integrating magnetic coupling and voltage boosting techniques to enhance performance. The topology relies on a transformer with two primary windings of equal turns, interconnected to each other, with the aim to ensure balanced current sharing, yielding enhanced performance over conventional interleaved designs, as outlined in [33]. Multiple secondary windings contribute to an extended voltage gain without resorting to extreme duty ratios. Additionally, a three-winding coupled inductor is incorporated to further enhance energy transfer, while VMCs not only contribute to increasing the output voltage but also significantly reducing voltage stress on the switches. One of the key advantages lies in the converter’s modularity, which allows for a flexible design through adjustments in the number of secondary windings, the turns ratio of the coupled inductor, or the number of VMCs. This results in low current and voltage stress on the switches and diodes, high efficiency, and moderate component count.

These features yield an efficient solution for both standalone and grid-connected single-phase inverters, especially those operating at dc voltage levels around 400 V, as commonly required in PV systems. The converter is also suitable for battery-powered systems involving output voltages in the range of several hundred volts. Furthermore, a promising application lies in connecting the converter directly to the dc bus of a microgrid, thereby eliminating redundant power processing stages in renewable energy systems such as PV and fuel cell-based architectures.

The structure of this article is outlined as follows. Section 2 describes the interleaved boost converter, including a thorough theoretical analysis in continuous conduction mode (CCM) and a comprehensive design procedure comprising all power stage elements. Section 3 compares the proposed structure with other similar counterparts found in the recent literature. Section 4 presents the experimental results obtained from a laboratory prototype rated at 48 V/400 V, 25 kHz, and 1 kW. Finally, Section 5 summarizes the main findings of this study.

2. Proposed Non-Isolated High Step-Up Interleaved Boost Converter

Figure 1 depicts the proposed high step-up converter, which is feasible for high-power, high-current applications. It relies on a transformer whose primary windings, with equal numbers of turns N_1p1 and N_1p2, are interconnected to each other. It is worth noting that magnetic coupling in this case ensures improved current sharing compared to conventional two-phase interleaved converters because the primary windings have the same impedance, as demonstrated in [34].

It is also possible to couple multiple secondary windings with turns N_1s1…N_1sn to the transformer, associated with diodes D_s1…D_sn and capacitors C_s1…C_sn, aiming to extend the voltage gain. Two branches composed of switches S₁, S₂ and diodes D₁, D₂ operate in an interleaved manner, relying on gating signals shifted by 180°. A three-winding coupled inductor represented by N_2p1, N_2s1, and N_2s2 offers another degree of freedom for increasing the output voltage. In turn, VMCs composed of diodes D_m1…D_m(n+1) and capacitors C_m1…C_m(n+1) allow for not only achieving a high gain, but also minimizing the voltage stresses on the switches as more VMCs are incorporated into the circuit. The topology also comprises the input voltage source V_i, the input filter inductor L₁, the output filter capacitor C_o, and the load R_o.

2.1. Qualitative Analysis

To perform the theoretical analysis of the converter operating in CCM, it is assumed that all power stage components are ideal; the primary windings of the transformer have the same number of turns so that the input current is equally shared between the phases; the converter operates in a steady-state, with a duty ratio D ≥ 0.5; the control signals of the active switches are phase-shifted by 180°; and the switching frequency remains constant. The corresponding operating stages and theoretical waveforms are illustrated in Figure 2 and Figure 3, respectively.

First stage [t₀, t₁] (Figure 2a): Both switches S₁ and S₂ are on. The current through inductor L₁ increases linearly as it stores energy. Part of this current flows through one of the transformer windings (N_1p1), shared between S₁ and N_2p1, while the other part, of equal magnitude, flows through N_1p2 and S₂, since N_1p1 and N_1p2 have the same number of turns. Meanwhile, diodes D₁, D₂, D_m1, D_m2, D_s1, and D_s2 are reverse-biased. The load is supplied due to the discharge of capacitors C_o, C_s1, and C_s2. This stage ends when S₂ is turned off.

The time interval Δt₁, which defines this stage, can be calculated using (1).

$$\mathrm{\Delta }{t}_1=t_1-t_0=\left(D-{\displaystyle \frac{1}{2}}\right)T_s,$$

(1)

where T_s is the switching period.

Second stage [t₁, t₂] (Figure 2b): Switch S₁ remains on, while switch S₂ is off. The voltage polarity across L₁ is reversed, causing the current to decrease linearly. Diode D_s2 becomes forward-biased, while D_s1, D_m1, D_m2, D₁, and D₂ remain reverse-biased. Capacitor C_s2 begins charging, while C_o and C_s1 continue discharging. This stage ends when D₁ is forward-biased.

The time interval Δt₂, which defines this stage, can be calculated using (2).

$$\mathrm{\Delta }{t}_2=t_2-t_1={\displaystyle \frac{C_o{C}_{s1}\mathrm{\Delta }{V}_{Co}}{I_o\left(C_o+C_{s1}\right)}},$$

(2)

where I_o is the average output current and ΔV_Co is the peak-to-peak voltage ripple across C_o.

Third stage [t₂, t₃] (Figure 2c): Switches S₁ and S₂ are on and off, respectively. Diodes D₁ and D_s2 are forward-biased, while diodes D_s1, D₂, D_m1, and D_m2 remains reverse-biased. The voltage across L₁ remains negative, causing the current to continue decreasing linearly. Capacitor C_o begins charging, but C_s1 and C_s2 continue discharging and charging, respectively. This stage ends when D_m2 is forward-biased.

The time interval Δt₃, which defines this stage, can be calculated using (3).

$$\mathrm{\Delta }{t}_3=t_3-t_2={\displaystyle \frac{C_{s1}\mathrm{\Delta }{V}_{Cs1}}{I_o}},$$

(3)

where ΔV_Cs1 is the peak-to-peak voltage ripple across C_s1.

Fourth stage [t₃, t₄] (Figure 2d): Switches S₁ and S₂ remain on and off, respectively. Diodes D_m2, D₁, and D_s2 are forward-biased, but diodes D_s1, D₂, and D_m1 reverse-biased. Capacitors C_o and C_s2 charge, whereas capacitor C_s1 discharges into the load. This stage ends when S₂ is turned on.

The time interval Δt₄, which defines this stage, can be calculated using (4).

$$\mathrm{\Delta }{t}_4=t_4-t_3=T_s-D{T}_s-{\displaystyle \frac{C_{s1}\mathrm{\Delta }{V}_{Cs1}}{I_o}}-{\displaystyle \frac{C_o{C}_{s1}\mathrm{\Delta }{V}_{Co}}{I_o\left(C_o+C_{s1}\right)}},$$

(4)

Fifth stage [t₄, t₅] (Figure 2e): This stage is similar to the first one and ends when S₁ is turned off. Its respective time interval Δt₅ is also defined by (1).

Sixth stage [t₅, t₆] (Figure 2f): This stage is complementary to the second one, with diode D_s1 becoming forward-biased instead of D_s2. This stage ends when D₂ is forward-biased. Its respective time interval Δt₆ is also defined by (2).

Seventh stage [t₆, t₇] (Figure 2g): This stage is analogous to the third one. Switches S₁ and S₂ remain off and on, respectively. Diode D_s1 is forward-biased, while diodes D_s2, D₁, D_m1, and D_m2 remain forward-biased. The voltage across L₁ is negative, as its current continues to decrease linearly. Capacitor C_o begins charging, but C_s1 and C_s2 continue charging and discharging, respectively. This stage ends when D_m1 becomes forward-biased, with its respective time interval Δt₇ given by (3).

Eighth stage [t₇, t₈] (Figure 2h): This stage is complementary to the fourth one. Switch S₂ remain on, while switch S₁ is off. Diodes D_m1, D₂, and D_s1 are forward-biased. However, diodes D_s2, D₁, and D_m2 are reverse-biased. Capacitors C_o and C_s1 charge, while capacitor C_s2 discharges into the load. This stage ends when S₁ is turned on again, with its respective time interval Δt₈ given by (4).

2.2. Quantitative Analysis

By analyzing Figure 2 and Figure 3, it is possible to apply the volt-second balance principle to inductor L₁ to obtain (5) and (6).

$$V_{L1}={\displaystyle \frac{2}{T_s}}\left[{\displaystyle \underset{0}{\overset{D{T}_s-\frac{T_s}{2}}{\int }}\left(V_i\right)dt+}{\displaystyle \underset{0}{\overset{\left(1-D\right)T_s}{\int }}\left(V_i-V_{N1\left(\max \right)}\right)dt}\right]=0,$$

(5)

$$V_i\left(D{T}_s-{\displaystyle \frac{T_s}{2}}\right)=\left[V_{N1}-V_i\right]\left[\left(1-D\right)T_s\right],$$

(6)

where V_L1 is the average voltage across L₁, V_i is the input voltage, and V_N1(max) represents the maximum voltage across the primary windings of the transformer. Therefore, the maximum voltage across the primary windings of the transformer is given by (7).

$$V_{N1\left(\max \right)}=V_{N1p1\left(\max \right)}=V_{N1p2\left(\max \right)}={\displaystyle \frac{V_i}{2\left(1-D\right)}}.$$

(7)

Furthermore, the output voltage V_o is equal to the sum of the average voltages across capacitors C_o, C_s1, and C_s2, corresponding to V_Co, V_Cs1, and V_Cs2, respectively, according to (8).

$$V_o=V_{Co}+V_{Cs1}+V_{Cs2}.$$

(8)

It is also possible to calculate V_Co, V_Cs1, and V_Cs2 from (9) and (10), where n₁ and n₂ account for the turns ratio of the transformer and coupled inductor, as defined by (11) and (12), respectively.

$$V_{Co}={\displaystyle \frac{V_i\left(n_2+mc\right)}{\left(1-D\right)}},$$

(9)

$$V_{Cs1}=V_{Cs2}={\displaystyle \frac{V_i{n}_1}{2\left(1-D\right)}},$$

(10)

$$n_1={\displaystyle \frac{N_{1s1}}{N_{1p1}}},$$

(11)

$$n_2={\displaystyle \frac{N_{2s1}}{N_{2p1}}}={\displaystyle \frac{N_{2s2}}{N_{2p1}}}=\sqrt{{\displaystyle \frac{L_{2s1}}{L_{2p1}}}}=\sqrt{{\displaystyle \frac{L_{2s2}}{L_{2p1}}}},$$

(12)

where mc is the number of VMCs; N_1p1 and N_1s1 are the number of turns of the primary and secondary windings of the transformer, respectively; N_2p1, N_2s1, and N_2s2 are the number of turns of the coupled inductor’s windings; and L_2p1, L_2s1, and L_2s2 are the self-inductances of the coupled inductor’s windings.

Thus, substituting (9) and (10) into (8), it is possible to calculate the voltage gain G_V of the ideal converter according to (13). If the leakage inductance of the coupled inductor (L_lkg) is considered in the analysis, the gain will be obtained using (14).

$$G_V={\displaystyle \frac{V_o}{V_i}}={\displaystyle \frac{\left(n_1+n_2+mc\right)}{1-D}},$$

(13)

$$G_V={\displaystyle \frac{V_o}{V_i}}={\displaystyle \frac{\left(n_1+\sqrt{\frac{L_{2s1}}{L_{2p1}+L_{lkg}}}+mc\right)}{1-D}}.$$

(14)

The input filter inductance can be determined from (15).

$$L_1={\displaystyle \frac{V_o\left(1-D\right)\left(2D-1\right)}{2f_s\mathrm{\Delta }{I}_{L1}\left(n_1+n_2+mc\right)}},$$

(15)

where ΔI_L1 represents the peak-to-peak current ripple through L₁ and f_s is the switching frequency.

It is possible to determine C_o, C_s1, and C_s2 from (16) and (17).

$$C_o={\displaystyle \frac{P_{o}D\left(1-D\right)}{2V_i{f}_s\mathrm{\Delta }{V}_o\left(n_1+n_2+mc\right)}},$$

(16)

$$C_{s1}=C_{s2}={\displaystyle \frac{D\cdot P_o\left(1-D\right)}{V_i{f}_s\mathrm{\Delta }{V}_o\left(n_1+n_2+mc\right)}},$$

(17)

where ΔV_o is the peak-to-peak output voltage ripple and P_o is the output power.

The VMC’s capacitances C_m1 and C_m2 can be calculated from (18).

$$C_{m1}=C_{m2}={\displaystyle \frac{I_{L1}\left(1-D\right)}{4f_s\mathrm{\Delta }{V}_{Cm}}},$$

(18)

where I_L1 is the average current through L₁, which is equal to the average input current I_i; and ΔV_Cm represents the peak-to-peak voltage ripple across the multiplier capacitors.

The average and rms currents through the active switches are given by (19) and (20), respectively. Additionally, the voltage stress on the switch can be determined from (21).

$$I_{S1\left(avg\right)}=I_{S2\left(avg\right)}={\displaystyle \frac{I_{L1}\left(D+n_1+n_2\right)}{2\left(n_1+n_2+mc\right)}},$$

(19)

$$I_{S1\left(rms\right)}=I_{S2\left(rms\right)}={\displaystyle \frac{I_{L1}\sqrt{5-D}}{\left(n_1+n_2+mc\right)}},$$

(20)

$$V_{S1\left(\max \right)}=V_{S2\left(\max \right)}={\displaystyle \frac{V_i}{1-D}}.$$

(21)

The average and rms currents through the VMC’s diodes and output diodes are calculated from (22)–(27). The maximum reverse voltages across the diodes are given by (28)–(30).

$$I_{D1\left(avg\right)}=I_{D2\left(avg\right)}={\displaystyle \frac{I_{L1}\left(1-D\right)}{2\left(n_1+n_2+mc\right)}},$$

(22)

$$I_{Ds1\left(avg\right)}=I_{Ds2\left(avg\right)}={\displaystyle \frac{I_{L1}\left(1-D\right)}{\left(n_1+n_2+mc\right)}},$$

(23)

$$I_{D1\left(rms\right)}=I_{D2\left(rms\right)}={\displaystyle \frac{3I_{L1}\sqrt{2\left(3-4D\right)}}{10\left(n_1+n_2+mc\right)}},$$

(24)

$$I_{Ds1\left(rms\right)}=I_{Ds2\left(rms\right)}={\displaystyle \frac{5I_{L1}\sqrt{2\left(3-4D\right)}}{6\left(n_1+n_2+mc\right)}},$$

(25)

$$I_{Dm1\left(avg\right)}=I_{Dm2\left(avg\right)}={\displaystyle \frac{I_{L1}\left(1-D\right)}{2\left(n_1+n_2+mc\right)}},$$

(26)

$$I_{Dm1\left(rms\right)}=I_{Dm2\left(rms\right)}={\displaystyle \frac{I_{L1}\sqrt{2\left(3-4D\right)}}{3\left(n_1+n_2+mc\right)}},$$

(27)

$$V_{D1\left(\max \right)}=V_{D2\left(\max \right)}=-{\displaystyle \frac{\left(2n_2+mc-2\right)V_i}{1-D}},$$

(28)

$$V_{Ds1\left(\max \right)}=V_{Ds2\left(\max \right)}=-{\displaystyle \frac{n_1{V}_i}{1-D}},$$

(29)

$$V_{Dm1\left(\max \right)}=V_{Dm2\left(\max \right)}=-{\displaystyle \frac{2V_i}{1-D}}.$$

(30)

2.3. Small-Signal Modeling

The small-signal analysis of power electronic converters can be performed utilizing the well-established state-space averaging (SSA) technique proposed in [35]. However, this process becomes quite tedious and complex as the system order increases. Given this, the authors in [36] proposed a simplified, yet accurate solution based on the pulse-width modulation (PWM) switch model for modeling non-isolated high step-up dc-dc boost converters based on VMCs. Applying this methodology to the topology shown in Figure 1 yields (31)–(33), which represent the control-to-output transfer function v_o(s)/d(s), the inductor-current-to-output transfer function v_o(s)/i_L(s), and the control-to-inductor-current transfer function i_L(s)/d(s).

$${\displaystyle \frac{v_o\left(s\right)}{d\left(s\right)}}={\displaystyle \frac{R_o\left[\left(1-D\right)V_o-2I_i{L}_{1}s\right]}{4Ls\left(s{R}_o{C}_{o\left(eq.\right)}+1\right)+{\left(1-D\right)}^2{R}_o}},$$

(31)

$${\displaystyle \frac{v_o\left(s\right)}{i_L\left(s\right)}}={\displaystyle \frac{R_o\left[\left(1-D\right)V_o-2I_i{L}_{1}s\right]}{2V_o\left(s{R}_o{C}_{o\left(eq.\right)}+1\right)+\left(1-D\right)R_o{I}_i}},$$

(32)

$${\displaystyle \frac{i_L\left(s\right)}{d\left(s\right)}}={\displaystyle \frac{2V_o\left(s{R}_o{C}_{o\left(eq.\right)}+1\right)+\left(1-D\right)R_o{I}_i}{4L_{1}s\left(s{R}_o{C}_{o\left(eq.\right)}+1\right)+{\left(1-D\right)}^2{R}_o}},$$

(33)

where C_o(eq.) is the equivalent capacitance corresponding to the series association of C_s1, C_s2, and C_o.

It is possible to validate these equations by performing time-domain simulations and comparing the responses of the converter and the small-signal model. For this purpose, the rated operating conditions adopted in the design of the experimental prototype tested in Section 4 were adopted, corresponding to V_i = 48 V, V_o = 400 V, P_o = 1000 W, f_s = 25 kHz, D = 0.58, L₁ = 50 µF, and C_o(eq.) = 15 µF. Figure 4a shows that the response of the converter aligns well with that of the model representing v_o(s)/d(s), when perturbing the rated duty ratio by +0.01, −0.01, and +0.05 at 100 ms, 200 ms, and 300 ms, respectively. Similarly, it is observed that v_o(s)/i_L(s) represents the converter accurately in Figure 4b. In this test, the rated input voltage is incremented by +0.01 V, −0.01 V, and +0.02 V at 100 ms, 200 ms, and 300 ms, respectively, which perturbs the inductor current as a consequence. Similarly, the inductor current follows i_L(s)/d(s) in Figure 4c when the rated duty cycle is perturbed by −0.001, +0.002, and −0.003 at 100 ms, 200 ms, and 300 ms.

3. Comparison with Other Non-Isolated High Step-Up Interleaved Boost Converters

Table 1. Comparison among non-isolated high step-up dc-dc interleaved boost converters based on coupled inductors.

Parameter	Proposed Converter	[15]	[16]	[17]	[18]	[19]	[20]
Switches	2	2	3	2	2	2	2
Diodes	$2+2mc+2N_S$	4	7	5	5	4	4
Capacitors	$1+2mc+2N_S$	3	7	4	4	4	6
Cores	3	2	3	1	2	1	4
Windings	$6+N_S$	4	5	3	4	3	6
Gain (Vo/Vi)	${\displaystyle \frac{n_1+n_2+mc}{1-D}}$	${\displaystyle \frac{1}{1-D}}+2n$	${\displaystyle \frac{n\left(1+D\right)}{1-D}}$	${\displaystyle \frac{n\left(2-D\right)}{1-D}}$	${\displaystyle \frac{3n+1}{1-D}}$	${\displaystyle \frac{1+n+D}{1-D}}$	${\displaystyle \frac{2n+D+1}{1-D}}$
VS(max.)/Vo	${\displaystyle \frac{1}{n_1+n_2+mc}}$	${\displaystyle \frac{1}{1+2n-2nD}}$	${\displaystyle \frac{1}{2\left(n-1\right)}}$	${\displaystyle \frac{1}{2n\left(2-D\right)}}$	${\displaystyle \frac{1}{3n+1}}$	${\displaystyle \frac{1}{1+n+D}}$	${\displaystyle \frac{1}{2n+D+1}}$
VD(max.)/Vo	${\displaystyle \frac{n_1}{n_1+n_2+mc}}$	${\displaystyle \frac{n}{1+2n-2nD}}$	${\displaystyle \frac{1}{2}}$	${\displaystyle \frac{1}{\left(2-D\right)}}$	${\displaystyle \frac{2n}{3n+1}}$	${\displaystyle \frac{1}{1+n+D}}$	${\displaystyle \frac{n+1}{2n+D+1}}$
Specifications	48 V/400 V	24 V/100 V	40 V/420 V	24 V/200 V	40 V/400 V	40 V/400 V	48 V/800 V
	25 kHz	50 kHz	100 kHz	50 kHz	50 kHz	50 kHz	50 kHz
	1 kW	200 W	210 W	200 W	400 W	500 W	1 kW
	95.12%	95.8%	96.5%	96.2%	97%	94.5%	93%
Common ground	Yes	Yes	Yes	No	Yes	No	Yes
Modularity	Yes	No	No	No	No	No	No
Isolated drive circuitry	No	No	No	Yes	No	Yes	No
Improved current sharing	Yes	No	No	No	No	No	No
Electrolytic capacitors	No	Yes	Yes	Yes	Yes	Yes	No

compares some interleaved topologies based on coupled inductors found in the literature, where n is the turns ratio of the coupled inductors and N_S is the number of secondary windings associated with the boost converter shown in Figure 1. Figure 5 depicts the voltage gain of the converter under analysis, while Figure 6 and Figure 7 represent the normalized voltage stresses on the switches and output diodes, respectively.

Despite combining the boost converter with auxiliary circuits in [15,16] provides voltage gain extension, the voltage stresses on the switches and output diode remain very high. Poor performance is also reported in [17], where the converter exhibits the lowest voltage and high normalized voltage stresses on the semiconductors. Conversely, the highest gain is obtained in [18], but the need for a clamping circuit to mitigate voltage spikes caused by the leakage inductance of the coupled inductor results in a high component count.

The converter proposed [19] requires few components, but the lack of a common ground connection, the need for isolated gate driver circuitry, and its modest voltage gain make it less appealing for practical applications. High voltage gain and low stresses on the switch are also obtained in [20]. However, this structure may suffer from significant voltage and current imbalance caused by the differential connection of two boost converters.

Unlike its counterparts, the proposed converter offers significant advantages, such as moderate voltage gain combined with a reasonable component count, low voltage stresses on switches and diodes, a common ground connection, enhanced current sharing due to magnetic coupling, inherent modularity associated with the possibility of adding more secondaries and VMCs. Notably, it is not intended to compete with other coupled-inductor-based topologies that can achieve ultra-high voltage gains, which in turn require a significantly higher number of components.

4. Experimental Results

Table 2. Specifications of the experimental prototype.

Parameter	Specification
Input voltage	Vi = 48 V
Output voltage	Vo = 400 V
Rated output power	Po = 1000 W
Switching frequency	fs = 25 kHz
Rated duty cycle	D = 0.58
Input filter inductor ripple	ΔIL1 = 15%·IL1
Voltage ripple across C1, C2, and C3	ΔVC = 0.25%·Vo
Voltage ripple across Cm1 and Cm2	ΔVCm = 0.5%·Vo
Output voltage ripple	ΔVo = 0.25%·Vo
Switches S1 and S2	MOSFET IRFP90N20 by Infineon
Diodes D1, D2, Ds1, Ds2, Dm1, and Dm2	Ultrafast diode U860 by ON Semiconductor
Capacitor C1	33 μF/250 V polypropylene capacitor
Capacitors C2 and C3	Two parallel-connected 33 μF/250 V polypropylene capacitors
Capacitors Cm1 and Cm2	Two parallel-connected polypropylene capacitors, rated at 10 μF/250 V and 33 μF/250 V
Filter inductor L1	L1 = 50 µF Core: MMT052T7725 by Magmattec 18 turns, 21 × AWG22
Transformer	Core: NEE-65/33/26 by Thornton N1p1 = N1p2 = 10 turns − 12 × AWG22 N1s1 = 15 turns − 8 × AWG22 (n1 = N1s1/N1p1 = 1.50)
Three-winding coupled inductor	Core: NEE-55/28/21 by Thornton N2p1 = 17 turns − 4 × AWG22 N2s1 = N2s2 = 21 turns − 2 × AWG22 (n2 = N2s1/N2p1 = 1.24)

summarizes the specifications of the experimental prototype of the non-isolated high step-up interleaved boost converter, shown in Figure 8. It is worth mentioning that the rated operating conditions were defined similarly to those in [37]. Additionally, all experimental waveforms were measured using a four-channel digital oscilloscope, model TPS2024 by Tektronix.

Table 3. Comparison between calculated and experimentally measured values.

Parameter	Calculated	Measured
Average inductor current (IL1)	20.83 A	20.90 A
Inductor current ripple (ΔIL1)	3.13 A	3.11 A
Average output voltage (Vo)	400.00 V	400 V
Maximum voltage across the switches (VS1(max), VS2(max))	114.49 V	112 V
Maximum reverse voltage across the output diodes (VD1(max), VD2(max))	−133.84 V	−148 V
Maximum reverse voltage across the multiplier diodes (VDm1(max), VDm2(max))	−228.93 V	−224 V
Maximum reverse voltage across the secondary diodes (VDs1(max), VDs2(max))	−161.50 V	−164 V
Maximum voltage across the multiplier capacitors (VCm1(max), VCm2(max))	114.49 V	112 V
Maximum voltage across the output filter capacitor (VCo(max))	238.68 V	246 V
Maximum voltage across the secondary capacitors (VCs1(max), VCs2(max))	80.96 V	84 V
Maximum voltage on the primary windings of the transformer (VN1p1(max), VN1p2(max))	57.24 V	56 V
Maximum voltage on the secondary winding of the transformer (VN1p1(max))	80.96 V	80 V
Maximum voltage on the primary winding of the coupled inductor (VN2p1(max))	114.49 V	112 V
Maximum voltage on the secondary windings of the coupled inductor (VN221(max), VN2s2(max))	124.18 V	130 V

presents a comparison between calculated and experimentally measured parameters, showing good alignment and confirming the consistency of the theoretical analysis. Eventual differences are due to parasitics and layout issues associated with the prototype.

Figure 9 shows the output current and the output voltage, with the converter operating at the rated power condition. Figure 10 depicts the gate-to-source voltage and the input current. The current ripple is observed to remain within the desired specifications, with the input filter inductor operating at twice the switching frequency. Figure 11 shows the drain-to-source voltages, which are phase-shifted by 180°. Furthermore, the maximum voltage across the switches remains lower than one-third of the output voltage, while no significant voltage spikes exist. This behavior is attributed to the components of the VMC, which effectively ensures proper voltage clamping.

Figure 12 illustrates the voltages across one of the primary windings and the secondary winding of the transformer. Due to the identical impedance of the primary windings, the voltage across these windings is equal, and the converter achieves effective current sharing without requiring dedicated and complex control strategies. On the other hand, due to the turns ratio between the primary and secondary windings, the secondary voltage is higher, thus allowing for increasing the voltage gain.

Figure 13 shows the voltages across the output diodes D₁ and D₂, whose maximum value is lower than the output voltage. Similarly, the voltages across diodes D_s1 and D_s2 in Figure 14 are also phase-shifted by 180°, as expected.

Figure 15 displays the voltages across the multiplier diodes D_m1 and D_m2. Such diodes are subjected to higher reverse voltages than their remaining counterparts due to the presence of adjacent capacitors in the VMCs. Nevertheless, the voltage stress is only slightly higher than half the output voltage.

Figure 16 shows the efficiency as a function of the output power, reaching a maximum of 96.31% around 800 W, with 95.12% around the rated power.

The total losses across all components, amounting to 47.9 W, were calculated based on experimentally measured current and voltage ratings. These calculations accounted for the characteristics of all semiconductors specified by commercial manufacturers and the properties of magnetic components determined during physical construction. The procedure adhered to expressions commonly found in power electronics textbooks, following the guidelines outlined in [37]. Notably, the loss breakdown shown in Figure 17 shows that the diodes and switches account for the major portions of losses, corresponding to 14.35 W and 13.47 W, respectively. Key improvements in overall efficiency could be achieved by employing devices with a lower drain-to-source on-resistance and forward voltage drop, for instance.

5. Conclusions

This work has presented a non-isolated high step-up dc-dc interleaved boost converter based on coupled inductors and VMCs, aimed at high-power, high-current applications. Prominent advantages of the topology include three possibilities to extend the voltage gain besides the duty ratio: the turns ratio of the transformer with multiple secondary windings, the turns ratio of the three-winding coupled inductor, and VMCs. The VMCs minimize the voltage stresses on semiconductors, keeping them below the output voltage and enabling the use of transistors with low drain-to-source on-resistance, reducing conduction losses. The design also eliminates the need for electrolytic capacitors, which typically exhibit higher equivalent series resistance (ESR) than film capacitors. Additionally, the primary windings of the transformer are designed to have identical impedance, ensuring better current sharing compared to conventional interleaved converters.

Although the proposed converter does not achieve the highest voltage gain compared to other similar topologies reported in the literature, it offers multiple solutions for increasing output voltage other than the duty cycle, enabling diverse design trade-offs. For example, adding more VMCs to the circuit can reduce voltage stresses without significantly affecting power density, as an alternative to increasing the turns ratio of magnetic elements. Overall, it can provide moderate voltage gains while achieving high efficiency across a wide load range, with the rated power reaching kilowatt levels.