Sensorless Dual TSEP (V_th, R_dson) Implementation for Junction Temperature Measurement in Parallelized SiC MOSFETs ^†

Abstract

This article presents a method for detecting the temperature distribution of two parallelized Silicon Carbide (SiC) MOSFETs. Two thermally sensitive electrical parameters (TSEPs), namely the on-state resistance ($R_{dson}$) and the threshold voltage ($V_{th}$), are introduced. A comparison of the temperatures interpolated by $V_{th}$ and $R_{dson}$ shows disparity, enabling the detection of individual junction temperatures. $V_{th}$ instability and its measurement are discussed for SiC devices. Experimental results show that, depending on the instability of the $V_{th}$ and the sensitivity of the two TSEPs at certain temperatures, a combination of different TSEPs could be a solution for extracting the maximum junction temperature of parallelized devices.

1. Introduction

In power electronics applications, such as automotive [1] or rail traction [2], SiC MOSFETs can replace Si IGBTs or MOSFETs due to their intrinsic characteristics, such as higher temperature robustness, higher-frequency switching, and higher-voltage operation [3,4], leading to lower switching and conduction losses. Figure 1 illustrates the reduction in losses for a 1200 V/100 A power module in which Si IGBTs were replaced with SiC MOSFETs, resulting in a 73% reduction in losses at 20 kHz.

At the same time, power modules are evolving to adapt to SiC MOSFETs and to improve efficiency. Internal package electromagnetic parasitics at high frequencies are becoming the main bottleneck to higher-frequency operation [5], and the smaller surface of SiC MOSFETs, compared to Si IGBTs [6,7], makes it necessary to reduce the thermal resistance of the modules [8]. Innovations have been introduced in new layouts and packaging, such as the double-sided cooling module [9], which reduces parasitic inductance by 40% and achieves thermal resistances of up to 0.08 °C/W [10].

Such modules offer dual advantages. First, as shown in Figure 2, no wire bonding is needed to achieve electrical connections, which reduces stray inductance. Second, dies can be cooled down with two heat-flow paths. Nonetheless, these innovations come with a drawback: because dies are grounded between two substrates, it is impossible to access their surfaces directly. Hence, it is impossible to obtain direct measurements of surface temperatures using thermocouples, IR cameras, or optical fibers.

Even if difficult in double-sided modules, obtaining temperatures of MOSFETs during pretests is a must for manufacturers, as shown in Figure 3, for the same average component temperature (80 °C), going from a variation of 40 °C to 50 °C during a cycle leads to a division of the component’s lifetime by 4. Similarly, going from an average temperature of 80 °C to 100 °C, for the same thermal variation of 40 °C, leads to a division of the lifetime by 5. Hence, to determine lifespan, precise acquisition of the junction temperature is needed. If no direct access to the die is possible, only thermally sensitive electrical parameters (TSEPs) or built-in sensors [12] are then suitable.

A major drawback of SiC MOSFETs is the difficulty in manufacturing wafers with limited imperfections, which leads to the need to manufacture smaller dies compared to Si ones to achieve the same die-per-wafer yield [3]. Hence, parallelizing (same gate, drain, and source connections) dies is mandatory for high-current applications. This comes with other problems, such as the risk of current and thermal imbalance between MOSFETs, which can both lead to dysfunction. If one of the MOSFETs is subjected to greater thermal cycling than the others, its reduced lifetime shortens the lifetime of the system as a whole.

Actually, despite its importance, no method allows for detecting thermal imbalance in double-sided modules using totally parallelized dies by TSEPs [13]. Only an apparent temperature is extracted from TSEPs, which does not enable the determination of potential thermal imbalances and overheating dies.

A method has been developed to determine the maximal junction temperature of multi-chip SiC MOSFET single-sided cooling power modules [14], using deep learning and a TSEP, but the process is based on optical-fiber measurement of the surface temperature of dies and cannot be applied to double-sided modules. Studies have characterized the apparent temperature estimated via TSEPs for parallelized dies, showing that certain TSEPs ($V_{ce}$,$V_f$) only allow the estimation of the average temperature of the parallelized dies for low $\Delta T$, while others (turn-off transient or $V_0$) allow the estimation of a temperature between the average temperature of the dies and the maximum one [15,16]. Nevertheless, these articles address Si IGBTs, or Si and SiC diodes, and their validity with regard to SiC MOSFETs is not clear.

Thus, the main objective of this article is to develop an electrical measurement method that determines temperature imbalances between fully parallelized SiC MOSFETs, even when the MOSFETs are not accessible. To this end, TSEPs will be investigated in order to determine what temperature is estimated (average, maximum, minimum, or other). The intended application of this method is the determination of the maximum junction temperature ($T_j$) of SiC MOSFETs when no direct measurement of $T_j$ is possible, in order to ensure the reliability of double-sided power modules.

A drawback of using SiC MOSFETs is their $V_{th}$ shift, which is the subject of discussion among both industry professionals and researchers (see Figure 4). $V_{th}$ is a key parameter because its instability plays a role in current imbalance during operation and because it is an interesting TSEP. To mitigate the impact of $V_{th}$ shift after stresses, conditioning methods have been developed [17], such as the JEDEC guidelines [18], which describe circuits allowing precise measurement of $V_{th}$. Conditioning is usually achieved by applying a positive or negative voltage at the gate of the MOSFET while short-circuiting its drain and source to remove carrier trapping. Measurement is then performed by short-circuiting the gate and drain and forcing a small current (see Figure 5) through the device. The resulting voltage is $V_{th}$. In this work, the current used to measure $V_{th}$ as a TSEP will be optimized.

The SiC MOSFETs studied during the tests and simulations are the SCT070W120G3-4AG from STMicroelectronics.

2. Methodology

In the first part, simulations are carried out to explore the behavior of the TSEPs when a temperature imbalance occurs between the two MOSFETs. Once the two TSEPs have been described, a test bench is set up to reproduce the simulation conditions on real components. A study of the optimization of the I$V_{th}$ current is proposed. Simulations and tests are compared. Finally, a measurement method for detecting temperature imbalances in MOSFETs is presented.

2.1. Simulations

Two well-known TSEPs, the $R_{dson}$ [19,20,21] and $V_{th}$ [22,23], are studied to determine which temperature they provide when there is a temperature imbalance. The simulations are conducted using LTSpice software XVII, and the manufacturer’s models are used for the MOSFETs. In each study, the procedure is as follows: an electrical circuit is set up, allowing the measurement of a specific TSEP. Figure 6 shows the setups for the $R_{dson}$ and $V_{th}$ measurements. In each case, the junction temperature of the two MOSFETs, which is the same, is the variable in the simulation. Hence, by simulating the measurement of the $V_{th}$ and $R_{dson}$ when the junction temperature varies, it is possible to obtain a relationship between those parameters, as presented in Figure 7.

Once these two equations are determined, the simulations are repeated, this time incorporating the temperature imbalances between the two MOSFETs (see Figure 8). The mean temperature of the two MOSFETs is kept constant at 100 °C, with a step of $\Delta T_j$ of 5 °C until it reaches 30 °C.

At each point of thermal imbalance, the $V_{th}$ and $R_{dson}$ are simulated. Through the simulations and equations, it is possible to interpolate temperatures via the $R_{dson}$ and $V_{th}$, named $T_{R_{dson}}$ and $T_{V_{th}}$. Figure 9a shows the interpolated temperatures via the two TSEPs for different temperature imbalances between the two MOSFETs. It appears that $T_{R_{dson}}$ is always very near the average temperature of the two MOSFETs, whereas $T_{V_{th}}$ seems to be a hybrid of the maximum temperature and the mean temperature (but still closer to the mean one). Then, the difference between the temperatures extrapolated by the $V_{th}$ and $R_{dson}$ (named $\Delta T_{TSEP}$) is plotted as a function of the thermal imbalance of the two MOSFETs, as shown in Figure 9b. It appears that they are linked by a quadratic law.

With these simulations, it appears that it could be possible to determine the individual temperatures of two MOSFETs that are totally parallelized, when no individual information is obtainable, solely via the measurement of the two TSEPs: the $R_{dson}$ would allow the determination of the mean temperature of the devices, and the difference between $T_{R_{dson}}$ and $T_{Vth}$ would determine the imbalance.

2.2. Test Bench

The objective of the bench is to perform quick measurements of the $R_{dson}$ and $V_{th}$, with conditioning before the $V_{th}$ measurement, to detect thermal imbalance. The time between the $V_{th}$ measurement and the $R_{dson}$ one must be as short as possible to ensure that the same temperature is measured. The test bench (visible in Figure 10) is separated into two parts: fluidic and electric. The tests were conducted on the DepTH-LAB platform [24] at Icam Toulouse.

2.2.1. Fluidic Part

The fluidic part can be seen in Figure 11a. The exposed pad of the MOSFET is in contact with heat sinks via TIMs. Fluids flow through the heat sinks to extract thermal power dissipation and impose the casing temperatures. The thermal resistance of the foils and heat sinks is estimated at 1.5 °C/W. As each heat sink is connected to a different cryostat, each casing temperature can be monitored separately. Flow rates and inlet and outlet temperatures are controlled. In addition, two thermocouples (T-types) are placed under each MOSFET to measure the temperature as close as possible to the Tcase. The two cryostats used are the RP205E from LAUDA (Lauda-Königshofen, Germany) (with P20.275.50 oil) and the Unistat 510 from HUBER (Edison, NJ, USA) (with M20.195/235.20 oil). The oils used allow the liquid temperature (and thus the casing temperature of the MOSFETs) to reach a maximum of 200 °C for high-temperature tests.

2.2.2. Electrical Part

As seen in Figure 11b, the electric part of the bench can be separated into three subparts: current sources and switches (green), 4-state drivers (red), and configuration changes + measurements (conditioning and $R_{dson}$ to $V_{th}$ configuration) (blue).

Each test can be split into the following steps, as shown in Figure 12.

During the $R_{dson}$ step, a voltage Vgsmax is applied to the gate (15 V). A constant current Id is injected into the drain (typically 10 A per MOSFET). The voltage is measured across the drain and the Kelvin source to obtain Vdsk, and the $R_{dson}$ is calculated from the voltage and current. Switch S1 is then opened to cut the current Ip.

During the conditioning step, successive voltages are applied to the gate in order to precondition the MOSFETs and to ensure that the $V_{th}$ measurements are repeatable. In this study, a voltage of 15 V is applied for 1 s during this phase.

During the $V_{th}$ step, the gate and drain are short-circuited by closing S3. A small current $I_{V_{th}}$ is injected into the drain–gate by closing S2. The current flows through the gate first until the charging of the capacitor Cgs closes the channel. When it does, the current flows through the drain, and the voltage stabilizes. Vds can then be measured to obtain the $V_{th}$.

Commands for all switches are managed by an Arduino Uno microcontroller (ARDUINO, Monza, Italy) with direct manipulation of the ports to achieve a minimum instruction execution time (time between two switch operations) of 50 ns.

Measurement is performed with an oscilloscope MSO58N of TEKTRONIX (Beaverto, OR, USA). The voltage probe for Vds is a TEKTRONIX TPP0500B, and the power current is measured with a TEKTRONIX TCP0030A current probe. The current $I_{V_{th}}$ is generated by an SMU (Keithley 2612), and the current Ip is generated by an EA-PS 2042-20B.

3. Results

3.1. Choice of $I_{V_{th}}$

First, all ten SiC MOSFETs had their $V_{th}$ and $R_{dson}$ measured individually (see Figure 13). It was arbitrarily decided to use 10 mA for the $V_{th}$ current in order to compare the $V_{th}$ between MOSFETs. Since MOSFETs 9 and 10 were the ones with the best matching $V_{th}$ (3.524 V and 3.526 V), they were the two MOSFETs chosen to be parallelized.

An important parameter in this setup is the choice of the current used to measure the threshold voltage. As it is defined as the minimum voltage to apply to the gate and drain to achieve a certain current in the drain, its value can change depending on the current selected. The JEDEC guidelines do not indicate the values to use; hence, every MOSFET manufacturer uses a different value: 1 mA for STMicroelectronics, 6.4 for Rohm, and 3.3 for INFINEON. As no information on why this current is used was given, neither by the manufacturers nor by JEDEC, a study of the optimal $I_{V_{th}}$ was proposed. A much wider range of currents was covered than is usual in industry, from 1 µA to 1 ampere, to obtain a proper idea of the ideal value. Each measurement was subjected to a conditioning voltage of 15 V for one second. Each time, the Vth of the two parallelized MOSFETs was measured at the same temperature. As the method used to obtain the $V_{th}$ relied on the loading of the capacitance Cgs under a constant current to obtain the channel of the MOSFET closed, there was a loading time before the $V_{th}$ was obtained (see Figure 14a). It appears that the higher the current, the faster the measurement (see Figure 14b). The $V_{th}$ was considered obtained when the Vgs reached its maximum value.

Having the shortest possible capacitance charging time is extremely important in tests. As the $V_{th}$ is measured without power injection, the measurement must be taken immediately after an injection. If the loading time is too long, the cooling of the chip during that time will not be negligible, making the measurement and its comparison with the $R_{dson}$ irrelevant.

Nonetheless, the charging time of the Vth is not the only parameter to consider. The curves shown in Figure 15a were obtained for three junction temperatures: 105, 130, and 155 °C. Considering that the $V_{th}$ is linear with temperature, the sensitivity was extracted from each curve shown in Figure 15a and then plotted, as shown in Figure 15b. It seems that the $V_{th}$ was more sensitive to temperature variations when the current was higher than 1 mA. Below this value, the sensitivity stayed constant at around −4.75 mV/°C.

Another important parameter that must be considered when choosing the $I_{V_{th}}$ is the temperature measured when an imbalance is present. As shown in Figure 16, the current should be as low as possible to obtain good sensitivity to the temperature imbalance between the two MOSFETs.

This last parameter (sensitivity to thermal imbalance) is in direct opposition to the first two (sensitivity to temperature and time to charge Cgs). Hence, a compromise must be found between the measurement accuracy of the temperature imbalance and the measurement speed. For this study, the current selected was 10 mA per MOSFET. With two MOSFETs parallelized, the gate charge time should be only 32 µs, with a sensitivity of 5.5 mV/°C.

3.2. Imbalance Measurement

The first objective was to demonstrate the feasibility of temperature imbalance detection. It was decided to perform long gate saturation to suppress traps and $V_{th}$ instability before each measurement (1 s).

Figure 17 illustrates the scenario used to measure the $R_{dson}$ and $V_{th}$ successively after a one-second conditioning (+15 V on the gate, 0 V Vds). In these tests, the $T_j$ of each MOSFET was considered equal to the temperature of its casing, as there was no noticeable self-heating during the scenario.

The two MOSFETs were each heated to 100 °C. A test was performed, and then the temperature of one MOSFET was increased to create a thermal imbalance. Measurements were performed, and then the thermal imbalance was increased again. These tests are shown in Figure 18 for the SCT070W120G3-4AG. It can be clearly seen that there is a correlation between the temperature imbalance between the two MOSFETs and the square root of the temperature difference interpolated with the $R_{dson}$ and $V_{th}$. The simulations and tests show exactly the same sensitivity.

With this correlation, new tests were performed (Figure 19). This time, T1, T2, $V_{th}$, and $R_{dson}$ were measured. The $V_{th}$ and $R_{dson}$ permitted a $T_{R_{dson}}$ and $T_{V_{th}}$ estimation, and the difference between these two values, using the equation given in Figure 18, made it possible to get an idea of the temperature imbalance between the two MOSFETs. As the temperature interpolated by the $R_{dson}$ was near the average temperature of the two MOSFETs, it was then possible to evaluate the individual temperatures of the two MOSFETs, even if totally parallelized.

4. Discussion

The choice of the $V_{th}$ measurement current, when the drain–gate short-circuit and current-injection method is used, deserves particular attention. In a conventional application, when a single MOSFET is studied, or when imbalance is not an issue, the choice of the $V_{th}$ should be based on high current values. However, care must be taken to ensure that the power dissipation of the measurement remains negligible or is taken into account. If maximum $T_j$ detection is desired, a compromise will have to be found. A value of 10 mA seems to be ideal, as it allows tests to be carried out in a short time while measuring a hybrid temperature between the $T_{max}$ and $T_{mean}$.

Simulations and tests show very good similarities. As shown in Figure 18, even if tests are noisy, the two interpolated curves only have a 1.6% difference. This shows that the STMicroelectronics simulation models can be used to determine the thermo-sensitivity and TSEP behavior of several parallelized chips, at least for the $R_{dson}$ and $V_{th}$ simulations.

The SiC results presented are the first of an ongoing test campaign and should be regarded as a work in progress. So far, only offline measurements have been conducted, without accounting for self-heating. The need for optimized conditioning before measurement has not been studied.

Nonetheless, these first results are promising. As shown in Figure 19, it is possible to detect temperature imbalances in simple cases. It should be noted that even if the imbalance is underestimated, it is much more precise than a single measurement of the $R_{dson}$ or $V_{th}$. New tests must be carried out at different casing temperatures to determine whether the results are reproducible. More importantly, tests with elevated junction temperatures due to self-heating will be performed, as this is the goal of any TSEP.

Assuming that the lifetime of the chips is halved when the junction temperature increases by ten degrees, it can be seen that the new method makes it possible to estimate the lifetime of the chips with far fewer errors. Taking the extreme case, where one MOSFET is at 121 °C and the other at 148 °C, where the actual maximum junction temperature is 148 °C (lifetime normalized at 1), a conventional measurement using a simple TSEP would, at best, have estimated the virtual junction temperature at 138 °C (i.e., a lifetime of 2). Thanks to the method developed, the maximum temperature reached by the MOSFETs was estimated at 145.5 °C (lifetime of 1.2). It appears that the lifetime of the module can then be much more accurately estimated.

Moreover, it should be noted that as the $V_{th}$ is unstable, even with proper conditioning, only important imbalances of temperature can be estimated, as smaller ones could be caused by natural fluctuations of the $V_{th}$. Finally, this entire study was carried out using matched MOSFETs, which have roughly the same $V_{th}$ at the same temperature. It is likely that MOSFETs with different electrical characteristics would not allow this method to be used. However, the trend in power electronics modules is to couple MOSFETs with equivalent electrical characteristics, which makes it likely that this approach will be valid for new modules. On older modules, the shift in the $V_{th}$ over time could raise questions about the feasibility of this method. However, this method has been designed to qualify the lifetime of new modules by extracting their maximum $T_j$. Hence, this method should be of interest in this particular niche.

As a preliminary analysis, it is reasonable to assume that temperature imbalances in excess of at least 15 °C will be observable using this method.

5. Conclusions

By comparing the $R_{dson}$ and $V_{th}$ thermal responses of two completely parallelized SiC MOSFETs, this article developed a new non-intrusive method to detect thermal imbalances in power modules where no direct access to dies is available. This method exploits the fact that the interpolated virtual junction temperature via the $R_{dson}$ is close to the average temperature of the two components, regardless of the temperature imbalance between them, and the fact that, conversely, the temperature obtained by interpolating the $V_{th}$, when MOSFETs are preconditioned, is a hybrid temperature between the average and maximum temperatures of the two components. An empirical relationship was then established between the temperature difference interpolated by the $R_{dson}$ and $V_{th}$ and the temperature difference between the MOSFETs.

Initially, simulations were carried out to determine what temperature each TSEP could interpolate.

A test bench was presented, which enabled the $R_{dson}$ and $V_{th}$ of the parallelized MOSFETs to be measured in rapid succession, as well as allowing different reference temperatures, and therefore different junction temperatures, to be imposed on the components.

The initial tests made it possible to determine an optimal current to ensure that the $V_{th}$ is sensitive both to global temperature variations and to temperature variations between MOSFETs. To ensure that the gate loading time of the MOSFETs studied was not too long, a compromise was found, enabling the optimal current to be set at 10 mA per parallelized die.

Subsequently, when tests were carried out, it was shown that the expected behavior obtained through simulation corresponded well to that obtained through tests, showing that the manufacturer’s LTSpice models, in the context of the study of the $V_{th}$ and $R_{dson}$ and their sensitivity to temperature, are sufficiently accurate. The sensitivity of the $\Delta T_{TSEP}$ is quite small, and even a 1 °C error in the measurement of the temperature of the $R_{dson}$ or $V_{th}$ could lead to significant errors in the estimation of the thermal imbalance. Nevertheless, the first tests carried out show a clear improvement in the maximum junction temperature estimated using the developed method.

Further tests will be carried out to confirm these results. First, these tests will be performed using chips from other manufacturers in order to validate the generalization of this measurement method. In addition, other TSEPs will be tested to determine whether the $V_{th}$, which suffers from instability over time, can be replaced. A study on optimizing the voltage and preconditioning time will be carried out to further increase sensitivity to temperature imbalances between MOSFETs. A second version of this bench is currently in production, which will enable new TSEPs to be tested and up to three MOSFETs to be parallelized.