A Switched-Capacitor-Based Quasi-H7 Inverter for Common-Mode Voltage Reduction

Abstract

This paper proposes a novel three-phase two-level DC-AC inverter with significantly reduced common-mode voltage. The proposed inverter combines a conventional three-phase H7 configuration with a voltage multiplier network, effectively doubling the DC-link voltage relative to the input. Compared to existing solutions, the topology achieves a remarkably low common-mode voltage, limited to only 16.6% of the DC-link voltage. Additionally, the voltage stress across the additional switches remains at half of the DC-link voltage. The paper details the operating principles, mathematical formulation, and circuit-level analysis of the proposed inverter. Simulation results are provided to validate its performance. Furthermore, a hardware prototype has been implemented using a DSP TMS320F28379D microcontroller manufactured by Texas Instruments, headquartered in Dallas, TX, USA in conjunction with an Altera Cyclone® IV EP4CE22F17C6N FPGA-based digital control platform manufactured by Intel Corporation, headquarters in Santa Clara, CA, USA. Experimental results are presented to confirm the effectiveness and feasibility of the proposed design.

1. Introduction

Common-mode voltage (CMV) plays a crucial role in various applications, particularly in transformerless photovoltaic (PV) and electric motor drives [1,2,3,4,5]. In conventional pulse-width modulation (PWM) inverters, CMV with high frequency and amplitude is known to cause several undesirable effects, including electromagnetic interference (EMI), ground leakage currents, and bearing current generation [6,7]. In a typical three-phase system, the CMV is calculated as the average of the voltages between nodes A-O, B-O, and C-O and is expressed as:

$$V_{CM}={\displaystyle \frac{(V_{AO}+V_{BO}+V_{CO})}{3}}.$$

(1)

where the point “O” represents the negative terminal of the input DC source, and V_AO, V_BO, and V_CO denote the phase voltages measured with respect to this point, as illustrated in Figure 1.

To address the CMV issues associated with conventional PWM inverters, a lot of reduction techniques have been proposed in previous studies. These approaches include modifications to inverter topologies as well as the development of advanced PWM control strategies.

Improved modulation control strategies, such as Active Zero State PWM (AZSPWM), Near State PWM (NSPWM), and Reduced Switching PWM (RSPWM), have been proposed to mitigate CMV variation by avoiding the use of zero-voltage states [8,9]. These techniques reduce the magnitude of the CMV to approximately 33.3% of the input DC voltage. However, this improvement comes at the cost of degraded power quality, a reduced modulation index, and lower efficiency, ultimately affecting overall inverter performance. To further reduce the CMV, hybrid space vector PWM (SVPWM) methods have been explored in [10]. The voltage linearity characteristics of these strategies are similar to those of the AZSPWM method. In addition, the CMV frequency was only equal to three times the fundamental frequency. Nevertheless, hybrid SVPWM techniques present challenges such as increased algorithmic complexity and higher switching losses. A novel model predictive control method is proposed in [11] to suppress common-mode voltage by strategically limiting the number of usable voltage vectors within each sector. As a result, the CMV magnitude is effectively constrained to 33.3% of the input DC voltage. In parallel, [12] introduces a low-common-mode SVPWM technique that divides the voltage plane into 12 sectors, achieving the same CMV magnitude while tripling the CMV switching frequency.

In addition to modulation strategies, various inverter topologies have been proposed to reduce the CMV. As discussed in [13,14,15], three-phase four-leg inverter structures are commonly employed for CMV suppression. In [13], a near state vector selection-based model for predictive control is introduced to limit the common-mode voltage by using a minimum number of usable vectors in every switching period. This method reduces the magnitude of the CMV to approximately 25% of the input DC voltage. In [14,15], the fourth leg of a three-phase four-leg inverter is actively controlled to compensate for CMV variation, effectively achieving zero common-mode voltage. A three-phase H7 inverter was introduced in [16], in which an additional switch is inserted between the input DC source and the conventional H-bridge inverter. A schematic of the conventional three-phase H7 inverter is shown in Figure 1. By controlling this additional switch to float the inverter from the DC source during zero states, the CMV varies between V_dc/3 and V_dc, as summarized in

Table 1. CMV value of conventional H7 inverter under different switching states.

Switching State	Bridge States (S1S3S5)	State of S7	VCMV
State 1	100	1	Vdc/3
State 2	110	1	2Vdc/3
State 3	010	1	Vdc/3
State 4	011	1	2Vdc/3
State 5	001	1	Vdc/3
State 6	101	1	2Vdc/3
State 7	111	0	Vdc

. A voltage-clamping H8 topology, discussed in [17], employs two additional active switches to disconnect the power source from the inverter during freewheeling states. This configuration maintains a constant CMV during mode transitions, with the CMV magnitude limited to only 33.3% of the input DC voltage. Alternative H8 topologies were also presented in [18,19], utilizing only two extra switches to constrain CMV variation. In these designs, the CMV fluctuation is similarly restricted to 33.3% of the input DC voltage.

In this paper, a novel switched-capacitor-based quasi-H7 inverter (SC-qH7 inverter) is proposed. The presented topology combines a conventional three-phase H7 inverter with a voltage multiplier network. Unlike existing solutions, the CMV of the proposed inverter varies only from V_PN/6 to V_PN/3, whereas the CMV in the conventional H7 inverter topology fluctuates from V_PN/3 to V_PN. Furthermore, the SC-qH7 inverter supports the full modulation index range without compromising on performance. A switched-capacitor network is proposed to achieve low common-mode voltage and voltage boosting in the proposed SC-qH7 inverter. Similar to conventional switched-capacitor circuits, the proposed SC-qH7 inverter also introduces an impulse charging current in capacitors. This issue of current waveforms can be efficiently mitigated by adding resonant inductors in the switched capacitor loop as presented in [20,21]. The proposed inverter structure is introduced in Section 2, followed by a description of the applied PWM control technique in Section 3. Simulation and experimental validation results are provided in Section 4.

2. Topology and Operating Principle of the SC-qH7 Inverter

Figure 2 illustrates the circuit configuration of the proposed SC-qH7 inverter. In this topology, a switched-capacitor network is added to the conventional H7 inverter.

From Figure 2, the voltage across diode D_b (V_NO) is calculated as follows:

$$V_{NO}=\left\{\begin{array}{cc}-V_{Cb}& S_b \mathrm{is} \mathrm{on}\\ 0& S_b \mathrm{is} \mathrm{off}\end{array}\right.$$

(2)

The CMV (V_CM) of the proposed SC-qH7 inverter can be rewritten as follows:

$$V_{CM}=V_{NO}+{\displaystyle \frac{(V_{AN}+V_{BN}+V_{CN})}{3}}$$

(3)

2.1. Operating Principle of Proposed SC-qH7 Inverter

The operating principles of the proposed SC-qH7 inverter can be explained through its distinct switching modes, as summarized in

Table 2. CMV value and switching modes of proposed SC-qH7 inverter.

Switching Mode	Switches						Diodes		Output Leg Voltage			VCM
	S1	S3	S5	Sa	Sb	S0	Da	Db	VAN	VBN	VCN
Mode 1	On	Off	Off	On	Off	On	Off	On	VPN	0	0	VPN/3
Mode 2	On	On	Off	Off	On	On	On	Off	VPN	VPN	0	VPN/6
Mode 3	Off	On	Off	On	Off	On	Off	On	0	VPN	0	VPN/3
Mode 4	Off	On	On	Off	On	On	On	Off	0	VPN	VPN	VPN/6
Mode 5	Off	Off	On	On	Off	On	Off	On	0	0	VPN	VPN/3
Mode 6	On	Off	On	Off	On	On	On	Off	VPN	0	VPN	VPN/6
Mode 7	On	On	On	Off	On	Off	Off	On	0	0	0	VPN/4

V_PN is the DC-link voltage across the H-bridge circuit.

. Similar to the conventional H7 inverter [15], the proposed SC-qH7 inverter has seven switching modes, as shown in Figure 3.

Mode 1 (see Figure 3a): five switches S_a, S₀, S₁, S₄, and S₆ are turned on, while four switches S_b, S₂, S₃, and S₅ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N of the proposed SC-qH7 inverter are V_PN, 0 V, and 0 V, respectively. During this mode, diode D_a is blocked, whereas diode D_b is forward-based. Consequently, capacitor C_a discharges, and capacitor C_b charges through the loop V_dc-S_a-C_b-D_b. The corresponding CMV during this mode is V_PN/3.

Mode 2 (see Figure 3b): five switches S_b, S₀, S₁, S₃, and S₆ are turned on, while four switches S_a, S₂, S₄, and S₅ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N are V_PN, V_PN, and 0 V, respectively. During this mode, diode D_b is blocked, and diode D_a is forward-based. Capacitor C_b discharges, while capacitor C_a charges through the loop V_dc-D_a-C_a-S_b. The corresponding CMV during this mode is V_PN/6.

Mode 3 (see Figure 3c): five switches S_a, S₀, S₂, S₃, and S₆ are turned on, while four switches S_b, S₁, S₄, and S₅ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N are 0 V, V_PN, and 0 V, respectively. During mode 3, diode D_a is blocked, while diode D_b is forward-based. Capacitor C_a discharges, and capacitor C_b charges through the loop V_dc-S_a-C_b-D_b. The corresponding CMV during this mode is V_PN/3.

Mode 4 (see Figure 3d): switches S_b, S₀, S₂, S₃, and S₅ are turned on, while four switches S_a, S₁, S₄, and S₆ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N are 0 V, V_PN, and V_PN, respectively. During mode 4, diode D_b is blocked, while diode D_a is forward-based. Capacitor C_b discharges, and capacitor C_a charges through the loop V_dc-D_a -C_a -S_b. The corresponding CMV during this mode is V_PN/6.

Mode 5 (see Figure 3e): switches S_a, S₀, S₂, S₄, and S₅ are turned on, while four switches S_b, S₁, S₃, and S₆ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N are 0 V, 0 V, and V_PN, respectively. During this mode, diode D_a is blocked, while diode D_b is forward-based. Capacitor C_a discharges, and capacitor C_b charges through the loop V_dc-S_a-C_b-D_b. The corresponding CMV during this mode is V_PN/3.

Mode 6 (see Figure 3f): switches S_b, S₀, S₁, S₄, and S₅ are turned on, while four switches S_a, S₂, S₃, and S₆ are turned off. As a result, the voltages between the nodes A-N, B-N, and C-N are V_PN, 0 V, and V_PN, respectively. During mode 6, diode D_b is blocked, while diode D_a is forward-based. Capacitor C_b discharges, and capacitor C_a charges through the loop V_dc-D_a-C_a-S_b. The corresponding CMV during this mode is V_PN/6.

Mode 7 (see Figure 3g): four switches S_b, S₁, S₃, and S₅ are turned on, while five switches S_a, S₀, S₂, S₄, and S₆ are turned off. During this mode, diode D_b is blocked, while diode D_a is forward-based. Capacitor C_b discharges, and capacitor C_a charges through the loop V_dc-D_a-C_a-S_b.

As shown in Figure 2, the DC-link voltage of the proposed SC-qH7 inverter is:

$$V_{PN}=V_{Ca}+V_{Cb}=2V_{dc}.$$

(4)

For the same input DC voltage, the proposed SC-qH7 inverter achieves a DC-link voltage that is twice that of the conventional H7 inverter. Based on the operating principles described earlier, it is observed that the CMV of the SC-qH7 inverter varies from V_PN/6 to V_PN/3 (approximately 16.6% of V_PN) during powering modes (modes 1 through 6). Notably, during these modes, switch S₀ remains in the ON state, contributing to stable power delivery. When the inverter transitions to mode 7, switch S₀ is turned OFF. Unlike the conventional H7 topology, the proposed topology incorporates seven additional capacitors positioned alongside switches S₀ through S₆, as shown in Figure 2. These capacitors, together with the inherent junction capacitances of the switches, form a coupling path between the input DC source and the inverter’s AC output side. Consequently, under the zero-state condition, the CMV is primarily determined by the combined effect of these capacitive elements.

2.2. Capacitor Model During Freewheeling Mode

The transition process from the powering mode to the freewheeling mode is analyzed in this section, with a specific focus on the mode transition from mode 2 to mode 7. The transitions from mode 4 and mode 6 follow a similar process and are therefore omitted for brevity. At the initial time, it is assumed that the system is operating in mode 2, as illustrated in Figure 3b. The initial conditions are formulated as follows:

$$\left\{\begin{array}{c}\begin{array}{ccc}{V}_{C0}& =& 0V\\ V_{C2}& =& V_{PN}\end{array}\\ \begin{array}{ccc}{V}_{C4}& =& V_{PN}\\ V_{C6}& =& 0V\end{array}\end{array}\right.$$

(5)

The frequency-domain equivalent of the proposed SC-qH7 inverter is depicted in Figure 4, where the initial conditions of the system are represented by equivalent voltage sources. From Figure 4, the following mathematical equations are obtained:

$$\left\{\begin{array}{l}{I}_P\left(s\right)=I_A\left(s\right)+I_B\left(s\right)+I_C\left(s\right)\\ {\displaystyle \frac{I_P\left(s\right)}{s{C}_0}}+{\displaystyle \frac{I_A\left(s\right)}{s{C}_2}}=0\\ {\displaystyle \frac{I_A\left(s\right)}{s{C}_2}}-{\displaystyle \frac{I_B\left(s\right)}{s{C}_4}}=0\\ {\displaystyle \frac{I_C\left(s\right)}{s{C}_6}}-{\displaystyle \frac{I_B\left(s\right)}{s{C}_4}}={\displaystyle \frac{V_{PN}}{s}}\end{array}\right.$$

(6)

With the frequency-domain equivalents, the CMV of the proposed SC-qH7 inverter (V_CM(s)) when entering mode 7 is expressed as:

$$V_{CM}\left(s\right)=-{\displaystyle \frac{V_{PN}}{2s}}+{\displaystyle \frac{1}{3}}\left[\left({\displaystyle \frac{V_{PN}}{s}}+{\displaystyle \frac{I_A\left(s\right)}{s{C}_2}}\right)+\left({\displaystyle \frac{V_{PN}}{s}}+{\displaystyle \frac{I_B\left(s\right)}{s{C}_4}}\right)+\left({\displaystyle \frac{I_C\left(s\right)}{s{C}_6}}\right)\right]$$

(7)

By solving Equations (2) and (3), the CMV of the proposed SC-qH7 inverter (V_CM(s)) when entering mode 7 can be rewritten as:

$$V_{CMV}\left(s\right)=\left({\displaystyle \frac{C_0+C_2+C_4-C_6}{C_0+C_2+C_4+C_6}}\right){\displaystyle \frac{V_{PN}}{2s}}$$

(8)

Taking the inverse Laplace transform, we get:

$$V_{CMV}=\left({\displaystyle \frac{C_0+C_2+C_4-C_6}{C_0+C_2+C_4+C_6}}\right){\displaystyle \frac{V_{PN}}{2}}$$

(9)

When C₀ = C₂ = C₄ = C₆, the V_CMV under mode 7 is equal to V_PN/4.

Therefore, the CMV of the proposed SC-qH7 inverter only takes values of V_PN/3, V_PN/6, or V_PN/4. All the switching modes and the corresponding CMV of the proposed SC-qH7 inverter are given in Table 2. As highlighted in the table, the variation range of the CMV in the proposed topology is limited to just 16.6% of the DC-link voltage, representing a significant improvement compared to conventional inverter structures.

3. PWM Control Technique of SC-qH7 Inverter

Figure 5 illustrates the proposed PWM control strategy for the SC-qH7 inverter. Similar to the Discontinuous PWM (DPWM) technique, the proposed method utilizes three types of switching vectors: an odd active vector, an even active vector, and the zero vector V₇. If the final reference voltage is located in sector A₁, as presented in Figure 5a, the switching sequence will be (111)-(110)-(100)-(100)-(110)-(111). The complete switching pattern for each sector under the DPWM strategy for the SC-qH7 inverter is summarized in

Table 3. Switching pattern of the DPWM strategy for the SC-qH7 inverter.

Sector	Switching Sequence
A1	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_2$$\left(110\right)-{\overrightarrow{V}}_1$$\left(100\right)-{\overrightarrow{V}}_1$$\left(100\right)-{\overrightarrow{V}}_2$$\left(110\right)-{\overrightarrow{V}}_7$(111)
A2	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_2$$\left(110\right)-{\overrightarrow{V}}_3$$\left(010\right)-{\overrightarrow{V}}_3$$\left(010\right)-{\overrightarrow{V}}_2$$\left(110\right)-{\overrightarrow{V}}_7$(111)
A3	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_4$$\left(011\right)-{\overrightarrow{V}}_3$$\left(010\right)-{\overrightarrow{V}}_3$$\left(010\right)-{\overrightarrow{V}}_4$$\left(011\right)-{\overrightarrow{V}}_7$(111)
A4	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_4$$\left(011\right)-{\overrightarrow{V}}_5$$\left(001\right)-{\overrightarrow{V}}_5$$\left(001\right)-{\overrightarrow{V}}_4$$\left(011\right)-{\overrightarrow{V}}_7$(111)
A5	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_6$$\left(101\right)-{\overrightarrow{V}}_5$$\left(001\right)-{\overrightarrow{V}}_5$$\left(001\right)-{\overrightarrow{V}}_6$$\left(101\right)-{\overrightarrow{V}}_7$(111)
A6	${\overrightarrow{V}}_7$$\left(111\right)-{\overrightarrow{V}}_6$$\left(101\right)-{\overrightarrow{V}}_1$$\left(100\right)-{\overrightarrow{V}}_1$$\left(100\right)-{\overrightarrow{V}}_6$$\left(101\right)-{\overrightarrow{V}}_7$(111)

. The time durations of the voltage space vectors $\overrightarrow{V_1}$, $\overrightarrow{V_2}$, $\overrightarrow{V_3}$,$\overrightarrow{V_4}$, $\overrightarrow{V_5}$,$\overrightarrow{V_6}$, and $\overrightarrow{V_7}$ during a switching period are denoted as T₁, T₂, T₃, T₄, T₅, T₆, and T₇, respectively.

In sector A1, as illustrated in Figure 5 and Table 3, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors: $\overrightarrow{V_1}$, $\overrightarrow{V_2}$, and $\overrightarrow{V_7}$. Based on the volt–second balance principle, we derive the following:

$$T_{s\times }\overrightarrow{V_{ref}} =T_{1\times }\overrightarrow{V_1}+T_{2\times }\overrightarrow{V_2}+T_{7\times }\overrightarrow{V_7}$$

(10)

where T_s is the switching period.

The time durations of the voltage space vectors $\overrightarrow{V_1}$, $\overrightarrow{V_2}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_1=M_i\times T_s\times \sin \left({\displaystyle \frac{\pi }{3}}-\theta \right) \\ T_2=M_i\times T_s\times \sin \left(\theta \right) \\ T_7=T_s-T_1-T_2 \end{array}\right.$$

(11)

In the above equations, $M_i=\sqrt{3}{\displaystyle \frac{V_m}{V_{PN}}}$ represents the modulation index, where V_m is the magnitude of the reference voltage vector and V_PN is the DC-link voltage.

Similarly, in sector A2, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors $\overrightarrow{V_2}$, $\overrightarrow{V_3}$, and $\overrightarrow{V_7}$. The time durations of the voltage space vectors $\overrightarrow{V_2}$, $\overrightarrow{V_3}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_2=M_i\times T_s\times \sin \left(\theta +{\displaystyle \frac{\pi }{3}}\right) \\ T_3={ M}_i\times T_s\times \sin \left(\theta -{\displaystyle \frac{\pi }{3}}\right) \\ T_7={ T}_s-T_2-T_3 \end{array}\right.$$

(12)

Similarly, in sector A3, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors $\overrightarrow{V_3}$, $\overrightarrow{V_4}$, and $\overrightarrow{V_7}$. The time durations of the voltage space vectors $\overrightarrow{V_3}$, $\overrightarrow{V_4}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_3=M_i\times T_s\times \sin \left(\theta \right) \\ T_4=M_i\times T_s\times \sin \left(\theta -{\displaystyle \frac{2\pi }{3}}\right) \\ T_7=T_s-T_3-T_4 \end{array}\right.$$

(13)

Similarly, in sector A4, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors $\overrightarrow{V_4}$, $\overrightarrow{V_5}$, and $\overrightarrow{V_7}$. The time durations of the voltage space vectors $\overrightarrow{V_4}$, $\overrightarrow{V_5}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_4=M_i\times T_s\times \sin \left(\theta -{\displaystyle \frac{\pi }{3}}\right) \\ T_5=M_i\times T_s\times \sin \left(\theta -\pi \right) \\ T_7=T_s-T_4-T_5 \end{array}\right.$$

(14)

Similarly, in sector A5, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors $\overrightarrow{V_5}$, $\overrightarrow{V_6}$, and $\overrightarrow{V_7}$. The time durations of the voltage space vectors $\overrightarrow{V_5}$, $\overrightarrow{V_6}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_5=M_i\times T_s\times \sin \left(\theta -{\displaystyle \frac{2\pi }{3}}\right) \\ T_6=M_i\times T_s\times \sin \left(\theta +{\displaystyle \frac{2\pi }{3}}\right) \\ T_7=T_s-T_5-T_6 \end{array}\right.$$

(15)

Similarly, in sector A6, the reference voltage vector ($\overrightarrow{V_{ref}}$) is synthesized using the three vectors $\overrightarrow{V_1}$, $\overrightarrow{V_6}$, and $\overrightarrow{V_7}$. The time durations of the voltage space vectors $\overrightarrow{V_1}$, $\overrightarrow{V_6}$, and $\overrightarrow{V_7}$ can be calculated as:

$$\left\{\begin{array}{c}{T}_1=M_i\times T_s\times \sin \left(\theta +{\displaystyle \frac{\pi }{3}}\right) \\ T_6=M_i\times T_s\times \sin \left(\theta -\pi \right) \\ T_7=T_s-T_1-T_6 \end{array}\right.$$

(16)

The proposed SC-qH7 inverter under the proposed PWM control strategy offers the notable advantage of maintaining linear operation across the full range of the modulation index. A comparison of the CMV between the conventional H7 inverter and the proposed SC-qH7 inverter under the DPWM strategy in sector A₁ is also presented in Figure 5c. As shown in Figure 5b, during even active vectors and the zero vector V₇, switch S_a remains in the OFF state while switch S_b remains ON. Conversely, during odd active vectors, switch S_a is ON and switch S_b is OFF. Additionally, switch S₀ remains ON throughout the operation, except during vector V₇, where it is turned OFF. This switching scheme ensures that the CMV of proposed SC-qH7 inverter only takes values of V_PN/3, V_PN/4, or V_PN/6. As a result, the proposed SC-qH7 inverter retains all the inherent advantages of voltage source inverters (VSIs) operated under DPWM, such as reduced switching losses, low total harmonic distortion (THD) in the output current, and full modulation index range (0 ≤ M_i ≤ 1), while also offering the additional benefit of reduced CMV variation.

The power loss of the proposed SC-qH7 inverter topology can be categorized into losses from power switches, power diodes, and capacitors.

The conduction loss of the IGBT is calculated as:

$$P_{con}=V_{CEO}\times \overline{I_C}+I_{crms}^2\times R_c+V_D\times \overline{I_F}+I_{Frms}^2\times R_D$$

(17)

where $V_{CEO}$, V_D, R_c, R_D,$\overline{I_C}$, I_crms, $\overline{I_F}$, and I_Frms represent the voltage drop across the IGBT in saturation mode, the forward voltage of the antiparallel diode, the resistance of the IGBT, the forward conduction resistance of the antiparallel diode, the average value of the collector current of the IGBT, the RMS collector current of the IGBT, the average value of the current through the antiparallel diode, and the RMS antiparallel diode current, respectively.

The switching loss of the IGBT can be calculated as:

$$P_{sw}=(E_{ON}+E_{OFF})\times f_s$$

(18)

where $E_{ON}$, $E_{OFF}$, and f_s represent the Turn-ON energy loss of the IGBT, the Turn-OFF energy loss of the IGBT, and the switching frequency, respectively.

The power loss of diode can be calculated as:

$$P_{D }=Q_{rr}\times V_{Doff}\times f_s+V_{Don}\times \overline{I_{Don}}$$

(19)

where V_Don, V_Doff, $\overline{I_{Don}}$, and Q_rr are the forward voltage drop on the diode, the voltage across the diode, the reverse recovery charge of the diode, and the average value of the current through the diode, respectively.

The capacitor loss can be calculated as follows:

$$P_{Cap}=R_{cap}\times I_{caprms}^2$$

(20)

where $R_{cap}$, $I_{caprms}$, and f_s represent the equivalent series resistance of the capacitors and the RMS capacitor current, respectively.

4. Simulation and Experiment Results

4.1. Simulation Results

To validate the operating principles and evaluate the performance of the proposed SC-qH7 inverter, simulation studies were conducted using the PSIM 9.0 software environment. The key parameters used in the simulation are given as follows. The switching frequency and the fundamental frequency were 10 kHz and 50 Hz, respectively. The two capacitors C_a and C_b were both selected as 220 µF. The DC input voltage was set to 100 V, and the stray capacitor was 300 nF. The capacitances of the additional capacitors (C₀−C₆), as show in in Figure 2, were each set to 1 nF. An inductive load with R_l = 27 Ω and L_l = 25 mH was used.

Figure 6 presents the simulation waveforms of the proposed SC-qH7 inverter, including the input voltage, the voltages across capacitors C_a and C_b, the DC-link voltage, the voltage stress across switches S_a and S_b, and diodes D_a and D_b, as well as the output line-to-line voltage, output phase voltages, and their corresponding FFT analysis. As highlighted in Figure 6, the DC-link voltage V_PN reached a steady-state value of 200 V, which was twice the input DC voltage. The voltage across capacitors C_a and C_b were each maintained at the input DC voltage level. The voltage stress across both switches (S_a, S_b) and both diodes (D_a, D_b) was observed to be equal and limited to the input voltage, confirming the reduced stress advantage of the design. As also shown in Figure 6, the inverter generated a unipolar output line-to-line voltage waveform. The output phase voltage achieved an amplitude of approximately 115 V with a modulation index M = 1. The corresponding output phase currents were sinusoidal and free from noticeable distortion. The amplitude of the output phase current was 4 A, and the THD was measured to be approximately 0.8%, demonstrating excellent power quality performance.

Figure 7 presents the simulation waveforms of the common-mode voltage and the phase voltages with respect to the negative DC terminal, i.e., the voltages between nodes A–O, B–O, and C–O, for the proposed SC-qH7 inverter. The figure also includes a zoomed-in view to clearly illustrate the CMV variation during the different operating modes. As shown in Figure 7b, during the powering modes, the CMV took discrete values of 66.6 V or 33.3 V, while during the freewheeling mode, the CMV stabilized at 50 V. These results confirm that the CMV remained bounded between 33.3 V and 66.6 V, consistent with the theoretical expectations. Consequently, the total variation in CMV was limited to 33.3 V, which corresponds to one-sixth of the DC-link voltage, demonstrating the effectiveness of the proposed SC-qH7 inverter in reducing CMV fluctuations. The waveform of the common-mode voltage across the stray capacitor C_PE appeared as highlighted in Figure 8. This low CMV level contributes to a reduced leakage current in the proposed SC-qH7 inverter.

To further evaluate the inverter’s performance under varying operating conditions, the input voltage was increased to 160 V and 200 V, while the modulation index was decreased to 0.6 and 0.4, respectively. Figure 8 displays the stray capacitor voltage, corresponding leakage current, and their frequency spectra at different modulation indices. As shown in Figure 8, the higher-order harmonic components of the stray capacitor voltage remained very low across all tested conditions. The rms value of the leakage current was approximately 4 mA when M = 1 and V_dc = 100 V (Figure 8a). When the modulation index was reduced to 0.6 and the input voltage was increased to 160 V, the leakage current increased slightly to 6 mA (Figure 8b). At a further reduced modulation index of 0.4 with an input voltage of 200 V, the leakage current remained modest at 12 mA (Figure 8c). These results confirm that the proposed SC-qH7 inverter can operate across the full modulation index range while maintaining low leakage current levels, demonstrating its suitability for transformerless applications.

4.2. Experimental Results

In order to confirm the effectiveness of the proposed SC-qH7 inverter, a 1 kW laboratory prototype was constructed and tested. The modulation algorithms were implemented using a TMS320F28379D digital signal processor manufactured by Texas Instruments, Dallas, TX, USA, while a DE0-Nano FPGA manufactured by Intel Corporation Santa Clara, CA, USA was employed to handle logic control functions. The parameters used for the experimental setup were identical to those used in the simulation to ensure consistency in performance evaluation. For power switching, two IRFP4668PbF MOSFETs with a voltage rating of 200 V were used for switches S_a and S_b. The six H-bridge switches, along with the additional switch S₀, were implemented using IPW60R045CPA MOSFETs. These eight MOSFETs were manufactured by Infineon Technologies, Neubiberg, Germany. Additionally, two STPS60SM200C Schottky diodes manufactured by STMicroelectronics, Geneva, Switzerland, with low voltage ratings were used for the freewheeling diodes D_a and D_b.

Figure 9 presents the experimental waveforms of the proposed SC-qH7 inverter, including the input voltage, voltages across capacitors C_a and C_b, voltage stress across switches S_a and S_b and diodes D_a and D_b, output line-to-line voltage v_AB, output phase-A voltage, three-phase output currents, and the FFT of the output phase-A current. As shown in Figure 9a, the steady-state voltages across capacitors C_a and C_b were 98 V and 95 V, respectively. These values were slightly lower than the input voltage due to parasitic elements present in the experimental hardware. The observed low-frequency peak-to-peak ripple voltages were approximately 4 V for C_a and 6 V for C_b. Figure 9b shows that the voltage stress on switches S_a and S_b was identical at 99 V, while the voltage stresses across diodes D_a and D_b were 98 V and 95 V, respectively. Figure 9c confirms that the inverter generated a unipolar output line-to-line voltage waveform. As shown in Figure 9d, the output phase currents were sinusoidal and free from noticeable distortion. The measured amplitude of the output phase current was 4 A, and the THD was approximately 1.05%, validating the inverter’s high-quality output performance. The measured efficiency of the proposed SC-qH7 inverter reached approximately 90.8% when Mi = 1 at a output power of 700 W. However, the efficiency of the proposed SC-qH7 inverter was relatively low due to the use of non-optimal components in the experimental setup.

Figure 10 shows the experimental waveforms of the common-mode voltage and the voltages between nodes A-O, B-O, and C-O, along with their zoomed-in views. As shown in Figure 10a, the CMV during the powering modes took discrete values of approximately 65 V or 32 V, while it stabilized at 50 V during the freewheeling mode. This confirms that the CMV remained constrained within the expected range of 32 V to 65 V.

Figure 11 illustrates the experimental waveform of the CMV across the stray capacitor C_PE, along with the corresponding leakage current. The experimental results are in good agreement with the simulation results, validating the accuracy of the proposed inverter model. It can be observed that the SC-qH7 inverter effectively limited the CMV variation, particularly during transitions into and out of mode 7. This suppression of the CMV contributed to a significantly reduced leakage current. As shown in Figure 11, the rms value of the leakage current was approximately 13.5 mA. Therefore, the proposed SC-qH7 inverter effectively limited the leakage current to a level well below 300 mA, as specified in the standard VDE-0126-1-1 [22].

5. Conclusions

In this paper, a novel three-phase two-level DC–AC inverter with low common-mode voltage, CMV, referred to as the SC-qH7 inverter, was proposed, analyzed, simulated, and experimentally validated. By integrating a voltage multiplier network into the conventional H7 inverter topology, the proposed structure achieves a DC-link voltage that is twice the input DC voltage. As a result, the SC-qH7 inverter is capable of operating in both buck and boost modes. The inverter generates a unipolar output line-to-line voltage, which reduces the voltage stress across the output filter inductor. This leads to a more compact filter design and lower power losses. Compared to conventional topologies, the SC-qH7 inverter exhibits a significantly reduced CMV, with its magnitude limited to only 16.6% of the DC-link voltage. Furthermore, the voltage stress across the additional switches in the voltage multiplier network is limited to half of the DC-link voltage, enhancing device reliability. The voltage across the stray capacitor remains low, which effectively suppresses the resulting leakage current. Simulation and experimental results confirm that the leakage current remains below 13.5 mA. Additionally, the output current THD is measured at only 1.05%, demonstrating excellent power quality. These features make the proposed SC-qH7 inverter a promising and efficient solution for three-phase transformerless photovoltaic (PV) systems. Because two capacitors in the switched-capacitor network suffer impulse charging current, the selection of the capacitors needs to meet the requirements of reliability and size of the power converter. The reliability and lifetime of the capacitors are calculated based on the switching frequency and spectral content of the impulse current through the capacitor. The size and type of the capacitor are calculated based on the level of harmonics and the lifetime of the capacitor.