GaN Power Transistors in Converter Design Techniques

Abstract

The expected outstanding performance of GaN-based transistors in power applications, characterized by high switching frequency, efficiency, and compactness, requires that the design rules of converter layout optimization, filtering, and shielding need to be reexamined. Addressing the above topics, this paper reviews commercial GaN power transistors and specifies their integration techniques, including printed circuit board (PCB) embedded solutions. Then, referring to the optimization results of a half-bridge inverter leg, design techniques are presented that reduce the harmful effect of inductive and capacitive internal converter couplings, thus mitigating the electromagnetic interference (EMI) conducted emissions.

1. Introduction

Gallium nitride (GaN) based power devices are becoming a competitive technology to design power electronic converters operating at higher frequencies, and revealing higher efficiency and compactness. In view of increasing requirements for high-efficiency energy conversion, two wide bandgap (WBG) semiconductor types can be distinguished: GaN and silicon carbide (SiC), regarded as silicon (Si) successors. Their advantageous properties can be derived from the comparative physical data depicted as the pentagon diagram in Figure 1 [1,2].

What is remarkable in the diagram, very high values of critical electric field E_c > 3 MV/cm and energy bandgap E_g > 3 eV, can be observed for GaN material, which makes designing power devices for specific voltage breakdown and operation at higher temperatures easier using this material than Si. Moreover, high values of electron mobility µ_n reaching 1500 cm²/Vs and electron saturation velocity v_sat ≈ 24 cm/µs [2] reduce the die size, decreasing, as a consequence, terminal capacitances, providing the lower switching loss and the lower on-resistance, related with the lower on-state loss [3]. To evaluate materials potential impact on device operation quality, several figures of merit (FOMs) have been developed in [4,5]. Based on the data derived from [1], the selected FOMs have been recalculated and normalized using the Si data set in

Table 1. Comparative indicators of FOMs for semiconductor materials: Si, 4H-SiC, and GaN.

Material	HMFOM	HCAFOM	HTFOM
Si	1.00	1.00	1.00
4H-SiC	5.26	31.99	0.47
GaN	11.56	96.67	0.12

.

where HMFOM indicates a total conduction and switching loss reduction potential

$$HMFOM=E_c\sqrt{{\mu }_n}$$

(1)

HCAFOM depicts a die size reduction potential, and

$$HCAFOM=\epsilon E_c^2\sqrt{{\mu }_n}$$

(2)

HTFOM represents a thermal performance corresponding to junction temperature rise

$$HTFOM={\displaystyle \frac{{\sigma }_{th}}{\epsilon E_c}}$$

(3)

Based on the analytical assessment in Table 1, the greatest reductions in total power loss and die size can be achieved with GaN semiconductors, enabling mass and volume reduction in GaN-based power converters. However, their thermal performance is significantly worse, suggesting the need to design high-efficiency converter topologies.

The GaN and SiC based devices also expand the power region and operation frequency of Si MOSFETs, IGBTs, and Superjunction Si MOSFETs, as shown in Figure 2 [2]. In 2023, the market size of global GaN power devices was around USD 271 million, and it is projected to grow to USD 4.376 billion by 2030 at a compound annual growth rate (CAGR) of 49% [6]. Based on the Infineon 2025 predictions [7], more and more applications for power conversion are expected after deploying GaN-based devices in the voltage range of up to 700 V and beyond. The EU’s mandate for USB-C chargers, adapters, home appliances, and incentives for renewable energy technologies, including residential solar and energy, along with the demand for high-efficiency on-board chargers for hybrid and electric vehicles, allow us to expect the imminent development of GaN-based converters.

In recent years, many review papers have summarized various aspects of GaN power devices, including reliability issues [8,9,10], technologies increasing the threshold voltage [11], advances of vertical structures [12,13,14,15], along with presenting general and application-oriented overviews [2,3,16,17,18]. However, the fast-switching operation of GaNs in power converters results in high voltage dv/dt and current di/dt derivatives, which increase EMI perturbations and switching power loss. To mitigate these harmful switching effects, various design issues and precautions have been elaborated.

To reduce EMI at source, active gate drivers were developed [19] to adapt voltage derivatives to load conditions, optimizing the trade-off between high-frequency operation and switching power loss. However, some solutions [20] rely on complex system-on-chip (SoC) hardware with analog-to-digital (A/D) conversion for transistor current measurement.

An alternative methodology involves using EMI filters, designing snubber circuits [21,22], or employing other damping techniques through inductively coupled circuits with optimized damping resistances [23,24]. For effective suppression of commutation ringing, these solutions require precise wide-band converter parameter identification, which is challenging due to load changes or aging phenomena.

Additionally, to limit switching power loss, soft switching converter topologies have been developed, albeit at the expense of increased controller complexity and additional auxiliary elements [18,25,26].

Another design objective reexamined in this paper is the minimization of parasitic elements that primarily impact EMI issues, achieved by focusing on converter construction, printed circuit board (PCB) layout optimization, and shielding techniques. Addressing the above topics, this paper reviews commercial GaN power transistors and specifies their integration techniques, including printed circuit board (PCB) embedded solutions [27,28,29]. Then, referring to the results obtained in [30], case study design techniques for a half-bridge inverter leg are presented, which reduce the harmful effect of inductive and capacitive internal converter couplings, thus mitigating the EMI conducted emissions.

2. Classification of GaN Power Devices

Owing to low technological maturity and high cost of native GaN substrates, the majority of current commercial GaN devices are lateral and are epitaxially deposited on a wafer of Al₂O₃ (sapphire), SiC, or Si [31]. The basic lateral structure incorporates a layer of AlGaN on top of the GaN, creating a heterojunction between these two layers. The positive net charge at the AlGaN/GaN junction due to the polarization effect attracts free electrons from the material to achieve charge neutrality. The accumulation of a large number of free electrons in the junction forms a high mobility, high density electron channel, known as a two-dimensional electron gas (2DEG) [3,17,32]. The device is specified as a high electron mobility transistor (HEMT). Due to the native 2DEG channel, it is a depletion-mode normally on HEMT with a negative threshold voltage. To attain normally off operation, preferred for security in power applications, two commercially developed techniques of enhancement mode (e-mode) and hybrid transistors are widely exploited [3].

2.1. E-Mode GaN HEMTs

The efficient techniques for e-mode GaN HEMTs have been developed by modifying the gate region to shift the threshold voltage to a positive value, V_GS(th) > 0. In the p-GaN gate transistor, a p-doped layer is deposited under the gate terminal to obtain a fixed negative charge at the junction with the AlGaN layer. At the zero gate voltage, V_GS, this negative charge depletes the 2DEG under the gate terminal, and the drain current I_D cannot flow, as is depicted in Figure 3. The positive voltage V_GS > V_GS(th)) enhances the 2DEG and completes the channel.

The metal gate of the p-GaN HEMT forms the ohmic or Schottky contact with the p-GaN layer [11]. The gate structure with ohmic contact of the gate injection transistor (GIT) contains the p-AlGaN layer over the undoped AlGaN/GaN heterojunction. The increase in the gate voltage over the built-in voltage of the p-n junction results in the hole injection to the channel from the p-AlGaN layer, causing the constant gate source leakage current I_GSS of several milliamps to flow into the gate at steady-state. This intentional injection of minority carriers enhances the conductivity of the 2DEG, reducing, as a consequence, the on-state resistance R_ds(on). However, to achieve fast switching transients and low R_ds(on), dedicated gate drivers are recommended.

In order to reduce I_GSS and increase the gate forward voltage, a reverse-bias Schottky contact is formed in the structure of the p-GaN gate transistor, also known as the Schottky gate transistor. The operation of the p-GaN gate transistor is similar to that of the GIT transistor. However, by applying a positive gate-source voltage, the Schottky diode is reverse-biased and conducts a small leakage gate current. Therefore, gate control is compatible with most of the drivers for silicon MOSFETs, and such a structure is mostly used for commercially available e-mode GaN HEMT devices [3].

Typical parameters of the selected commercially available e-mode GaN HEMTs of the 650 V/60 A power series are gathered in

Table 2. Parameters of selected 650 V/60 A e-mode GaN HEMTs of for T_j = 25 °C.

Device	Manufacturer	RDS(on) [mΩ]	QG [nC]	VGS(th) [V]	IGSS [mA]	Topology
IGT65R025D2	Infineon	25	11	0.9–1.6	46	GIT 1
GS0650605BA	GaN Systems	25	14	1.1–2.6	0.32	p-GaN
INN650TA030AH	Innoscience	26	16	1.2–2.5	0.25	p-GaN

¹ Gate injection transistor.

. Their common feature is that the V_DS rating is limited to 650 V. However, finite engineering samples are offered with the breakdown drain-source voltage shifted to 1200 V [33]. Other e-mode GaNs’ features are as below:

• Ultra-fast switching;
• Zero reverse-recovery charge Q_RR;
• Low gate charge Q_G and output charge Q_OSS;
• Reverse conduction capability;
• Strong on-resistance temperature dependence.

2.2. Hybrid Transistors

The hybrid transistor topologies shown in Figure 4 represent alternative methods to ensure safe switching of depletion-mode GaN HEMTs in power converters.

The cascode hybrid transistor consists of the d-mode GaN HEMT connected in series with the low-voltage normally off Si MOSFET, where the gate terminal of the HEMT transistor is connected to the source terminal of the MOSFET. When the MOSFET is turned on, its V_DS tends to zero, turning on the HEMT. Similarly, during the MOSFET turn-off process, its V_DS voltage increases, which turns the HEMT off. Thus, the cascode hybrid transistor operates in a way similar to the Si MOSFET with positive V_GS(th). In the on-state, both transistors conduct the same current, while in the off-state, the GaN HEMT blocks the major part (>90%) of the drain voltage. Therefore, it is possible to use a low-voltage Si MOSFET possessing low R_DS(on) and high switching time [34]. What is noteworthy, this configuration does not need connecting the source to the substrate for potential augmentation of voltage breakdown up to 1200 V [35].

The parameters of the selected, commercially available cascode GaN HEMTs are gathered in

Table 3. Parameters of selected hybrid GaN HEMTs of V_DS = 650 V for T_j = 25 °C.

Device	Manufacturer	RDS(on) [mΩ]	QG [nC]	VGS(th) [V]	ID/IDM [A]	Topology
TP65H035G4QS	Renesas	35	22	4	46/240	Cascode
GAN039650NBB	Nexperia	33	26	3.9	58/234	Cascode
LMG3522R030	Texas Inst.	26	-	-	55/125	Direct drive

. Typical features are summarized as below:

• V_GS(th) set by the Si MOSFET independent of the d-mode GaN HEMT;
• Standard-level MOSFET drivers can be used;
• High immunity to drain voltage gradients dv/dt;
• Enhanced inrush current capability;
• Low gate charge Q_G and output charge Q_OSS;
• Reverse conduction capability;
• Very low reverse-recovery charge Q_RR.

In the direct drive configuration, both transistors are connected in series. Here, the d-mode GaN HEMT is controlled directly from the gate driver. Since the Si MOSFET is always on, its body diode does not turn on due to low R_DS(on). As a result, there are no Q_rr-related power losses in the direct-drive configuration. Moreover, during normal operation, fast switching capabilities of the d-mode GaN HEMT can be fully exploited, including slew rate control by using the gate current. In the case of a power supply fault, when the driver cannot turn off the GaN HEMT, the under-voltage lockout (UVLO) protection turns off the Si MOSFET to anticipate a short circuit in the converter [36]. The parameters of the selected commercially available hybrid transistors are enclosed in Table 3.

2.3. Bidirectional GaN Transistors

The lateral structure of GaN HEMTs enables monolithic integration of two transistors to form a bidirectional switch on a single chip possessing two gates and two sources with a shared drain region. The main objective of bidirectional switches required for power electronics applications is a four-quadrant operation for bidirectional current conduction in the on-state, and bipolar voltage blocking in the off-state [37]. In such a device, parasitic inductances are minimized, and the common low-resistive drift channel length is similar to that of a single GaN HEMT.

Navitas Semiconductor Ltd. offers a commercially available normally off dual gate bidirectional switch, NV6428 [38]. Assuming different potentials S1 and S2 of the source terminals, this switch requires two floating gate (isolated gate) driver channels. As a four-quadrant switch, it is capable of blocking the voltage in either or both directions, and conducting the current in either or both directions, depending on the states of G1 and G2, as in Figure 5.

To assure bipolar voltage blocking with simultaneous unidirectional current conduction, the single gate control is sufficient. In this case, the other gate can be connected with the low-voltage silicon Schottky diode using a cascode configuration [39]. Alternatively, in the single-gate bidirectional GaN HEMT (produced, e.g., by Innoscience (Suzhou, China), Nexperia (Nijmegen, The Netherlands)), the transistor channel, due to its symmetry, has two terminals that can be assigned to the drain or to the source. However, to block the reverse current, the voltage across the transistor cannot exceed the threshold for conduction in the reverse direction. This might involve additional circuit design considerations, making use, for instance, of external diodes or other components to prevent the reverse current flow [40]. Selected data of bi-directional GaN HEMTs are put in

Table 4. Selected data of bidirectional e-mode GaN HEMTs for T_j = 25 °C.

Device	Manufacturer	RDS(on) [mΩ]	QOSS [nC]	VDS [V]	ID/IDM [A]	Topology
NV6428	Navitas	52	100	650	49/78	Dual gate
INV120EQ035A	Innoscience	3.5	95	120	100/320	Single gate
GANB4R8-040	Nexperia	4	12.2	40	20/100	Single gate

.

2.4. Vertical GaN Transistors

Vertical GaN power transistors have an internal structure similar to their Si and SiC counterparts, where the current flows from the drain to the source across a vertical drift layer. Vertical GaN devices, with a thicker drift layer, feature a higher breakdown voltage, current capability, and heat dissipation for a given chip area, compared to the thin channel layer of lateral HEMTs. Several types of vertical GaN devices have already been developed in laboratory conditions [13]. These include Schottky barrier diodes [12] and p-i-n GaN-on-Silicon diodes [41]. The primary transistor types include the current aperture vertical electron transistors (CAVET) and the vertical GaN MOSFETs [14]. The industrial fabrication of vertical GaN devices is expected in near future.

3. GaN Integration Techniques

Fast switching capability of high voltage GaN transistors creates challenging design integration solutions to minimize gate and power loop inductances, in order to mitigate harmful EMI resulting from the converter switching operation. Moreover, due to a very low threshold voltage of e-mode GaNs, the reduction of gate wire bonding improves their immunity to turn-on events during high drain-source voltage gradients.

An additional outcome of using the integrated circuits is the increased power density and efficiency. The techniques reported in the literature and commercially available integrated techniques are adapted to converter power ratings and applications.

The issue of integration is relevant in monolithically integrated single-gate driver circuits with GaN transistors on a single substrate and in co-packaged silicon gate drivers placed on the same die-attach-pad with GaNs. These integrated circuit (IC) power chips are equipped with different security functions, including overtemperature, overcurrent, and undervoltage protections [42]. More advanced structures integrate complete fundamental power stage blocks, as is the half-bridge topology [43], which consists of high- and low-side GaN switches, a level shifter for ground-referenced PWM signals, a bootstrap to drive high-side circuits, and other functions depicted in Figure 6. Its fully monolithic implementation was designed to operate as a buck converter of up to 2 MHz with input of up to 80 V and output of 10 A.

There is a continuous progress reported in design solutions of gate drivers for half-bridge integration. Challenges posed by common-mode transient immunity and negative voltage operation in level shifting during the dead time conduction are considered in [44]. Another approach is based on isolated gate drivers utilizing an on-chip coreless transformer to achieve signal-level shifting to the high side. This integrated power stage (IPS) is encapsulated with two GaN HEMTs in a small 8 × 8 mm package [45]. A few examples of Si gate drivers integrated with the single e-mode GaN or the two GaNs half-bridge IPS are gathered in

Table 5. Selected data of IPSs utilizing e-mode GaN HEMTs for T_j= 25°C.

Device	Manufacturer	RDS(on) [mΩ]	dv/dt [V/ns]	VDS [V]	ID/IDM [A]	Topology
BM3G005MUVLB	ROHM	50	150	650	21/68	Single HEMT
NV6522	Navitas	40	100	650	41/83	Single HEMT
EPC2152	EPC	2 × 10	-	80	15/-	Half-bridge
IGI60F1414A1L	Infineon	2 × 140	300	600	6/23	Half-bridge

.

Despite the advanced assembly of IPSs, some indispensable interconnections to external decoupling capacitors of the gate supply or the dc-link rail are needed. To limit parasitic inductances, PCB embedding with the placement of on-package decoupling capacitors is proposed [28], as in Figure 7. Another analytical treatment of the PCB-embedded GaN modules in terms of electrical and thermal performance is presented in [29].

4. Half-Bridge Implementation Case Study

The implementation case study has been focused on the example of a half-bridge inverter leg based on lateral e-mode GaN HEMTs, as in Figure 8 [30]. The inverter is supplied from a DC voltage source, V_i = 250 V, through the line impedance stabilization network LISN. Two input capacitors divide the voltage into V_i/2 to create a 0 V midpoint connection for the load. The operation frequency has been set at f_s = 250 kHz. The inverter is feeding the resistive–inductive load L-R_load. Power loop inductance is represented by the bus bar inductances L_s+/L_s−. The layout of stray capacitances is marked red, including the main common mode capacitance C_CM at the inverter output midpoint. To limit the CM current circulation path through the load circuit, the CM filter L_CM is inserted at the inverter output. The inverter utilizes a four-layer PCB to provide a high level of integration between discrete components and PCB copper layers (planes, polygons), vias, and tracks [46]. The three tested design techniques adopting the top-side cooled e-mode GaNs are discussed below.

4.1. Power Loop and Gate Loop Inductances

The power loop inductance is a sum of the bus bar stray inductances L_{s+ and} L_s−, the common source inductances L_s, the equivalent series inductance ESL of the decoupling capacitor, and mutual inductances between them [47]. The power loop inductance should be minimized to limit overvoltage at the transistor turn-off transient. The gate circuit inductance L_g generates the gate-source overvoltage and should also be minimized. Due to the common source inductances of the transistors, the drain current and the gate current pass through the same conductor, generating disturbances in the gate circuit and increasing the switching energy [48]. The coupling between the drain circuit and the gate circuit is to be minimized by using short distances to the gate driver and a small loop surface of the gate circuit.

4.2. The Impact of Stray Capacitance

The gate circuit should be robust against false turn-on faults resulting from the Miller capacitance C_dg at high drain-source voltage gradients dv_DS/dt. When applied to the gate, the negative voltage in the turn-off state improves the gate immunity to the Miller effect. The common mode capacitance C_CM, between the switching node potential and the ground, represents a number of distributed capacitances, including the thermal pad capacitance that is enlarged by the grounded heat sink placement [49]. Since high voltage gradients, dv/dt of the switching node, generate CM currents, the design effort is to minimize C_CM. Other stray capacitances: C+ and C− between the bus bars, potentials DC+ and DC−, respectively, and the ground, provide recycling of CM currents inside the switching cell, hence, they should be increased, while still remaining symmetric to avoid differential mode (DM) coupling and CM noise.

4.3. Planar 2D Layout of PCB

The planar 2D layout configuration of the PCB is illustrated in Figure 9. Two transistors are soldered at the top of the PCB. Heat dissipation is realized by a heat sink mounted directly on both devices. To reduce the power loop area, decoupling capacitors C_decoup are placed beneath the inverter leg on the same side of the PCB. Also, the layouts of the DC+ plane (red) and the DC− plane (blue) provide a symmetrical and reduced power loop. The half-bridge isolated gate driver is mounted close to the transistor. The gate circuits consist of two branches with resistors R_on and R_off and diode D_off to separately tune the turn-on and turn-off transients. The inverter middle point track is implemented by two PCB middle layers (orange and cyan) of the same geometry, connected by vias to increase the current capability of the converter. With the aim of attenuating the CM current emission, the middle point track shielding is applied by extending the surfaces of the DC+ and DC− bus bar planes. The application of shielding results in internal recycling of CM noise at the cost of an increase in capacitances between the drain and source terminals of the switching transistors [30,50,51].

4.4. 2.5D Power Chip-on-Chip Layout of PCB

Figure 10 shows the 2.5D power chip-on-chip (PCoC) layout schematic [30,52]. Two GaN HEMTs, mounted “in mirror” on the top and bottom sides of the PCB, are connected directly to the DC+ and DC− bus bars. The inverter middle point track is arranged in the same way as previously in the inner layers of the PCB. The decoupling capacitors are placed close to the transistors, on each side of the PCB. The power loop area is smaller, since it is almost embedded inside the PCB thickness.

4.5. 3D Power Chip-on-Chip Layout of PCB

After recording the initial results of the 2D and 2.5D concepts, a full PCoC 3D layout was designed as in Figure 11. In this configuration, the decoupling capacitors were mounted vertically in dedicated holes within the multilayer PCB, positioned on the left and right sides of the transistor locations. As before, the implementation is based on a four-layer PCB with two GaN HEMTs, mounted in a “mirror” arrangement on the top and bottom sides of the PCB. This design further reduces the power loop area compared to the 2.5D layout. Additionally, due to the capacitors’ placement, the number of vias and the overall volume of the circuit assembly were minimized. However, when utilizing the 2.5D or the 3D layout techniques, heat sinks must be installed on both sides of the PCB.

4.6. Simulation Results

Table 6. Power loop stray inductances of the half-bridge inverter leg (simulation results).

Layout	2D	2.5D	3D
Stray inductance @ 1 MHz	8.9 nH	7.56 nH	1.93 nH
Stray inductance @ 10 MHz	4.83 nH	4.69 nH	1.49 nH
Stray inductance @ 100 MHz	6.94 nH	5.46 nH	1.57 nH

compares the power loop stray inductances for the considered layout configurations, calculated with the Ansys Q3D extractor. It is evident from the data presented that the power loop inductance is the lowest for the full 3D layout. It is to be noted that the data in the table do not include internal parasitic inductances of the transistor package (in a range of 0.4 nH for each GaN HEMT).

4.7. Experimental Validation

The experimentally measured current noise spectra of the shielding boards for 3D and 2D layout configurations are compared in Figure 12. For the 3D PCoC layout, slightly better attenuation of the CM current spectral envelope is obtained in the whole frequency range. For the DM current, the noise attenuation improvement for the 3D layout is even more significant, except for the frequency range between 2 and 10 MHz, where the 2D solution is more effective.

Figure 13 illustrates the half-bridge inverter setup with a zoom on the four-layer PCB planar 2D layout of GaN HEMTs (2xGS66506T), assuring close connection to the isolated gate driver (Si827x). The decoupling capacitors (6 × 100 nF) are placed in two stacks at the bottom side of the PCB package, under the transistors. In order to minimize CM capacitive coupling of the gate driver power supply, the battery board of the batteries is mounted perpendicular to the main board.

Figure 14 depicts the oscilloscope record of the half-bridge inverter’s steady-state operation. All four consecutive conduction states (with subperiods of bidirectional current conduction of GaNs), being the result of the resistive–inductive load, are present. The zooms of voltage waveforms at turn-off transients show the significantly reduced voltage overshoots, validating the design layout with minimized power loop stray inductance.

Throughout this study on half-bridge inverter operation, the impact of reducing power loop inductance on transistor V_DS voltage overshoot and switching oscillation attenuation has been demonstrated. As a result, CM noise can also be reduced. Furthermore, it has been shown that decreasing the parasitic capacitance between the inverter leg’s midpoint and the ground potential directly mitigates CM noise generation. The newly proposed shielding approach—utilizing the positive or negative bus bar planes—enables internal recycling of CM noise, leading to a total reduction of over 17 dB in CM emission at the inverter input.

5. Conclusions

Gallium nitride (GaN) based power devices are becoming a competitive technology to design power electronic converters operating at higher frequencies and revealing higher efficiencies and compactness. Owing to energy savings, the adoption of GaN power switches is particularly attractive to supply AI data centers, 5G power stations, automotive chargers, or USB-C chargers and adapters. The majority of current commercial GaN transistors are e-mode lateral structure GaN HEMT devices or d-mode GaN HEMTs in hybrid configuration with low voltage Si MOSFETs for the voltage range of up to 700 V and beyond. Due to a low-resistive channel and four-quadrant operation, the emerging bidirectional GaN transistors formed by monolithic integration of two transistors are expected to support the next generation of grid converters and traction inverters.

The increase in the GaN operation switching frequency to the MHz range means that the design of the power layout becomes a key step to build an effectively working converter. The limitation of voltage overshoots and commutation oscillations, assuring low EMI emission, requires sub-nanohenry power loop and gate loop inductances. The half-bridge implementation case study underlined the importance of packaging GaN devices with PCB embedded technologies, including power chip-on-chip 3D concepts to minimize stray inductances.

The minimization of the common mode capacitance C_CM, representing a number of distributed stray capacitances between the inverter middle point track and the ground, is crucial for CM interference attenuation. However, for recycling the CM currents inside the switching cell, the stray capacitances C+ and C− between the bus bars and the ground should be increased, while still remaining symmetric to avoid coupling of DM and CM noise.

The application of local shielding techniques to the inverter middle point track, thermal pads, and gate power supplies increases the recirculation of CM currents within the converter, which leads to further reduction of CM noise. Moreover, to block the CM current circulation path through the load circuit, a CM filter L_CM (integrated inductor) should be inserted between the inverter middle point track and the load circuit.